level-sensitive scan design

{{Short description|Part of an integrated circuit manufacturing test process}}

{{Unreferenced|date=March 2022}}

{{redirect|LSSD|the school district in Tennessee|Lebanon Special School District}}

Within the field of electronics Level-sensitive scan design (LSSD) is part of an integrated circuit manufacturing test process. It is a DFT scan design method which uses separate system and scan clocks to distinguish between normal and test mode. Latches are used in pairs, each has a normal data input, data output and clock for system operation. For test operation, the two latches form a master/slave pair with one scan input, one scan output and non-overlapping scan clocks A and B which are held low during system operation but cause the scan data to be latched when pulsed high during scan.

____
|    |
Sin ----|S   |
A ------|>   |
|   Q|---+--------------- Q1
D1 -----|D   |   |
CLK1 ---|>   |   |
|____|	  |    ____
|   |	   |
+---|S   |
B -------------------|>   |
|	  Q|------ Q2 / SOut
D2 ------------------|D   |
CLK2 ----------------|>   |
|____|

In a single latch LSSD configuration, the second latch is used only for scan operation. Allowing it to be used as a second system latch reduces the silicon overhead.