multi-cycle processor

{{Wikibooks|Microprocessor Design|Multi Cycle Processors}}

A multi-cycle processor is a processor that carries out one instruction over multiple clock cycles, often without starting up a new instruction in that time (as opposed to a pipelined processor).{{Cite book|title=Digital Design and Computer Architecture ARM Edition|last=Harris|publisher=Elsevier|year=2016|isbn=978-0-12-800056-4|at=sec. 7.3-7.5}}{{Cite web |title=Multi-cycle MIPS Processor |url=https://syssec.ethz.ch/content/dam/ethz/special-interest/infk/inst-infsec/system-security-group-dam/education/Digitaltechnik_14/21_Architecture_MultiCycle.pdf |website=System Security Group, ETH Zurich |publisher=ETH Zurich |location=Zürich, Switzerland}}{{Cite web |title=Lecture 9: Processor design – multi cycle |url=https://www.inf.ed.ac.uk/teaching/courses/inf2c-cs/13-14/lectures/lec09-slides.pdf |website=School of Informatics :The University of Edinburgh |publisher=University of Edinburgh |location=Edinburgh , Scotland |access-date=2020-07-20 |archive-url=https://web.archive.org/web/20170808000955/http://www.inf.ed.ac.uk/teaching/courses/inf2c-cs/13-14/lectures/lec09-slides.pdf |archive-date=2017-08-08 |url-status=live }}{{Cite web |title=ESE 545: Computer Architecture: Designing a Multicycle Processor |url=http://www.ece.sunysb.edu/~midor/ESE545/CA_Multicycle%20processor%20design.pdf |website=Electrical and Computer Engineering - Stony Brook University |publisher=Stony Brook University |location=Stony Brook, New York |access-date=2020-07-20 |archive-url=https://web.archive.org/web/20180516185250/http://www.ece.sunysb.edu/~midor/ESE545/CA_Multicycle%20processor%20design.pdf |archive-date=2018-05-16 |url-status=live }}