repeat instruction
{{short description|Machine instruction executing another instruction repeatedly}}
{{Machine code}}
In computer instruction set architectures (ISA), a repeat instruction is a machine language instruction which repeatedly executes another instruction a fixed number of times, or until some condition is met.
Since it is an instruction that operates on other instructions like the execute instruction, it has been classified as a meta-instruction.{{cite journal|first=George E.|last=Rossman|title=A Course of Study in Computer Hardware Architecture|journal=IEEE Computer|volume=8|issue=12|pages=44–63|date=December 1975|doi=10.1109/C-M.1975.218835|s2cid=977792}}, p. 50
Computer models
The Univac 1103 (1953) includes a repeat instruction (op code mnemonic: {{mono|RPjnw}}) which executes the following instruction a fixed number of times, possibly incrementing one or both of the address fields of that instruction.{{cite manual|publisher=Remington Rand Univac|title=Reference Manual: Univac Scientific 1103A Computer|date=1956|page=30|url=http://www.bitsavers.org/pdf/univac/1103/Univac_Scientific_1103A_Reference_Manual_1956.pdf}} This compensates for the architecture's lack of index registers.Conrad Weisert, "Simulating an Obsolete Computer in 1960", Part 1: The main processor [https://www.idinews.com/history/Simulator.html]
The GE-600/Honeywell 6000 series (1964) supports a single-instruction repeat ({{mono|RPT}}), a double-instruction repeat ({{mono|RPTD}}), and a linked-list repeat ({{mono|RPL}}).{{cite manual|publisher=General Electric Computer Department|title=GE-635 System Manual|date=July 1964|page=A{{hyphen}}6|url=http://www.bitsavers.org/pdf/ge/GE-6xx/CPB-371A_GE-635_System_Man_Jul64.pdf}}{{cite manual|publisher=General Electric Information Systems|title=GE-625/635 Programming Reference Manual|date=July 1964|url=http://www.bitsavers.org/pdf/ge/GE-6xx/CPB1004F_GE635pgmRef_Jul69.pdf}}
The x86 ISA, starting with the 8086, includes a series of special-purpose repeat instructions ({{mono|REP(∅/E/Z/NE/NZ)}}) which are called "repeat string operation prefixes" and may only be applied to a small number of string instructions ({{mono|INS, OUTS, MOVS, LODS, STOS, CMPS, SCAS}}). These instructions repeat an operation and decrement a counter until it is zero, or may also stop when a certain condition is met.Intel Corporation, "Instruction Set Reference", Intel 64 and IA-32 Architectures Software Developer's Manual, Order Number 253667-060US, September 2016, 2B:4-550 [https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-2b-manual.pdf full text]
The Texas Instruments TMS320 digital signal processor (1983) includes an instruction for repeating a single-cycle instruction or two single-cycle instruction in parallel ({{mono|RPT}}) and an instruction for repeating a block of instructions ({{mono|RPTC}}). These use special block-repeat counter registers ({{mono|BRC0, BRC1}}).{{Cite book |last=Kuo |first=Sen-Maw |url=https://books.google.com/books?id=70scPIwK7cUC&q=block+repeat |title=Real-time Digital Signal Processing: Implementations, Applications, and Experiments with the TMS320C55X |date=2003 |publisher=清华大学出版社有限公司 |isbn=978-7-302-07700-8 |pages=67–68 |language=en}}