shallow trench isolation

{{Short description|Integrated circuit}}

Image:Isolation_pitch_vs_design_rule.PNG

File:Shallow trench isolation process.svg

Shallow trench isolation (STI), also known as box isolation technique, is an integrated circuit feature which prevents electric current leakage between adjacent semiconductor device components. STI is generally used on CMOS process technology nodes of 250 nanometers and smaller. Older CMOS technologies and non-MOS technologies commonly use isolation based on LOCOS.Quirk, Michael & Julian Serda (2001). [http://smtbook.com/instructor_guide.pdf Semiconductor Manufacturing Technology: Instructor's Manual] {{webarchive |url=https://web.archive.org/web/20070928192450/http://smtbook.com/instructor_guide.pdf |date=September 28, 2007 }}, p. 25.

STI is created early during the semiconductor device fabrication process, before transistors are formed. The key steps of the STI process involve etching a pattern of trenches in the silicon, depositing one or more dielectric materials (such as silicon dioxide) to fill the trenches, and removing the excess dielectric using a technique such as chemical-mechanical planarization.{{cite web | url=http://smtbook.com/features.htm | archive-url=https://web.archive.org/web/20070707023639/http://smtbook.com/features.htm | archive-date=7 July 2007 | title=The SMT Book Features }}

Certain semiconductor fabrication technologies also include deep trench isolation, a related feature often found in analog integrated circuits.

The effect of the trench edge has given rise to what has recently been termed the "reverse narrow channel effect"{{cite journal|last1=Jung|first1=Jong-Wan|last2=Kim|first2=Jong-Min|last3=Son|first3=Jeong-Hwan|last4=Lee|first4=Youngjong|title=Dependence of Subthreshold Hump and Reverse Narrow Channel Effect on the Gate Length by Suppression of Transient Enhanced Diffusion at Trench Isolation Edge|journal=Japanese Journal of Applied Physics|date=30 April 2000|volume=39|issue=Part 1, No. 4B|pages=2136–2140|doi=10.1143/JJAP.39.2136|bibcode=2000JaJAP..39.2136J}} or "inverse narrow width effect".A. Chatterjee et al., IEDM 1996.(conference announcement) {{citation|doi=10.1109/VLSIT.1996.507831|chapter=A shallow trench isolation study for 0.25/0.18 μm CMOS technologies and beyond|title=1996 Symposium on VLSI Technology. Digest of Technical Papers|pages=156–157|year=1996|last1=Chatterjee|first1=A.|last2=Esquivel|first2=J.|last3=Nag|first3=S.|last4=Ali|first4=I.|last5=Rogers|first5=D.|last6=Taylor|first6=K.|last7=Joyner|first7=K.|last8=Mason|first8=M.|last9=Mercer|first9=D.|last10=Amerasekera|first10=A.|last11=Houston|first11=T.|last12=Chen|first12=I.-C.|isbn=0-7803-3342-X|s2cid=27288482}} Basically, due to the electric field enhancement at the edge, it is easier to form a conducting channel (by inversion) at a lower voltage. The threshold voltage is effectively reduced for a narrower transistor width.{{cite journal|last1=Pretet|first1=J|last2=Ioannou|first2=D|last3=Subba|first3=N|last4=Cristoloveanu|first4=S|last5=Maszara|first5=W|last6=Raynaud|first6=C|title=Narrow-channel effects and their impact on the static and floating-body characteristics of STI- and LOCOS-isolated SOI MOSFETs|journal=Solid-State Electronics|date=November 2002|volume=46|issue=11|pages=1699–1707|doi=10.1016/S0038-1101(02)00147-8|bibcode=2002SSEle..46.1699P}}{{cite journal|last1=Lee|first1=Yung-Huei|last2=Linton|first2=Tom|last3=Wu|first3=Ken|last4=Mielke|first4=Neal|title=Effect of trench edge on pMOSFET reliability|journal=Microelectronics Reliability|date=May 2001|volume=41|issue=5|pages=689–696|doi=10.1016/S0026-2714(01)00002-6|bibcode=2001MiRe...41..689L }} The main concern for electronic devices is the resulting subthreshold leakage current, which is substantially larger after the threshold voltage reduction.