subthreshold slope

{{Short description|Feature of a MOSFET's current–voltage characteristic}}

The subthreshold slope is a feature of a MOSFET's current–voltage characteristic.

In the subthreshold region, the drain current behaviour—though being controlled by the gate terminal—is similar to the exponentially decreasing current of a forward biased diode. Therefore, a plot of drain current versus gate voltage with drain, source, and bulk voltages fixed will exhibit approximately log-linear behaviour in this MOSFET operating regime. Its slope is the subthreshold slope.

The subthreshold slope is also the reciprocal value of the subthreshold swing S_s-th which is usually given as:Physics of Semiconductor Devices, S. M. Sze. New York: Wiley, 3rd ed., with Kwok K. Ng, 2007, chapter 6.2.4, p. 315, {{ISBN|978-0-471-14323-9}}.

$S\_\{s-th\}\; =\; \backslash ln(10)\; \{kT\; \backslash over\; q\}\backslash left(1+\{C\_d\; \backslash over\; C\_\{ox\}\}\backslash right)$

$C\_d$ = depletion layer capacitance

$C\_\{ox\}$ = gate-oxide capacitance

$\{kT\; \backslash over\; q\}$ = thermal voltage

The minimum subthreshold swing of a conventional device can be found by letting $\backslash textstyle\; \{C\_\{d\}\}\; \backslash rightarrow\; 0$ and/or $\backslash textstyle\; \{C\_\{ox\}\}\; \backslash rightarrow\; \backslash infty$, which yield $S\_\{s-th,\; \backslash min\}\; =\; \backslash ln(10)\; \{kT\; \backslash over\; q\}$(known as thermionic limit) and 60 mV/dec at room temperature (300 K). A typical experimental subthreshold swing for a scaled MOSFET at room temperature is ~70 mV/dec, slightly degraded due to short-channel MOSFET parasitics.{{Cite book | last1 = Auth | first1 = C. | last2 = Allen | first2 = C. | last3 = Blattner | first3 = A. | last4 = Bergstrom | first4 = D. | last5 = Brazier | first5 = M. | last6 = Bost | first6 = M. | last7 = Buehler | first7 = M. | last8 = Chikarmane | first8 = V. | last9 = Ghani | first9 = T. | last10 = Glassman | first10 = T. | last11 = Grover | first11 = R. | last12 = Han | first12 = W. | last13 = Hanken | first13 = D. | last14 = Hattendorf | first14 = M. | last15 = Hentges | first15 = P. | last16 = Heussner | first16 = R. | last17 = Hicks | first17 = J. | last18 = Ingerly | first18 = D. | last19 = Jain | first19 = P. | last20 = Jaloviar | first20 = S. | last21 = James | first21 = R. | last22 = Jones | first22 = D. | last23 = Jopling | first23 = J. | last24 = Joshi | first24 = S. | last25 = Kenyon | first25 = C. | last26 = Liu | first26 = H. | last27 = McFadden | first28 = B. | last29 = Neirynck | first30 = C. | last30 = Parker | first29 = J. | last28 = McIntyre | first27 = R. | doi = 10.1109/VLSIT.2012.6242496 | chapter = A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors | title = 2012 Symposium on VLSI Technology (VLSIT) | pages = 131 | year = 2012 | isbn = 978-1-4673-0847-2

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A dec (decade) corresponds to a 10 times increase of the drain current I_D.

A device characterized by steep subthreshold slope exhibits a faster transition between off (low current) and on (high current) states.