14 nm process

The resolutions of a "14 nm" device are difficult to achieve in a polymeric resist, even with electron beam lithography. In addition, the chemical effects of ionizing radiation also limit reliable resolution to about 30 nm, which is also achievable using current state-of-the-art immersion lithography. Hardmask materials and multiple patterning are required.

A more significant limitation comes from plasma damage to low-k materials. The extent of damage is typically 20 nm thick,{{cite journal |first=O. |last=Richard |title=Sidewall damage in silica-based low-k material induced by different patterning plasma processes studied by energy filtered and analytical scanning TEM |journal=Microelectronic Engineering |volume=84 |issue=3 |pages=517–523 |year=2007 |doi=10.1016/j.mee.2006.10.058 |display-authors=etal}} but can also go up to about 100 nm.{{cite journal |first=T. |last=Gross |title=Detection of nanoscale etch and ash damage to nanoporous methyl silsesquioxane using electrostatic force microscopy |journal=Microelectronic Engineering |volume=85 |issue=2 |pages=401–407 |year=2008 |doi=10.1016/j.mee.2007.07.014 |display-authors=etal}} The damage sensitivity is expected to get worse as the low-k materials become more porous. For comparison, the atomic radius of an unconstrained silicon is 0.11 nm. Thus about 90 Si atoms would span the channel length, leading to substantial leakage.

Tela Innovations and Sequoia Design Systems developed a methodology allowing double exposure for the "16 nm"/"14 nm" node circa 2010.{{cite journal |first=V. |last=Axelrad |editor1-first=Michael L |editor1-last=Rieger |editor2-first=Joerg |editor2-last=Thiele |title=16nm with 193nm immersion lithography and double exposure |journal=Proc. SPIE |series=Design for Manufacturability through Design-Process Integration IV |volume=7641 |pages=764109 |year=2010 |doi=10.1117/12.846677 |bibcode=2010SPIE.7641E..09A |s2cid=56158128 |display-authors=etal}} Samsung and Synopsys had also, at that time, begun implementing double patterning in "22 nm" and "16 nm" design flows.{{cite journal |first=M-S. |last=Noh |editor1-first=Mircea V |editor1-last=Dusa |editor2-first=Will |editor2-last=Conley |title=Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows |journal=Proc. SPIE |series=Optical Microlithography XXIII |volume=7640 |pages=76400S |year=2010 |doi=10.1117/12.848194 |bibcode=2010SPIE.7640E..0SN |s2cid=120545900 |display-authors=etal}} Mentor Graphics reported taping out "16 nm" test chips in 2010.{{cite web|url=http://www.eetimes.com/electronics-news/4206398/Mentor-moves-tools-toward-16-nanometer|date= August 23, 2010 |title=Mentor moves tools toward 16-nanometer|publisher=EETimes}}{{and then what|date=February 2024}} On January 17, 2011, IBM announced that they were teaming up with ARM to develop "14 nm" chip processing technology.{{cite web |url=http://www-03.ibm.com/press/us/en/pressrelease/33405.wss |archive-url=https://web.archive.org/web/20110121214100/http://www-03.ibm.com/press/us/en/pressrelease/33405.wss |url-status=dead |archive-date=January 21, 2011 |work=IBM Press release |date=January 17, 2011 |title=IBM and ARM to Collaborate on Advanced Semiconductor Technology for Mobile Electronics }}{{and then what|date=February 2024}}

On February 18, 2011, Intel announced that it would construct a new $5 billion semiconductor fabrication plant in Arizona, designed to manufacture chips using the "14 nm" manufacturing processes and leading-edge 300 mm wafers.{{cite web|url=http://www.eetimes.com/electronics-news/4213295/Intel-to-build-new-Arizona-fab-|title=Intel to build fab for 14-nm chips|publisher=EE Times|access-date=February 22, 2011|archive-date=February 2, 2013|archive-url=https://web.archive.org/web/20130202082819/http://www.eetimes.com/electronics-news/4213295/Intel-to-build-new-Arizona-fab-|url-status=dead}}[https://www.eetimes.com/document.asp?doc_id=1258701 Update: Intel to build fab for 14-nm chips] The new fabrication plant was to be named Fab 42, and construction was meant to start in the middle of 2011. Intel billed the new facility as "the most advanced, high-volume manufacturing facility in the world," and said it would come on line in 2013. Intel since decided to postpone opening this facility and instead upgrade its existing facilities to support 14-nm chips.{{cite web |url=https://www.reuters.com/article/us-intel-arizona-idUSBREA0D1F920140114 |title=Intel shelves cutting-edge Arizona chip factory |work=Reuters |date=January 14, 2014 }}{{and then what|date=February 2024}} On May 17, 2011, Intel announced a roadmap for 2014 that included "14 nm" transistors for their Xeon, Core, and Atom product lines.{{cite web |url=http://www.anandtech.com/show/4345/intels-2011-investor-meeting-intels-architecture-group-14nm-airmont-atom-in-2014 |title=Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows |work=AnandTech |date=May 17, 2011 }}{{and then what|date=February 2024}}

In the late 1990s, Hisamoto's Japanese team from Hitachi Central Research Laboratory began collaborating with an international team of researchers on further developing FinFET technology, including TSMC's Chenming Hu and various UC Berkeley researchers. In 1998, the team successfully fabricated devices down to a 17{{nbsp}}nm process. They later developed a 15{{nbsp}}nm FinFET process in 2001.{{cite web |last1=Tsu-Jae King |first1=Liu |author-link1=Tsu-Jae King Liu |title=FinFET: History, Fundamentals and Future |url=https://people.eecs.berkeley.edu/~tking/presentations/KingLiu_2012VLSI-Tshortcourse |website=University of California, Berkeley |publisher=Symposium on VLSI Technology Short Course |date=June 11, 2012 |access-date=9 July 2019}} In 2002, an international team of researchers at UC Berkeley, including Shibly Ahmed (Bangladeshi), Scott Bell, Cyrus Tabery (Iranian), Jeffrey Bokor, David Kyser, Chenming Hu (Taiwan Semiconductor Manufacturing Company), and Tsu-Jae King Liu, demonstrated FinFET devices down to 10 nm gate length.{{cite book |last1=Ahmed |first1=Shibly |last2=Bell |first2=Scott |last3=Tabery |first3=Cyrus |last4=Bokor |first4=Jeffrey |last5=Kyser |first5=David |last6=Hu |first6=Chenming |last7=Liu |first7=Tsu-Jae King |last8=Yu |first8=Bin |last9=Chang |first9=Leland |title=Digest. International Electron Devices Meeting |chapter=FinFET scaling to 10 nm gate length |date=December 2002 |pages=251–254 |doi=10.1109/IEDM.2002.1175825 |chapter-url=https://www.eecs.wsu.edu/~osman/EE597/FINFET/finfet4.pdf |isbn=0-7803-7462-2 |s2cid=7106946 |access-date=December 10, 2019 |archive-date=May 27, 2020 |archive-url=https://web.archive.org/web/20200527205136/https://www.eecs.wsu.edu/~osman/EE597/FINFET/finfet4.pdf |url-status=dead }}

In 2005, Toshiba demonstrated a 15 nm FinFET process, with a 15 nm gate length and 10 nm fin width, using a sidewall spacer process.{{cite conference | first1=A | last1=Kaneko |first2 = A | last2= Yagashita | first3 = K| last3 = Yahashi| first4 =T |last4= Kubota |display-authors=etal| title=Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm FinFET with elevated source/drain extension | book-title=IEEE International Electron Devices Meeting (IEDM 2005) | pages=844–847 | year=2005 | doi=10.1109/IEDM.2005.1609488}} It had erstwhile been suggested in 2003 that for the 16 nm node, a logic transistor would have a gate length of about 5 nm.{{cite news |url=https://www.zdnet.com/article/intel-scientists-find-wall-for-moores-law/ |title=Intel scientists find wall for Moore's Law |publisher=ZDNet |date=December 1, 2003}}{{and then what|date=February 2024}} In December 2007, Toshiba demonstrated a prototype memory unit that used 15-nanometre thin lines.{{cite web|url=http://www.theinquirer.net/gb/inquirer/news/2007/12/13/nanometre-memory-tested|archive-url=https://web.archive.org/web/20071213194617/http://www.theinquirer.net/gb/inquirer/news/2007/12/13/nanometre-memory-tested|url-status=unfit|archive-date=December 13, 2007|title=15 Nanometre Memory Tested|website=The Inquirer}}

In December 2009, National Nano Device Laboratories, owned by the Taiwanese government, produced a "16 nm" SRAM chip.{{cite web|url=http://www.taiwantoday.tw/ct.asp?xitem=87144&CtNode=416|title=16nm SRAM produced – Taiwan Today|publisher=taiwantoday.tw|access-date=December 16, 2009|archive-url=https://web.archive.org/web/20160320040841/http://www.taiwantoday.tw/ct.asp?xitem=87144&CtNode=416|archive-date=March 20, 2016|url-status=dead|df=mdy-all}}{{and then what|date=February 2024}}

In September 2011, Hynix announced the development of "15 nm" NAND cells.{{cite journal |last=Hübler |first=Arved |year=2011 |title=Printed Paper Photovoltaic Cells |journal=Advanced Energy Materials |volume=1 |issue=6 |pages=1018–1022 |doi=10.1002/aenm.201100394 |bibcode=2011AdEnM...1.1018H |s2cid=98247321 |display-authors=etal}}{{and then what|date=February 2024}}

In December 2012, Samsung Electronics taped out a "14 nm" chip.{{cite news |url=https://www.engadget.com/2012/12/21/samsung-first-14nm-finfet-test-chip-/ |title=Samsung reveals its first 14nm FinFET test chip |publisher=Engadget |date=December 21, 2012}}{{and then what|date=February 2024}}

In September 2013, Intel demonstrated an Ultrabook laptop that used a "14 nm" Broadwell CPU, and Intel CEO Brian Krzanich said, "[CPU] will be shipping by the end of this year."{{cite news |url=https://www.theregister.co.uk/2013/09/10/intel_reveals_14nm_pc_declares_moores_law_alive_and_well/ |title=Intel reveals 14nm PC, declares Moore's Law 'alive and well' |publisher=The Register |date=September 10, 2013}} However, as of February 2014, shipment had at time erstwhile been delayed further until Q4 2014.{{cite web| url= http://www.digitimes.com/news/a20140212PD209.html?mod=2 |title=Intel postpones Broadwell availability to 4Q14 |date=February 12, 2014 |publisher=Digitimes.com |access-date=2014-02-13}}{{and then what|date=February 2024}}

In August 2014, Intel announced details of the "14 nm" microarchitecture for its upcoming Core M processors, the first product to be manufactured on Intel's "14 nm" manufacturing process. The first systems based on the Core M processor were to become available in Q4 2014 — according to the press release. "Intel's 14 nanometer technology uses second-generation tri-gate transistors to deliver industry-leading performance, power, density and cost per transistor," said Mark Bohr, Intel senior fellow, Technology and Manufacturing Group, and director, Process Architecture and Integration.{{cite news |url=http://newsroom.intel.com/community/intel_newsroom/blog/2014/08/11/intel-discloses-newest-microarchitecture-and-14-nanometer-manufacturing-process-technical-details |title=Intel Discloses Newest Microarchitecture and 14 Nanometer Manufacturing Process Technical Details |publisher=Intel |date=August 11, 2014}}{{and then what|date=February 2024}}

In 2018 a shortage of "14 nm" fab capacity was announced by Intel.{{Cite web|url=https://www.extremetech.com/computing/276481-intel-faces-14nm-shortage-as-cpu-prices-rise|title=Intel Faces 14nm Shortage As CPU Prices Rise - ExtremeTech|website=www.extremetech.com}}{{and then what|date=February 2024}}

In 2013, SK Hynix began mass-production of "16{{nbsp}}nm" NAND flash,{{cite web |title=History: 2010s |url=https://www.skhynix.com/eng/about/history2010.jsp |website=SK Hynix |access-date=8 July 2019 |archive-date=May 17, 2021 |archive-url=https://web.archive.org/web/20210517040328/https://www.skhynix.com/eng/about/history2010.jsp |url-status=dead }} TSMC began "16{{nbsp}}nm" FinFET production,{{cite web |title=16/12nm Technology |url=https://www.tsmc.com/english/dedicatedFoundry/technology/16nm.htm |publisher=TSMC |access-date=30 June 2019}} and Samsung began "10{{nbsp}}nm class" NAND flash production.{{cite news |title=Samsung Mass Producing 128Gb 3-bit MLC NAND Flash |url=https://www.tomshardware.co.uk/NAND-128Gb-Mass-Production-3-bit-MLC,news-43458.html |access-date=21 June 2019 |work=Tom's Hardware |date=11 April 2013 |archive-date=June 21, 2019 |archive-url=https://web.archive.org/web/20190621175628/https://www.tomshardware.co.uk/NAND-128Gb-Mass-Production-3-bit-MLC,news-43458.html |url-status=dead }}

On September 5, 2014, Intel launched the first three Broadwell-based processors that belonged to the low-TDP Core M family: Core M-5Y10, Core M-5Y10a, and Core M-5Y70.{{cite web |url= http://www.cpu-world.com/news_2014/2014090701_Intel_launches_first_Broadwell_processors.html |title=Intel launches first Broadwell processors |first=Anthony |last=Shvets |work=CPU World |date=7 September 2014 |access-date=18 March 2015}}{{and then what|date=February 2024}}

In February 2015, Samsung announced that their flagship smartphones, the Galaxy S6 and S6 Edge, would feature "14 nm" Exynos systems on chip (SoCs).{{Cite web|url=https://news.samsung.com/global/samsung-announces-mass-production-of-industrys-first-14nm-finfet-mobile-application-processor|title=Samsung Announces Mass Production of Industry's First 14nm FinFET Mobile Application Processor|website=news.samsung.com}}{{and then what|date=February 2024}}

On March 9, 2015, Apple Inc. released the "Early 2015" MacBook and MacBook Pro, which utilized "14 nm" Intel processors. Of note is the i7-5557U, which has Intel Iris Graphics 6100 and two cores running at 3.1 GHz, using only 28 watts.{{cite web |url= http://www.everymac.com/systems/apple/macbook_pro/specs/macbook-pro-core-i7-3.1-13-early-2015-retina-display-specs.html |title=Apple MacBook Pro "Core i7" 3.1 13" Early 2015 Specs |work=EveryMac.com |year=2015 |access-date=18 March 2015}}{{cite web |url= http://www.cpu-world.com/CPUs/Core_i7/Intel-Core%20i7-5557U%20Mobile%20processor.html |title=Intel Core i7-5557U specifications |work=CPU World |year=2015 |access-date=18 March 2015}}{{and then what|date=February 2024}}

On September 25, 2015, Apple Inc. released the iPhone 6S & 6S Plus, which were erstwhile equipped with "desktop-class" A9 chips{{cite web |url= https://www.theverge.com/2015/9/9/9295923/apple-a9x-ipad-pro-chip |title=Apple's new A9 and A9X processors promise 'desktop-class performance' |last=Vincent |first=James |work=The Verge |date= 9 September 2015|access-date=27 August 2017}} that are fabricated in both "14 nm" by Samsung and "16 nm" by TSMC (Taiwan Semiconductor Manufacturing Company).{{and then what|date=February 2024}}

In May 2016, Nvidia released its GeForce 10 series GPUs based on the Pascal architecture, which incorporates TSMC's "16 nm" FinFET technology and Samsung's "14 nm" FinFET technology.{{cite web|title = Talks of foundry partnership between NVIDIA and Samsung (14nm) didn't succeed, and the GPU maker decided to revert to TSMC's 16nm process.|url = http://www.techpowerup.com/216080/nvidia-pascal-gpus-to-be-built-on-16-nm-tsmc-finfet-node.html|access-date = August 25, 2015}}{{cite web|title = Samsung to Optical-Shrink NVIDIA "Pascal" to 14 nm|url = https://www.techpowerup.com/224976/samsung-to-optical-shrink-nvidia-pascal-to-14-nm.html|access-date = August 13, 2016}}{{and then what|date=February 2024}}

In June 2016, AMD released its Radeon RX 400 GPUs based on the Polaris architecture, which incorporated "14 nm" FinFET technology from Samsung. The technology had at that time been licensed to GlobalFoundries for dual sourcing.{{cite news|last1=Smith|first1=Ryan|title=AMD Announces RX 470 & RX 460 Specifications; Shipping in Early August|url=http://www.anandtech.com/show/10530/amd-announces-radeon-rx-470-rx-460-specifications-shipping-in-early-august|access-date=29 July 2016|publisher=Anandtech|date=28 July 2016}}{{and then what|date=February 2024}}

On August 2, 2016, Microsoft released the Xbox One S, which utilized "16 nm" by TSMC. {{and then what|date=February 2024}}

On March 2, 2017, AMD released its Ryzen CPUs based on the Zen architecture, incorporating "14 nm" FinFET technology from Samsung which had erstwhile been licensed to GlobalFoundries for GlobalFoundries to build.{{cite web|url=http://www.extremetech.com/computing/217664-globalfoundries-announces-14nm-validation-with-amd-silicon|title=GlobalFoundries announces 14nm validation with AMD Zen silicon|work=ExtremeTech}}{{and then what|date=February 2024}}

The NEC SX-Aurora TSUBASA processor, introduced in October 2017,{{Cite news|url=https://www.nec.com/en/press/201710/global_20171025_01.html|title=NEC releases new high-end HPC product line, SX-Aurora TSUBASA|work=NEC|access-date=2018-03-21|language=en-US}} used a "16{{nbsp}}nm" FinFET process from TSMC and was designed for use with NEC SX supercomputers.{{cite news |last1=Cutress |first1=Ian |title=Hot Chips 2018: NEC Vector Processor Live Blog |url=https://www.anandtech.com/show/13259/hot-chips-2018-nec-vector-processor-live-blog |access-date=15 July 2019 |work=AnandTech |date=August 21, 2018}}{{and then what|date=February 2024}}

On July 22, 2018, GlobalFoundries announced their "12 nm" Leading-Performance (12LP) process, based on a licensed 14LP process from Samsung.{{Cite web|url=https://fuse.wikichip.org/news/1497/vlsi-2018-globalfoundries-12nm-leading-performance-12lp/|title=VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP|last=Schor|first=David|date=2018-07-22|website=WikiChip Fuse|language=en-US|access-date=2019-05-31}}{{and then what|date=February 2024}}

In September 2018, Nvidia released GPUs based on their Turing (microarchitecture), which were made on TSMC's "12 nm" process and had a transistor density of 24.67 million transistors per square millimeter.{{Cite web|url=https://wccftech.com/nvidia-geforce-rtx-30-series-ampere-graphics-cards-deep-dive/|title = NVIDIA GeForce RTX 30 Series & Ampere GPUs Further Detailed - GA102/GA104 GPU Specs & RTX 3090, RTX 3080, RTX 3070 Performance & Features Revealed|date = September 4, 2020}}{{and then what|date=February 2024}}

class="wikitable" style="text-align:center;" ! ! ITRS Logic Device Ground Rules (2015) ! colspan="3" | Samsung{{efn|Second-sourced to GlobalFoundries.}} ! colspan="4" | TSMC{{cite web|url=https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_16_12nm|title=16/12nm Technology|website=TSMC|access-date=November 12, 2022}} ! colspan="3" | Intel ! colspan="3" | GlobalFoundries{{efn|Based on Samsung's 14{{nbsp}}nm process.}} ! colspan="2" | SMIC
style="text-align:left;" | Process name | 16/14 nm | 14LPE || 14LPP || 11LPP | 16{{abbr|FF|FinFET}} (16 nm) || 16{{abbr|FF+|FinFET Plus}} (16 nm) || 16{{abbr|FFC|FinFET Compact}} (16 nm) || 12{{abbr|FFC|FinFET Compact}} (12 nm) | 14 nm || 14 nm + || 14 nm ++ | 14{{abbr|LPP|Low Power Plus}}{{Cite web|url=https://www.globalfoundries.com/sites/default/files/product-briefs/product-brief-14lpp.pdf|title=PB14LPP-1.0|url-status=dead|archive-url=https://web.archive.org/web/20170905171527/https://www.globalfoundries.com/sites/default/files/product-briefs/product-brief-14lpp.pdf|archive-date=September 5, 2017|website=GlobalFoundries|access-date=November 28, 2022}} (14 nm) || 12{{abbr|LP|Leading-Performance}}{{Cite web|url=https://www.globalfoundries.com/sites/default/files/product-briefs/pb-12lp-11-web.pdf|title=PB12LP-1.1|url-status=dead|archive-url=https://web.archive.org/web/20181227045657/https://www.globalfoundries.com/sites/default/files/product-briefs/pb-12lp-11-web.pdf|archive-date=December 27, 2018|website=GlobalFoundries|access-date=November 28, 2022}}{{Cite web|url=https://fuse.wikichip.org/news/1497/vlsi-2018-globalfoundries-12nm-leading-performance-12lp/|title=VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP|first=David|last=Schor|date=July 22, 2018|website=WikiChip Fuse}} (12 nm)|| 12{{abbr|LP+|Leading-Performance-plus}} |14 nm || 12 nm
style="text-align:left;" | Transistor density (MTr/mm2) | {{unknown}} | colspan="2" | 32.94 ||54.38 | colspan="3" | 28.88{{Cite web|url=https://fuse.wikichip.org/news/2261/tsmc-announces-6-nanometer-process/|title=TSMC Announces 6-Nanometer Process|last=Schor|first=David|date=April 16, 2019|website=WikiChip Fuse|language=en-US|access-date=May 31, 2019}} | 33.8{{cite web | url=https://www.techcenturion.com/7nm-10nm-14nm-fabrication | title=7nm vs 10nm vs 14nm: Fabrication Process - Tech Centurion | date=November 26, 2019}} | colspan="3" | 37.5{{Cite web|url=https://spectrum.ieee.org/intel-now-packs-100-million-transistors-in-each-square-millimeter|title=Intel Now Packs 100 Million Transistors in Each Square Millimeter|website=IEEE Spectrum: Technology, Engineering, and Science News|date=March 30, 2017|language=en|access-date=2018-11-14}}{{efn|Intel uses this formula:{{Cite web|url=https://newsroom.intel.com/editorials/lets-clear-up-node-naming-mess/|title=Let's Clear Up the Node Naming Mess|last=Bohr|first=Mark|date=March 28, 2017|website=Intel Newsroom|access-date=December 6, 2018}} $\backslash rm\; 0.6\; \backslash times\; \backslash frac\{NAND2\backslash \; Tr\backslash \; Count\}\{NAND2\backslash \; Cell\backslash \; Area\}\; +\; 0.4\; \backslash times\; \backslash frac\{Scan\backslash \; Flip\backslash \; Flop\backslash \; Tr\backslash \; Count\}\{Scan\backslash \; Flip\backslash \; Flop\backslash \; Cell\backslash \; Area\}\; =$ # $\backslash rm\; Transistors\; /\; mm^2$}} 44.67{{cite web | url=https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-and-core-i3-8121u-deep-dive-review/3 | title=Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review }} | 30.59 || 36.71 || {{unknown}} | 30{{Cite web|title=SMIC-14nm|url=https://www.smics.com/en/site/technology_advanced_14|website=SIMC}} ||{{unknown}}
style="text-align:left;" | Transistor gate pitch (nm) | 70 | colspan="3" | 78 | colspan="4" | 88 | colspan="2" | 70 || 84 | colspan="2" |84 ||{{unknown}} | 90 || {{unknown}}
style="text-align:left;" | Interconnect pitch (nm) | 56 | colspan="3" | 67 | colspan="4" | 70 | colspan="3" | 52 | colspan="2" {{unknown}} ||{{unknown}} | {{unknown}} || {{unknown}}
style="text-align:left;" | Transistor fin pitch (nm) | 42 | colspan="3" | 49 | colspan="4" | 45 | colspan="3" | 42 | colspan="2" | 48 ||{{unknown}} | 51 || {{unknown}}
style="text-align:left;" | Transistor fin width (nm) | 8 | colspan="3" | 8 | colspan="4" {{unknown}} | colspan="3" | 8 | colspan="2" {{unknown}} ||{{unknown}} | {{unknown}} || {{unknown}}
style="text-align:left;" | Transistor fin height (nm) | 42 | colspan="3" | ~38 | colspan="4" | 37 | colspan="3" | 42 | colspan="2" {{unknown}} ||{{unknown}} | {{unknown}} || {{unknown}}
style="text-align:left;" | Production year | 2015 | 2014 Q4{{Cite web |last=Frumusanu |first=Andrei |title=The Samsung Exynos 7420 Deep Dive - Inside A Modern 14nm SoC |url=https://www.anandtech.com/show/9330/exynos-7420-deep-dive |access-date=2024-08-01 |website=www.anandtech.com}}|| 2016 Q1{{Cite web |last=Frumusanu |first=Andrei |title=Samsung Announces Second-Gen 14nm Low Power Plus (14LPP) Process Now In Mass Production |url=https://www.anandtech.com/show/9959/samsung-announces-14lpp-mass-production |access-date=2024-08-01 |website=www.anandtech.com}}||2018 H2{{Cite web |last=Shilov |first=Anton |title=Samsung Details 11LPP Process Technology: 10 nm BEOL Meets 14 nm Elements |url=https://www.anandtech.com/show/11877/samsung-details-11lpp-process-technology-10-nm-beol-meets-14-nm-elements |access-date=2024-08-01 |website=www.anandtech.com}} | 2013 Q4 risk production 2014 production || 2015 Q3 || 2016 Q2 || 2017 | 2014 Q3{{Cite web |last=Smith |first=Ryan |title=Intel’s 14nm Technology in Detail |url=https://www.anandtech.com/show/8367/intels-14nm-technology-in-detail |access-date=2024-08-01 |website=www.anandtech.com}}|| 2016 H2{{Cite web |last=Cutress |first=Ian |title=Intel Announces 7th Gen Kaby Lake: 14nm PLUS, Six Notebook SKUs, Desktop coming in January |url=https://www.anandtech.com/show/10610/intel-announces-7th-gen-kaby-lake-14nm-plus-six-notebook-skus-desktop-coming-in-january |access-date=2024-08-01 |website=www.anandtech.com}}|| 2017{{Cite web |last=Howse |first=Brett |title=Intel Announces 8th Generation Core "Coffee Lake" Desktop Processors: Six-core i7, Four-core i3, and Z370 Motherboards |url=https://www.anandtech.com/show/11869/intel-announces-8th-generation-coffee-lake-hex-core-desktop-processors |access-date=2024-08-01 |website=www.anandtech.com}} | 2016 || 2018 ||2020 Q3{{Cite web |title=GLOBALFOUNDRIES 12LP+ FinFET Solution Ready for Production |url=https://www.hpcwire.com/off-the-wire/globalfoundries-12lp-finfet-solution-ready-for-production/ |access-date=2024-08-01 |website=HPCwire |language=en-US}} | 2019 Q3 risk productionhttps://www.anandtech.com/show/14744/smic-14nm-finfet-in-risk-production-to-contribute-revenue-by-late-2019 2019 Q4 productionhttps://www.anandtech.com/show/15105/smic-begins-volume-production-of-14-nm-finfet-chips-chinas-first-finfet-line || 2019 Q4 risk productionhttps://medium.com/digitimes/smic-to-move-12nm-finfet-process-to-risk-production-by-year-end-2019-ed33cefe7ff8 2020 Q4 productionhttps://news.futunn.com/en/post/8135966/smic-starts-small-scale-mass-production-of-the-12nm-process?level=1&data_ticket=1747429279591661

{{notelist}}

Lower numbers are better, except for transistor density, in which case the opposite is true.{{Cite web|url=https://www.britannica.com/technology/computer-chip#ref1036975|title=Nanotechnology is expected to make transistors even smaller and chips correspondingly more powerful|date=December 22, 2017|website=Encyclopædia Britannica|access-date=March 7, 2018}} Transistor gate pitch is also referred to as CPP (contacted poly pitch), and interconnect pitch is also referred to as MMP (minimum metal pitch).{{Cite web|url=http://www.intel.com/content/dam/www/public/us/en/documents/technology-briefs/bohr-14nm-idf-2014-brief.pdf|title=Intel 14nm Process Technology}}{{Cite news|url=http://www.electronics-eetimes.com/news/samsung%E2%80%99s-14-nm-lpe-finfet-transistors/page/0/3|title=Samsung's 14 nm LPE FinFET transistors|date=January 20, 2016|newspaper=Electronics EETimes|access-date=February 17, 2017|language=en}}{{Cite web|url=https://en.wikichip.org/wiki/14_nm_lithography_process|title=14 nm lithography process - WikiChip|website=en.wikichip.org|language=en|access-date=February 17, 2017}}{{Cite web|url=https://en.wikichip.org/wiki/16_nm_lithography_process|title=16 nm lithography process - WikiChip|website=en.wikichip.org|language=en|access-date=February 17, 2017}}{{Cite web|url=https://www.semiconductors.org/clientuploads/Research_Technology/ITRS/2015/0_2015%20ITRS%202.0%20Executive%20Report%20(1).pdf|title=International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report|access-date=April 6, 2017|archive-url=https://web.archive.org/web/20161002215308/http://www.semiconductors.org/clientuploads/Research_Technology/ITRS/2015/0_2015%20ITRS%202.0%20Executive%20Report%20%281%29.pdf|archive-date=October 2, 2016|url-status=dead|df=mdy-all}}

{{Cite web|url=https://www.anandtech.com/show/15105/smic-begins-volume-production-of-14-nm-finfet-chips-chinas-first-finfet-line|title=SMIC Begins Volume Production of 14 nm FinFET Chips: China's First FinFET Line|last=Shilov|first=Anton|website=AnandTech|access-date=November 16, 2019|archive-date=November 15, 2019|archive-url=https://web.archive.org/web/20191115160920/https://www.anandtech.com/show/15105/smic-begins-volume-production-of-14-nm-finfet-chips-chinas-first-finfet-line|url-status=live}}

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{{sequence

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{{DEFAULTSORT:14 nanometre}}

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