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2 nm process

{{Short description|Semiconductor manufacturing process}}

{{Semiconductor manufacturing processes}}

{{Use dmy dates|date=March 2025}}

In semiconductor manufacturing, the 2 nm process is the next MOSFET (metal–oxide–semiconductor field-effect transistor) die shrink after the 3 nm process node.

The term "2 nanometer", or alternatively "20 angstrom" (a term used by Intel), has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by the Institute of Electrical and Electronics Engineers (IEEE), a "2.1 nm node range label" is expected to have a contacted gate pitch of 45 nanometers and a tightest metal pitch of 20 nanometers.{{Citation |url=https://irds.ieee.org/editions/2021/more-moore |title=INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS: More Moore |year=2021 |publisher=IEEE |page=7 |access-date=7 August 2022 |archive-date=7 August 2022 |archive-url=https://web.archive.org/web/20220807181530/https://irds.ieee.org/editions/2021/more-moore |url-status=live}}

class="wikitable"
ProcessGate pitchMetal pitchYear
7 nm60 nm40 nm2018
5 nm51 nm30 nm2020
3 nm48 nm24 nm2022
2 nm45 nm20 nm2025
1 nm42 nm16 nm2027

As such, 2 nm is used primarily as a marketing term by the semiconductor industry to refer to a new, improved generation of chips in terms of increased transistor density (a higher degree of miniaturization), increased speed, and reduced power consumption compared to the previous 3 nm node generation.{{Cite web |url=https://www.pcgamesn.com/amd/tsmc-7nm-5nm-and-3nm-are-just-numbers |title=TSMC's 7nm, 5nm, and 3nm "are just numbers… it doesn't matter what the number is" |date=10 September 2019 |access-date=20 April 2020 |archive-date=17 June 2020 |archive-url=https://web.archive.org/web/20200617230408/https://www.pcgamesn.com/amd/tsmc-7nm-5nm-and-3nm-are-just-numbers |url-status=live }}{{Cite journal |url=https://spectrum.ieee.org/a-better-way-to-measure-progress-in-semiconductors |author=Samuel K. Moore |title=A Better Way to Measure Progress in Semiconductors: It's time to throw out the old Moore's Law metric |publisher=IEEE |journal=IEEE Spectrum |date=21 July 2020 |access-date=20 April 2021 |archive-date=2 December 2020 |archive-url=https://web.archive.org/web/20201202002819/https://spectrum.ieee.org/semiconductors/devices/a-better-way-to-measure-progress-in-semiconductors |url-status=live }}

TSMC began risk production of its 2 nm process in July 2024, with mass production planned for the second half of 2025,{{Cite web |last=Salman |first=Ali |date=9 July 2024 |title=Apple Supplier TSMC Will Begin Trial Production Of 2nm Chips Next Week, Aiming To Secure A Stable Yield Before Mass Production |url=https://wccftech.com/tsmc-to-begin-trial-production-of-2nm-chips-next-week/ |access-date=10 September 2024 |website=Wccftech |language=en-US}} and Samsung plans to start production in 2025.{{Cite web |last=Shilov |first=Anton |title=Samsung Foundry Unveils Updated Roadmap: BSPDN and 2nm Evolution Through 2027 |url=https://www.anandtech.com/show/21444/samsung-foundry-unveils-updated-roadmap-2nm-evolution-through-2027 |access-date=10 September 2024 |website=www.anandtech.com}} Intel initially forecasted production in 2024 but scrapped its 2 nm node in favor of the smaller 18 angstrom (18A) node.{{Cite web |last=Alcorn |first=Paul |date=4 September 2024 |title=Intel announces cancellation of 20A process node for Arrow Lake, goes with external nodes instead, likely TSMC [Updated] |url=https://www.tomshardware.com/pc-components/cpus/intel-announces-cancellation-of-20a-process-node-for-arrow-lake-goes-with-external-nodes-instead-likely-tsmc |access-date=10 September 2024 |website=Tom's Hardware |language=en}}

Background

By 2018, a number of transistor architectures had been proposed for the eventual replacement of FinFET, most of which were based on the concept of GAAFET:{{cite web | url=https://semiengineering.com/the-increasingly-uneven-race-to-3nm-2nm/ | title=The Increasingly Uneven Race to 3nm/2nm | date=24 May 2021 }} horizontal and vertical nanowires, horizontal nanosheet transistors{{cite web | url=https://semiengineering.com/whats-different-about-next-gen-transistors/ | title=What's Different About Next-Gen Transistors | date=20 October 2022 }}{{cite web | url=https://spectrum.ieee.org/amp/intels-stacked-nanosheet-transistors-could-be-the-next-step-in-moores-law-2652903505 | title=Intel's Stacked Nanosheet Transistors Could be the Next Step in Moore's Law }} (Samsung MBCFET, Intel Nanoribbon), vertical FET (VFET) and other vertical transistors,{{cite web | url=https://spectrum.ieee.org/amp/nanowire-transistors-could-keep-moores-law-alive-2650269271 | title=Nanowire Transistors Could Keep Moore's Law Alive }}{{cite web | url=https://physicsworld.com/a/nanowires-give-vertical-transistors-a-boost/ | title=Nanowires give vertical transistors a boost | date=2 August 2012 }} complementary FET (CFET), stacked FET, several kinds of horizontal gate-all-around transistors such as nano-ring, hexagonal wire, square wire, and round wire gate-all-around transistors{{cite web | url=https://semiengineering.com/whats-after-finfets/ | title=What's After FinFETs? | date=24 July 2017 }} and negative-capacitance FET (NC-FET) which uses drastically different materials.{{cite web | url=https://semiengineering.com/transistor-options-beyond-3nm/ | title=Transistor Options Beyond 3nm | date=15 February 2018 }}

In late 2018, TSMC chairman Mark Liu predicted chip scaling would continue to 3 nm and 2 nm nodes; however, as of 2019, other semiconductor specialists were undecided as to whether nodes beyond 3 nm could become viable.{{and then what|date=February 2024}} TSMC began research on 2 nm in 2019{{Citation|url=https://wccftech.com/tsmc-2nm-research-taiwan/|title=TSMC To Commence 2nm Research In Hsinchu, Taiwan Claims Report|first=Ramish|last=Zafar|date=12 June 2019|access-date=23 September 2020|archive-date=7 November 2020|archive-url=https://web.archive.org/web/20201107234628/https://wccftech.com/tsmc-2nm-research-taiwan/|url-status=live}}—expecting to transition from FinFET to GAAFET.{{citation | url = https://www.digitimes.com/news/a20200921VL201.html | title = Highlights of the day: TSMC reportedly adopts GAA transistors for 2nm chips | date = 21 September 2020 | work = www.digitimes.com | access-date = 23 September 2020 | archive-date = 23 October 2020 | archive-url = https://web.archive.org/web/20201023051432/https://www.digitimes.com/news/a20200921VL201.html | url-status = live }}{{and then what|date=February 2024}} In July 2021, TSMC received governmental approval to build its 2 nm plant. In August 2020, it began building a research and development lab for 2 nm technology in Hsinchu, expected to become partially operational by 2021.{{citation | url = https://taipeitimes.com/News/front/archives/2020/08/26/2003742295 | title = TSMC developing 2nm tech at new R&D center | first = Lisa | last = Wang | date = 26 August 2020 | work = taipeitimes.com | access-date = 23 September 2020 | archive-date = 24 January 2021 | archive-url = https://web.archive.org/web/20210124141651/https://www.taipeitimes.com/News/front/archives/2020/08/26/2003742295 | url-status = live }}{{and then what|date=February 2024}} In September 2020, TSMC confirmed this and stated that it could also install production at Taichung depending on demand.{{citation | url = https://focustaiwan.tw/sci-tech/202009230017 | title = TSMC to build 2nm wafer plant in Hsinchu | first1 = Chang | last1 = Chien-Chung | first2 = Frances | last2 = Huang | date = 23 September 2020 | work = focustaiwan.tw | access-date = 23 September 2020 | archive-date = 25 October 2020 | archive-url = https://web.archive.org/web/20201025160716/https://focustaiwan.tw/sci-tech/202009230017 | url-status = live }}{{and then what|date=February 2024}} According to the Taiwan Economic Daily (2020), expectations were for high yield risk production in late 2023.{{citation | url = https://www.gizchina.com/2020/09/23/tsmc-2nm-process-makes-a-significant-breakthrough/ | title = TSMC 2NM PROCESS MAKES A SIGNIFICANT BREAKTHROUGH | first = Efe | last = Udin | date = 23 September 2020 | work = www.gizchina.com | access-date = 24 September 2021 | archive-date = 19 October 2021 | archive-url = https://web.archive.org/web/20211019171632/https://www.gizchina.com/2020/09/23/tsmc-2nm-process-makes-a-significant-breakthrough/ }}{{citation | url = https://news.mydrivers.com/1/714/714927.htm | language = Chinese | title = 台积电2nm工艺重大突破！2023年风险试产良率或达90% | date = 22 September 2020 | access-date = 24 September 2021 | archive-date = 24 September 2021 | archive-url = https://web.archive.org/web/20210924122618/https://news.mydrivers.com/1/714/714927.htm | url-status = dead}}{{and then what|date=February 2024}} According to Nikkei, the company at that time expected to have been installing production equipment for 2 nm by 2023.{{Cite web|title=Taiwan gives TSMC green light for most advanced chip plant|url=https://asia.nikkei.com/Business/Tech/Semiconductors/Taiwan-gives-TSMC-green-light-for-most-advanced-chip-plant|access-date=24 August 2021|website=Nikkei Asia|language=en-GB|archive-date=4 November 2021|archive-url=https://web.archive.org/web/20211104002128/https://asia.nikkei.com/Business/Tech/Semiconductors/Taiwan-gives-TSMC-green-light-for-most-advanced-chip-plant|url-status=live}}{{and then what|date=February 2024}}

Intel's 2019 roadmap scheduled potentially equivalent 3 nm and 2 nm nodes for 2025 and 2027, respectively, and in December 2019 announced plans for 1.4 nm production in 2029.{{Citation |last=Cutress |first=Ian |title=Intel's Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm |url=https://www.anandtech.com/show/15217/intels-manufacturing-roadmap-from-2019-to-2029 |work=www.anandtech.com |archive-url=https://web.archive.org/web/20210112092150/https://www.anandtech.com/show/15217/intels-manufacturing-roadmap-from-2019-to-2029 |access-date=23 September 2020 |archive-date=12 January 2021 |url-status=live}}{{and then what|date=February 2024}}

At the end of 2020, seventeen European Union countries signed a joint declaration to develop their entire semiconductor industry, including developing process nodes as small as 2 nm, as well as designing and manufacturing custom processors, assigning up to €145 billion in funds.{{citation | url = https://www.eetimes.eu/eu-signs-e145bn-declaration-to-develop-next-gen-processors-and-2nm-technology/ | title = EU Signs €145bn Declaration to Develop Next Gen Processors and 2nm Technology | first = Nitin | last = Dahad | date = 9 December 2020 | work = www.eetimes.eu | access-date = 9 January 2021 | archive-date = 10 January 2021 | archive-url = https://web.archive.org/web/20210110005422/https://www.eetimes.eu/eu-signs-e145bn-declaration-to-develop-next-gen-processors-and-2nm-technology/ | url-status = live }}{{citation | url = https://ec.europa.eu/digital-single-market/en/news/joint-declaration-processors-and-semiconductor-technologies | title = Joint declaration on processors and semiconductor technologies | publisher = EU | date = 7 December 2020 | access-date = 9 January 2021 | archive-date = 11 January 2021 | archive-url = https://web.archive.org/web/20210111074903/https://ec.europa.eu/digital-single-market/en/news/joint-declaration-processors-and-semiconductor-technologies | url-status = live }}{{and then what|date=February 2024}}

In May 2021, IBM announced it had produced chips with 2 nm-class GAAFET transistors using three silicon layer nanosheets with a gate length of 12 nm.{{Citation| last=Nellis| first=Stephen| date=6 May 2021| title=IBM unveils 2-nanometer chip technology for faster computing| language=en| work=Reuters| url=https://www.reuters.com/article/us-ibm-semiconductors-idUSKBN2CN12S| access-date=6 May 2021| archive-date=7 May 2021| archive-url=https://web.archive.org/web/20210507065900/https://www.reuters.com/article/us-ibm-semiconductors-idUSKBN2CN12S| url-status=live}}{{citation | url = https://spectrum.ieee.org/ibm-introduces-the-worlds-first-2nm-node-chip | title = IBM Introduces the World's First 2-nm Node Chip | first = Dexter | last = Johnson | date = 6 May 2021 | work = IEEE Spectrum | access-date = 7 May 2021 | archive-date = 7 May 2021 | archive-url = https://web.archive.org/web/20210507092935/https://spectrum.ieee.org/nanoclast/semiconductors/nanotechnology/ibm-introduces-the-worlds-first-2nm-node-chip | url-status = live }}{{refn|group="notes"|12 nm gate length is the dimension defined by the IRDS 2020 to be associated with the "1.5 nm" process node:}}

In July 2021, Intel unveiled its process node roadmap from 2021 onwards. The company confirmed their 2 nm process node called "Intel 20A",{{refn|group="notes"|Under Intel's previous naming scheme this node was known as 'Intel 5 nm'.}} with "A" referring to an angstrom, a unit equivalent to 0.1 nanometers.{{Cite web|last=Cutress|first=Dr Ian|title=Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!|url=https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros|access-date=27 July 2021|date=26 July 2021|website=www.anandtech.com|archive-date=3 November 2021|archive-url=https://web.archive.org/web/20211103110548/https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros|url-status=live}} At the same time, they introduced a new process node naming scheme that aligned their product names with similar designations from their main competitors.{{citation | url = https://www.eetimes.com/intel-charts-manufacturing-course-to-2025/ | title = Intel Charts Manufacturing Course to 2025 | date = 27 July 2021 | work = www.eetimes.com | first = Brian | last = Santo | access-date = 11 August 2021 | archive-date = 19 August 2021 | archive-url = https://web.archive.org/web/20210819202119/https://www.eetimes.com/intel-charts-manufacturing-course-to-2025/ | url-status = live}} Intel's 20A node was at that time projected to have been their first to move from FinFET to gate-all-around transistors (GAAFET); Intel's version was named 'RibbonFET'. Their 2021 roadmap scheduled the Intel 20A node for volume production in 2024 and Intel 18A for 2025.{{and then what|date=February 2024}}

In October 2021, at Samsung Foundry Forum 2021, Samsung announced it would start mass production with its MBCFET (multi-bridge channel FET, Samsung's version of GAAFET) 2 nm process in 2025.{{cite press release|url=https://news.samsung.com/global/samsung-foundry-innovations-power-the-future-of-big-data-ai-ml-and-smart-connected-devices|title=Samsung Foundry Innovations Power the Future of Big Data, AI/ML and Smart, Connected Devices|website=Samsung|date=7 October 2021|access-date=9 May 2022|archive-date=8 April 2022|archive-url=https://web.archive.org/web/20220408182045/https://news.samsung.com/global/samsung-foundry-innovations-power-the-future-of-big-data-ai-ml-and-smart-connected-devices|url-status=live}}{{and then what|date=February 2024}}

In April 2022, TSMC announced its GAAFET N2 process technology would enter risk production phase at the end of 2024 and production phase in 2025.{{Cite web |last=Shilov |first=Anton |title=TSMC: Performance and Yields of 2nm on Track, Mass Production To Start In 2025 |url=https://www.anandtech.com/show/21413/tsmc-performance-and-yields-of-2nm-on-track-mass-production-to-start-in-2025 |access-date=10 September 2024 |website=www.anandtech.com}} In July 2022, TSMC announced that its N2 process technology was expected to feature backside power delivery and was expected to offer 10–15% higher performance at iso power or 20–30% lower power at iso performance and over 20% higher transistor density compared to N3E.{{cite web|url=https://investor.tsmc.com/english/encrypt/files/encrypt_file/reports/2022-07/185efaefea866a5e944499cda9eeecc65315449c/TSMC%202Q22%20Transcript.pdf|title=TSMC Q2 2022 Earnings Call|website=TSMC|date=14 July 2022|access-date=22 July 2022|archive-date=15 July 2022|archive-url=https://web.archive.org/web/20220715105421/https://investor.tsmc.com/english/encrypt/files/encrypt_file/reports/2022-07/185efaefea866a5e944499cda9eeecc65315449c/TSMC%202Q22%20Transcript.pdf|url-status=live}}{{and then what|date=February 2024}}

In July 2022, Samsung made a number of disclosures regarding the company's previously forthcoming process technology called "2GAP" (2nm Gate All-around Production): the process previously remained on track for 2025 launch into mass production; number of nanosheets was projected to increase from 3 in "3GAP" to 4; the company worked on several improvements of metallization, namely "single-grain metal" for low-resistance vias and direct-etched metal interconnect planned for 2GAP and beyond.{{cite web

|url=https://fuse.wikichip.org/news/6932/samsung-3nm-gaafet-enters-risk-production-discusses-next-gen-improvements/

|title=Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements

|website=WikiChip Fuse

|date=5 July 2022

}}{{and then what|date=February 2024}}

In August 2022, a consortium of Japanese companies funded a new venture with government support called Rapidus for manufacturing of 2 nm chips. Rapidus signed agreements with IMEC{{Cite web |last=Manners |first=David |date=16 December 2022 |title=Imec and Rapidus sign up for 2nm |url=https://www.electronicsweekly.com/news/business/811278-2022-12/ |website=Electronics Weekly |language=en}} and IBM{{Cite web |title=Japan to Manufacture 2nm Chips With a Little Help From IBM |url=https://www.pcmag.com/news/japan-to-manufacture-2nm-chips-with-a-little-help-from-ibm |date=13 December 2022 |first=Matthew |last=Humphries |website=PCMAG |language=en}} in December 2022.{{and then what|date=February 2024}}

In April 2023, at its Technology Symposium, TSMC introduced two more processes of its 2 nm technology platform: "N2P" featuring backside power delivery and scheduled for 2026, and "N2X" for high-performance applications. It was also revealed that the ARM Cortex-A715 core fabbed on the N2 process using a high-performance standard library was 16.4% faster at the same power, saved 37.2% of power at the same speed, or was ~10% faster and saved ~20% of power simultaneously at the same voltage (0.8 V) compared to the core fabbed on N3E using 3-2 fin library.

{{cite web

|url=https://www.anandtech.com/show/18832/tsmc-outlines-2nm-plans-n2p-brings-backside-power-delivery-in-2026-n2x-added-to-roadmap

|title=TSMC Outlines 2nm Plans: N2P Brings Backside Power Delivery in 2026, N2X Added To The Roadmap

|website=AnandTech

|date=26 April 2023

}}

In September 2024, Intel announced they would no longer be moving forward with their 20A process node, instead focusing on the development of 18A. Intel projected that avoiding ramping production of 20A could save over half a billion dollars. Intel noted that they'd successfully implemented RibbonFET gate-all-around (GAA) architecture and PowerVia backside power delivery in their 20A process, accelerating 18A development. Intel's Arrow Lake family of processors, which were meant to use Intel 20A, will instead have dies sourced from "external partners" and packaged by Intel.{{Cite press release |last=Sell |first=Ben |date=4 September 2024 |title=Continued Momentum for Intel 18A |url=https://www.intel.com/content/www/us/en/newsroom/opinion/continued-momentum-intel-18a.html |access-date=11 September 2024 |website=Intel |language=en}}

2 nm process nodes

class="wikitable" style="text-align:center"

!

!colspan="4" | Samsung{{cite web

|url=https://www.anandtech.com/print/16995/samsung-foundry-2nm-silicon-in-2025

|title=Samsung Foundry: 2nm Silicon in 2025

|website=AnandTech

|date=6 October 2021

}}{{cite web | url=https://www.anandtech.com/show/21377/samsung-foundry-update-2nm-unveil-in-june-2nd-gen-3nm-hits-production-this-year | title=Samsung Foundry Update: 2nm Unveil in June, Second-Gen SF3 3nm Hits Production This Year }}{{cite web | url=https://www.anandtech.com/show/21444/samsung-foundry-unveils-updated-roadmap-2nm-evolution-through-2027 | title=Samsung Foundry Unveils Updated Roadmap: BSPDN and 2nm Evolution Through 2027 }}{{cite web | url=https://library.techinsights.com/public/hg-asset/f32a0f17-5369-4c97-913c-b78d2ddd833b | title=IEDM 2024 – TSMC 2nm Process Disclosure – How Does it Measure Up | first=Scotten | last=Jones | website=TechInsights Platform | date=27 January 2025}}

! colspan="3" | TSMC

! colspan="2" | Intel

Process name

| SF2 || SF2P || SF2X || SF2Z

| N2 || N2P || N2X

| 20A || 18A

Transistor type

| colspan="4" |MBCFET

| colspan="3" |GAAFET

| colspan="2" |RibbonFET

Transistor density (MTr/mm2)

| 231 || {{Unknown}} || {{Unknown}} || {{Unknown}}

| colspan="2"|313 || {{Unknown}}

| {{Unknown}} || 238

SRAM bit-cell size (μm2)

| {{Unknown}} || {{Unknown}} || {{Unknown}} || {{Unknown}}

| 0.0175[https://www.tomshardware.com/tech-industry/sram-scaling-isnt-dead-after-all-tsmcs-2nm-process-tech-claims-major-improvements SRAM scaling isn't dead after all — TSMC's 2nm process tech claims major improvements] || {{Unknown}} || {{Unknown}}

| {{Unknown}} || 0.021[https://submissions.mirasmart.com/ISSCC2025/PDF/ISSCC2025AdvanceProgram.pdf A 0.021μm² High-Density SRAM in Intel-18A-RibbonFET Technology with PowerVia-Backside Power Delivery (19 Feb 2025)]

Transistor gate pitch (nm)

| {{Unknown}} || {{Unknown}} || {{Unknown}} || {{Unknown}}

| {{Unknown}} || {{Unknown}} || {{Unknown}}

| {{Unknown}} || 50https://www.hardwareluxx.de/index.php/news/hardware/prozessoren/66415-25-schneller-oder-36-sparsamer-intel-vergleicht-intel-18a-gegen-intel-3.html

Interconnect pitch (nm)

| {{Unknown}} || {{Unknown}} || {{Unknown}} || {{Unknown}}

| {{Unknown}} || {{Unknown}} || {{Unknown}}

| {{Unknown}} || 32

Release status

| {{no|2025 volume production}} || {{no|2026 volume production}} || {{no|2026 volume production}} || {{no|2027 volume production}}

| {{partial|2024 H2 risk production
2025 H2 volume production}}{{cite web | url=https://www.anandtech.com/show/21370/tsmc-2nm-update-n2-in-2025-n2p-loses-bspdn-nanoflex-optimizations | title=TSMC 2nm Update: N2 in 2025, N2P Loses Backside Power, and NanoFlex Brings Optimal Cells }} || {{no|2026 H2 volume production}} || {{no|2027 volume production}}https://www.tomshardware.com/tech-industry/tsmcs-2nm-n2-process-node-enters-production-this-year-a16-and-n2p-arriving-next-year

| {{no|2024 H1 risk production}}{{cite web | url=https://www.anandtech.com/show/20046/intel-unveils-meteor-lake-architecture-intel-4-heralds-the-disaggregated-future-of-mobile-cpus/2 | title=Intel Unveils Meteor Lake Architecture: Intel 4 Heralds the Disaggregated Future of Mobile CPUs }}
2024 volume production
Canceled 2024 || {{partial|2025 H1 risk production}}https://www.tomshardware.com/pc-components/cpus/intel-announces-18a-process-node-has-entered-risk-production-crucial-milestone-comes-as-company-ramps-to-panther-lake-chips
2025 H2 volume production

Beyond 2 nm

In July 2021, Intel reported that they planned 18A production for 2025. Intel's February 2022 roadmap added that 18A was previously expected to have delivered 10% improvement in performance per watt compared to Intel 20A. Intel's August 2024 newsroom announcement further indicated that the 18A process should be manufacturing-ready for 2025 H1.{{cite press release |url=https://www.intel.com/content/www/us/en/newsroom/news/intel-foundry-achieves-major-milestones.html|title=Intel 18A powered on and healthy, on track for next-gen client and server chip production next year|publisher=Intel|date=6 August 2024}}

In December 2021, vertical-transport FET (VTFET) CMOS logic transistor design with a vertical nanosheet was demonstrated at sub-45 nm gate pitch.{{cite book | chapter-url=https://ieeexplore.ieee.org/document/9720561 | doi=10.1109/IEDM19574.2021.9720561 | s2cid=247321213 | chapter=Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices | title=2021 IEEE International Electron Devices Meeting (IEDM) | year=2021 | last1=Jagannathan | first1=H. | last2=Anderson | first2=B. | last3=Sohn | first3=C-W. | last4=Tsutsui | first4=G. | last5=Strane | first5=J. | last6=Xie | first6=R. | last7=Fan | first7=S. | last8=Kim | first8=K-I. | last9=Song | first9=S. | last10=Sieg | first10=S. | last11=Seshadri | first11=I. | last12=Mochizuki | first12=S. | last13=Wang | first13=J. | last14=Rahman | first14=A. | last15=Cheon | first15=K-Y. | last16=Hwang | first16=I. | last17=Demarest | first17=J. | last18=Do | first18=J. | last19=Fullam | first19=J. | last20=Jo | first20=G. | last21=Hong | first21=B. | last22=Jung | first22=Y. | last23=Kim | first23=M. | last24=Kim | first24=S. | last25=Lallement | first25=R. | last26=Levin | first26=T. | last27=Li | first27=J. | last28=Miller | first28=E. | last29=Montanini | first29=P. | last30=Pujari | first30=R. | pages=26.1.1–26.1.4 | isbn=978-1-6654-2572-8 | display-authors=1 }}

In May 2022, IMEC presented a process technology roadmap which extends the current biannual cadence of node introduction and square-root-of-two node naming rule to 2036. The roadmap ends with process node "A2" (meant to represent a 2 angstrom node), named by analogy with TSMC's naming scheme to be introduced by then.{{cite web|url=https://www.tomshardware.com/news/imecs-sub-1nm-process-node-and-transistor-roadmap-until-2036-from-nanometers-to-the-angstrom-era|title=Imec Presents Sub-1nm Process and Transistor Roadmap Until 2036|website=Tom's Hardware|date=21 May 2022}}

Apart from the expected shrinking of transistor structures and interconnects, innovations forecasted by IMEC were as follows:{{and then what|date=February 2024}}

  • Transistor architecture (forksheet FET, CFET, CFET with atomic (2D material) channel);
  • Deployment of high-NA (0.55) EUV tools with the first $400 million tool to be completed at ASML in 2023, and the first production tool was shipped to and installed at Intel in 2024;{{cite press release |url=https://www.intel.com/content/www/us/en/newsroom/resources/intel-high-na-euv.html |title=High NA EUV at Intel |access-date=27 September 2024}}
  • Further reduction of standard cell height (eventually to "less than 4" tracks);
  • Back-side power distribution, buried power rails;
  • New materials (ruthenium for metallization (interconnects), graphene, WS2 monolayer for atomic channel);
  • New manufacturing techniques (subtractive metallization, direct metal etch);
  • Air gaps to further reduce relative permittivity of intermetal dielectric and, therefore, interconnect capacitance;
  • IC design innovations (2.5D chiplets, 3D interconnect), more advanced EDA tools.

In September 2022, Samsung presented their future business goals, which at that time included an aim to mass-produce 1.4 nm by 2027.{{cite press release|url=https://news.samsung.com/global/samsung-electronics-unveils-plans-for-1-4nm-process-technology-and-investment-for-production-capacity-at-samsung-foundry-forum-2022|title=Samsung Electronics Unveils Plans for 1.4nm Process Technology and Investment for Production Capacity at Samsung Foundry Forum 2022|publisher=Samsung|date=4 October 2022}}

As of 2023, Intel, TSMC and Samsung have all demonstrated CFET transistors. These transistors are made up of two stacked horizontal nanosheet transistors, one transistor is of the p-type (a pFET transistor) and the other transistor is of the n-type (an nFET transistor).{{cite web | url=https://spectrum.ieee.org/cfet-intel-samsung-tsmc | title=Intel, Samsung, and TSMC Demo 3D-Stacked Transistors - IEEE Spectrum}}

Notes

{{reflist|group="notes"}}

References

{{reflist|refs =

{{citation | title = TSMC: Chip Scaling Could Accelerate | first = Alan | last = Patterson | date = 12 September 2018 | url = https://www.eetimes.com/tsmc-chip-scaling-could-accelerate/ | work = www.eetimes.com | access-date = 23 September 2020}}

{{citation | url = https://www.eetasia.com/news/article/SPIE-Conference-Predicts-Bumpy-Chip-Roadmap | title = SPIE Conference Predicts Bumpy Chip Roadmap | date = 4 March 2019 | first = Rick | last = Merritt | work = www.eetasia.com | access-date = 23 September 2020 | archive-date = 27 June 2019 | archive-url = https://web.archive.org/web/20190627031404/https://www.eetasia.com/news/article/SPIE-Conference-Predicts-Bumpy-Chip-Roadmap | url-status = live }}

}}

Further reading

  • {{citation| url = https://www.eetasia.com/18032601-2nm-end-of-the-road/ | title = 2nm: End of the Road ? | first = Rick | last = Merritt | date = 26 March 2018 | work = www.eetasia.com }}

{{sequence

| prev = "3 nm" (FinFET/GAAFET)

| list = MOSFET semiconductor device fabrication process

| next = "1 nm" (FinFET/GAAFET)

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