ARM Cortex-X1

{{Infobox CPU

| name = ARM Cortex-X1

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| produced-start = 2020

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| designfirm = ARM Ltd.

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| fastest = 3.0 GHz in phones and 3.3 GHz in tablets/laptops

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| address-width = 40-bit

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| l1cache = {{Nowrap|128 KiB}} {{Small|({{Nowrap|64 KiB}} I-cache with parity, {{Nowrap|64 KiB}} D-cache)}} per core

| l2cache = {{Nowrap|512–1024 KiB}} per core

| l3cache = {{Nowrap|512 KiB – 8 MiB}} {{Small|(optional)}}

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| microarch = ARM Cortex-X1

| arch = ARMv8-A: A64, A32, and T32 {{Small|(at the EL0 only)}}

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| extensions = ARMv8.1-A, ARMv8.2-A, cryptography, RAS, ARMv8.3-A LDAPR instructions, ARMv8.4-A dot product

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| numcores = 1–4 per cluster

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| pcode1 = Hera

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| variant = ARM Cortex-A78, ARM Neoverse V1

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| successor = ARM Cortex-X2

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The ARM Cortex-X1 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin design centre as part of ARM's Cortex-X Custom (CXC) program.{{Cite web|title=Introducing the Arm Cortex-X Custom program|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-cortex-x-custom-program|access-date=2020-06-18|website=community.arm.com|language=en}}{{Cite web|last=Ltd|first=Arm|title=Cortex-X Custom CPU program|url=https://www.arm.com/products/cortex-x|access-date=2020-06-18|website=Arm {{!}} The Architecture for the Digital World|language=en}}

Design

The Cortex-X1 design is based on the ARM Cortex-A78, but redesigned for purely performance instead of a balance of performance, power, and area (PPA).

The Cortex-X1 is a 5-wide decode out-of-order superscalar design with a 3K macro-OP (MOPs) cache. It can fetch 5 instructions and 8 MOPs per cycle, and rename and dispatch 8 MOPs, and 16 μOPs per cycle. The out-of-order window size has been increased to 224 entries. The backend has 15 execution ports with a pipeline depth of 13 stages and the execution latencies consists of 10 stages. It also features 4x128b SIMD units.{{Cite web|last=Frumusanu|first=Andrei|title=Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence|url=https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging|access-date=2020-06-18|website=www.anandtech.com}}{{Cite web|date=2020-05-26|title=Arm Cortex-X1: The First From The Cortex-X Custom Program|url=https://fuse.wikichip.org/news/3543/arm-cortex-x1-the-first-from-the-cortex-x-custom-program/|access-date=2020-06-18|website=WikiChip Fuse|language=en-US}}{{Cite web|last=McGregor|first=Jim|title=Arm Unleashes CPU Performance With Cortex-X1|url=https://www.forbes.com/sites/tiriasresearch/2020/05/26/arm-unleashes-cpu-performance-with-cortex-x1/|access-date=2020-06-18|website=Forbes|language=en}}{{Cite web|date=2020-05-26|title=Arm Cortex-X1 and Cortex-A78 CPUs: Big cores with big differences|url=https://www.androidauthority.com/arm-cortex-x1-cortex-a78-1119666/|access-date=2020-06-18|website=Android Authority|language=en-US}}

ARM claims the Cortex-X1 offers 30% faster integer and 100% faster machine learning performance than the ARM Cortex-A77.

The Cortex-X1 supports ARM's DynamIQ technology, expected to be used as high-performance cores when used in combination with the ARM Cortex-A78 mid and ARM Cortex-A55 little cores.

Architecture changes in comparison with [[ARM Cortex-A78]]

Around 20% performance improvement (+30% from A77){{Cite web|title=Cortex-X1 – Microarchitectures – ARM – WikiChip|url=https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-x1|access-date=2021-02-13|website=en.wikichip.org|language=en}}
30% faster integer
100% faster machine learning performance
Out-of-order window size has been increased to 224 entries (from 160 entries)
Up to 4x128b SIMD units (from 2x128b)
15% more silicon area
5-way decode (from 4-way)
8 MOPs/cycle decoded cache bandwidth (from 6 MOPs/cycle)
64 KB L1D + 64 KB L1I (from 32/64 KB L1)
Up to 1 MB/core L2 cache (from 512 KB/core max)
Up to 8 MB L3 cache (from 4 MB max)

Licensing

The Cortex-X1 is available as SIP core to partners of their Cortex-X Custom (CXC) program, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).

Usage

Samsung Exynos 2100{{Cite web|title=Exynos 2100 5G Mobile Processor: Specs, Features {{!}} Samsung|url=https://www.samsung.com/semiconductor/minisite/exynos/products/mobileprocessor/exynos-2100/|access-date=2021-01-13|website=Samsung Semiconductor|language=en}}
Qualcomm Snapdragon 888(+){{Broken anchor|date=2024-07-30|bot=User:Cewbot/log/20201008/configuration|target_link=List of Qualcomm Snapdragon processors#Snapdragon 888/888+ 5G (2021)|reason= The anchor (Snapdragon 888/888+ 5G (2021)) has been deleted.}}{{Cite web|title=Qualcomm Snapdragon 888 5G Mobile Platform {{!}} Latest 5G Snapdragon Processor {{!}} Qualcomm|url=https://www.qualcomm.com/products/snapdragon-888-5g-mobile-platform|access-date=2021-01-13|website=www.qualcomm.com}}
Google Tensor{{Cite web|url=https://arstechnica.com/gadgets/2021/10/the-google-silicon-team-gives-us-a-tour-of-the-pixel-6s-tensor-soc/|title=The "Google Silicon" team gives us a tour of the Pixel 6's Tensor SoC|website=Ars Technica|last=Amadeo|first=Ron|date=2021-10-19}}

References

Category:ARM processors