ARM Cortex-X2
{{Short description|Microprocessor core model by ARM}}
{{Infobox CPU
|name=ARM Cortex-X2
|image=
|image_size=
|alt=
|caption=
|produced-start=2021
|produced-end=
|soldby=
|designfirm=Arm
|manuf1=
|cpuid=
|code=
|slowest=2.85
|fastest=3.0
|data-width=
|address-width=40-bit
|virtual-width=
|l1cache={{Nowrap|128 KiB}}
{{Small|({{Nowrap|64 KiB}} I-cache with parity,
{{Nowrap|64 KiB}} D-cache) per core}}
|l2cache={{Nowrap|256–1024 KiB}} {{Small|per core}}
|l3cache={{Nowrap|512 KiB – 16 MiB}} {{Small|(optional)}}
|l4cache=
|llcache=
|application=
|size-from=
|size-to=
|arch=ARMv9.0-A
|microarch=ARM Cortex-X2
|extensions=
|instructions=
|numcores=1–12 (per cluster)
|transistors=
|gpu=
|co-processor=
|pack1=
|sock1=
|core1=
|pcode1=Matterhorn ELP
|model1=
|brand1=
|variant=ARM Cortex-A710
|predecessor=ARM Cortex-X1
|successor=ARM Cortex-X3
}}
The ARM Cortex-X2 is a CPU implementing the ARMv9-A 64-bit instruction set designed by ARM Holdings' Austin design centre as part of ARM's Cortex-X Custom (CXC) program.{{Cite web |title=Cortex-X Custom CPU program |url=https://www.arm.com/products/cortex-x |access-date=2021-12-02 |website=Arm |language=en}}
It forms part of Arm's Total Compute Solutions 2021 (TCS21) along with Arm's Cortex-A710, Cortex-A510, Mali-G710 and CoreLink CI-700/NI-700.{{Cite web |date=2021-05-25 |title=Arm Total Compute solutions powering decade of compute - Arm Community |url=https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/total-compute-solutions |access-date=2023-09-16 |website=Arm |language=en}}
Architecture changes in comparison with [[ARM Cortex-X1]]
The processor implements the following changes:{{Cite web |date=2021-05-25 |title=Arm Launches Its New Flagship Performance Armv9 Core: Cortex-X2 |url=https://fuse.wikichip.org/news/5269/arm-launches-its-new-flagship-performance-armv9-core-cortex-x2/ |access-date=2021-12-03 |website=WikiChip Fuse |language=en-US}}
- ARMv9.0{{Cite web |title=Documentation – Arm Developer |url=https://developer.arm.com/documentation/101803/0200/ |url-status=live |archive-url=https://web.archive.org/web/20211203013119/https://developer.arm.com/documentation/101803/0200/ |archive-date=2021-12-03 |access-date=2021-12-03 |website=arm.com}}
- 10 cycle pipeline down from 11, created by reducing the dispatch stage from 2 cycles to 1
- Reorder buffer (ROB) increased by 30% from 224 entries to 288
- dTLB increased by 20% from 40 entries to 48
- SVE2 SIMD support
- Bfloat16 data type support
- Support for Aarch32 removed
- DSU-110
- Up to 12 cores (up from 8 cores)
- Up to 16M L3 cache (up from 8 MB)
- CoreLink CI-700/NI-700
- Up to 32MB SLC
Performance claims:
- Comparing the Cortex-X2{{Cite web |title=Arm Announces Mobile Armv9 CPU Microarchitectures: Cortex-X2, Cortex-A710 & Cortex-A510 |url=https://www.anandtech.com/show/16693/arm-announces-mobile-armv9-cpu-microarchitectures-cortexx2-cortexa710-cortexa510 |access-date=2021-12-03 |website=anandtech.com}} to the Cortex-X1 with the same process,
clock speed, and 4MB of L3 cache (also known as ISO-process): - 16% greater integer performance / IPC
- 100% greater ML performance
- 30% peak performance improvement over the Cortex-X1 in smartphones
:(3.3 GHz, 1MB L2, 8MB L3)
- 40% faster than an Intel Core i5-1135G7 at 15W (3.5 GHz, 1MB L2, 16MB L3)
Architecture comparison
:;"Prime" core
| class="wikitable sortable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 100%; text-align:center; |
| uArch |
|---|
| Code name
|Hercules |Hera |Matterhorn-ELP |Makalu-ELP |Hunter-ELP |Blackhawk |Travis |
| Architecture
| colspan="2" |ARMv8.2 | colspan="2" |ARMv9 | colspan="3" |ARMv9.2 |
| Peak clock speed
| colspan="3" |~3.0 GHz |~3.3 GHz |~3.4 GHz |~3.8 GHz |~4.2 GHz |
| Decode width
|4 | colspan="2" |5 |6 |10 | |
| Dispatch
|6/cycle | colspan="3" |8/cycle | colspan="2" |10/cycle | |
| Max in-flight
|2x 160 |2x 224 |2x 288 |2x 320 |2x 384 |2x 768 | |
| L0 (Mops entries)
|1536 | | |
| L1-I + L1-D
|32+32 KiB | colspan="2" |64+64 KiB | colspan="2" |64+64 KiB |64+64 KiB | |
| L2
|128–512 KiB | colspan="3" |0.25–1 MiB |0.5–2 MiB |2–3 MiB | |
| L3
| colspan="2" |0–16 MiB | colspan="2" |0–32 MiB | |
Usage
- MediaTek • Dimensity 9000(+)
- Qualcomm • Snapdragon 7+ Gen 2{{cite web |url=https://www.qualcomm.com/products/application/smartphones/snapdragon-7-series-mobile-platforms/snapdragon-7-plus-gen-2-mobile-platform |title= Snapdragon 7+ Gen 2 Mobile Platform |publisher= Qualcomm |access-date= 17 March 2023}} • Snapdragon 8/8+ Gen 1{{Cite web |title=Qualcomm Snapdragon 8 Gen 1 Mobile Platform {{!}} Latest 5G Snapdragon Processor |url=https://www.qualcomm.com/products/snapdragon-8-gen-1-mobile-platform |access-date=2021-12-02 |website=qualcomm.com |date=17 November 2021}}{{cite web |url=https://www.anandtech.com/show/17102/snapdragon-8-gen-1-performance-preview-sizing-up-cortex-x2/2#:~:text=The%20small%20frequency%20bump%20from,efficiency%20when%20running%20these%20workloads |title=The Snapdragon 8 Gen 1 Performance Preview: Sizing Up Cortex-X2 |date=December 14, 2021 |publisher=AnandTech |access-date=March 3, 2022}}
- Samsung • Exynos 2200{{Cite web |title = Exynos 2200 | Processor |url=https://www.samsung.com/semiconductor/minisite/exynos/products/mobileprocessor/exynos-2200/}}
See also
- ARM Cortex-A710, related high performance microarchitecture
- Comparison of ARMv8-A cores, ARMv8 family