ARM Neoverse#Neoverse V2
{{Short description|Group of 64-bit ARM processor cores}}
The ARM Neoverse is a group of 64-bit ARM processor cores licensed by Arm Holdings. The cores are intended for datacenter, edge computing, and high-performance computing use. The group consists of ARM Neoverse V-Series, ARM Neoverse N-Series, and ARM Neoverse E-Series.{{Cite web|url=https://www.arm.com/products/silicon-ip-cpu/neoverse|title=Arm Neoverse}}{{Cite web|url=https://www.nextplatform.com/2021/04/27/arm-puts-some-muscle-into-future-neoverse-server-cpu-designs/|title=Arm Puts Some Muscle Into Future Neoverse Server CPU Designs|date=27 April 2021 }}
Neoverse V-Series
The Neoverse V-Series processors are intended for high-performance computing.
= Neoverse V1 =
Neoverse V1 (code named Zeus{{cite web | url=https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_v1 | title=Neoverse V1 - Microarchitectures - ARM - WikiChip }}) is derived from the Cortex-X1{{cite web | url=https://www.anandtech.com/show/16640/arm-announces-neoverse-v1-n2-platforms-cpus-cmn700-mesh/2 | title=Arm Announces Neoverse V1, N2 Platforms & CPUs, CMN-700 Mesh: More Performance, More Cores, More Flexibility }} and implements the ARMv8.4-A instruction set and some part of ARMv8.6-A.{{cite web| url=https://developer.arm.com/Processors/Neoverse%20V1 |title=Neoverse V1 |access-date=2023-04-16}} It was officially announced by Arm on September 22, 2020.{{Cite web |title=Accelerating the next generation cloud-to-edge infrastructure |access-date=2023-04-16 |url=https://www.arm.com/company/news/2020/09/accelerating-the-next-gen-cloud-to-edge-infrastructure }} It is said to be initially realized with a 7 nm process from TSMC. One of the changes from the X1 is that it supports SVE 2x256-bit.
According to The Next Platform, the AWS Graviton3 is based on the Neoverse V1.{{Cite web|url=https://www.nextplatform.com/2022/01/04/inside-amazons-graviton3-arm-server-processor/|title=Inside Amazon's Graviton3 Arm Server Processor|date=4 January 2022 }}{{Cite web |date=2022-05-29 |title=Graviton 3: First Impressions |url=https://chipsandcheese.com/2022/05/29/graviton-3-first-impressions/ |access-date=2023-09-16 |website=Chips and Cheese |language=en-US}}
= Neoverse V2 =
Neoverse V2 (code named Demeter) is derived from the ARM Cortex-X3 and implements the ARMv9.0-A instruction set. It was officially announced by Arm on September 14, 2022.{{cite web | url=https://www.arm.com/company/news/2022/09/redefining-the-global-computing-infrastructure-with-next-generation-arm-neoverse-platforms | title=Redefining the global computing infrastructure with next-generation Arm Neoverse platforms }}{{Cite web |title=Neoverse V2 |url=https://developer.arm.com/Processors/Neoverse%20V2 |access-date=2023-09-16 |website=developer.arm.com}} NVIDIA Grace,{{cite web |url=https://www.nvidia.com/en-us/data-center/grace-cpu/ |title= NVIDIA Grace CPU and Arm Architecture |publisher= NVIDIA |access-date=2023-04-16}} AWS Graviton4{{cite web |title=Join the preview for new memory-optimized, AWS Graviton4-powered Amazon EC2 instances (R8g) |url=https://aws.amazon.com/blogs/aws/join-the-preview-for-new-memory-optimized-aws-graviton4-powered-amazon-ec2-instances-r8g/ |access-date=23 December 2023 |publisher=AWS}} and Google Axion{{Cite web |title=Introducing Google's new Arm-based CPU |url=https://cloud.google.com/blog/products/compute/introducing-googles-new-arm-based-cpu |access-date=2024-04-10 |website=Google Cloud Blog |language=en-US}} are based on the Neoverse V2.
Notable changes from the Neoverse V1:{{Cite web |date=2023-09-11 |title=Hot Chips 2023: Arm's Neoverse V2 |url=https://chipsandcheese.com/2023/09/11/hot-chips-2023-arms-neoverse-v2/ |access-date=2023-09-16 |website=Chips and Cheese |language=en-US}}
- BTB capacity: 12K entries
- TAGE predictor: 8-table
- micro-op cache: 1536 entries (reduced for efficiency)
- Decode width: 6
- Rename / Dispatch width: 8
- ROB: 320 entry
- Execution ports: 15
- L2 cache: 1024-2048 KB per core
- CMN-700 mesh interconnect
- Up to 256 cores per die
- Up to 512 MB SLC
- Up to 4 TB/s bandwidth
= Neoverse V3 =
Neoverse V3 (code named Poseidon) was teased by Arm alongside the V2 and E2 announcements. It is targeted for systems including DDR5, PCIe gen6, and CXL 3.0. The codename Poseidon was first used for the generation succeeding Zeus, now V1, and targeted for 2021 on a 5nm node.{{Cite web |last=Kennedy |first=Patrick |date=2018-10-16 |title=Arm Neoverse Brand Launched for Infrastructure Servers to Edge |url=https://www.servethehome.com/arm-neoverse-brand-launched-for-infrastructure-servers-to-edge/ |access-date=2024-02-02 |website=ServeTheHome |language=en-US}}
Neoverse N-Series
The Neoverse N-Series processors are intended for core datacenter usage.
= Neoverse N1 =
On February 20, 2019, Arm announced the Neoverse N1 microarchitecture (code named Ares) derived from the Cortex-A76 redesigned for infrastructure/server applications. The reference design supports up to 64 or 128 Neoverse N1 cores.{{Cite web|last=Frumusanu|first=Andrei|title=Arm Announces Neoverse N1 & E1 Platforms & CPUs: Enabling A Huge Jump In Infrastructure Performance|url=https://www.anandtech.com/show/13959/arm-announces-neoverse-n1-platform|access-date=2020-06-17|website=www.anandtech.com}}{{Cite web|date=2019-02-20|title=Arm Launches New Neoverse N1 and E1 Server Cores|url=https://fuse.wikichip.org/news/2075/arm-launches-new-neoverse-n1-and-e1-server-cores/|access-date=2020-06-17|website=WikiChip Fuse|language=en-US}}
Notable changes from the Cortex-A76:
- Coherent I-cache and D-cache with 4-cycle LD-use
- L2 cache: 512–1024 KB per core
- Mesh interconnect instead of 1–4 cores per cluster
Neoverse N1 implements the ARMv8.2-A instruction set.
The Ampere Altra (2-socket 80-core) and AWS Graviton2 (64-core) CPU platforms are based on Neoverse N1 cores and were released in 2020.{{Cite web|last=Frumusanu|first=Andrei|title=Arm Announces Neoverse V1, N2 Platforms & CPUs, CMN-700 Mesh: More Performance, More Cores, More Flexibility|url=https://www.anandtech.com/show/16640/arm-announces-neoverse-v1-n2-platforms-cpus-cmn700-mesh|access-date=2022-05-05|website=www.anandtech.com}}
= Neoverse N2 =
The Neoverse N2 (code named Perseus) is derived from the Cortex-A710 and implements the ARMv9.0-A instruction set. It was officially announced by Arm on September 22, 2020. On August 28, 2023, Arm announced the Neoverse CSS N2 (Genesis), a customizable CPU subsystem implementation by Arm to reduce the time to market for customers.{{Cite web |date=2023-08-28 |title=Neoverse CSS Fastest Path to Production Silicon - Infrastructure Solutions blog - Arm Community blogs - Arm Community |url=https://community.arm.com/arm-community-blogs/b/infrastructure-solutions-blog/posts/neoverse-compute-subsystems-css-the-fastest-path-to-production-silicon |access-date=2023-09-16 |website=community.arm.com |language=en}}{{Cite web |last=Ltd |first=Arm |title=Neoverse Compute Subsystems |url=https://www.arm.com/products/neoverse-compute-subsystems |access-date=2023-09-16 |website=Arm {{!}} The Architecture for the Digital World |language=en}}{{Cite web |date=2023-09-13 |title=Arm at HC35 (2023): CSS-Genesis |url=https://chipsandcheese.com/2023/09/13/arm-at-hc35-2023-css-genesis/ |access-date=2023-09-16 |website=Chips and Cheese |language=en-US}}{{Cite web |last=Morgan |first=Timothy Prickett |date=2023-08-31 |title=Arm Gets Closer To Creating Full-Blown Server CPU Designs - The Next Platform |url=https://www.nextplatform.com/2023/08/31/arm-gets-closer-to-creating-full-blown-server-cpu-designs/,%20https://www.nextplatform.com/2023/08/31/arm-gets-closer-to-creating-full-blown-server-cpu-designs/ |access-date=2023-09-16 |website=www.nextplatform.com |language=en-US}} Microsoft Azure Cobalt 100 128 Core CPU and Alibaba Yitian 710 use Neoverse N2.{{cite web |last1=Lee |first1=John |title=Microsoft Azure Cobalt 100 128 Core Arm Neoverse N2 CPU Launched |url=https://www.servethehome.com/microsoft-azure-cobalt-100-128-core-arm-neoverse-n2-cpu-launched/ |website=ServeTheHome |archive-url=https://web.archive.org/web/20240319130019/https://www.servethehome.com/microsoft-azure-cobalt-100-128-core-arm-neoverse-n2-cpu-launched/ |archive-date=19 March 2024 |date=16 November 2023 |url-status=live}}{{cite web |last1=Yang |first1=Willen |url=https://community.arm.com/arm-community-blogs/b/infrastructure-solutions-blog/posts/accelerated-llm-inference-on-arm-neoverse-n2 |archive-url=https://web.archive.org/web/20240717214539/https://community.arm.com/arm-community-blogs/b/infrastructure-solutions-blog/posts/accelerated-llm-inference-on-arm-neoverse-n2 | archive-date=17 July 2024 |date=18 June 2024 |title=Accelerated LLM inference on Arm Neoverse N2 |website=Arm Community Blogs |url-status=live}}
Notable changes from the Neoverse N1:{{Cite web |date=2023-08-18 |title=ARM's Neoverse N2: Cortex A710 for Servers |url=https://chipsandcheese.com/2023/08/18/arms-neoverse-n2-cortex-a710-for-servers/ |access-date=2023-09-16 |website=Chips and Cheese |language=en-US}}{{Cite web |last=Frumusanu |first=Andrei |title=Arm Announces Neoverse V1, N2 Platforms & CPUs, CMN-700 Mesh: More Performance, More Cores, More Flexibility |url=https://www.anandtech.com/show/16640/arm-announces-neoverse-v1-n2-platforms-cpus-cmn700-mesh |access-date=2023-09-16 |website=www.anandtech.com}}
- BTB capacity: 8K entries
- micro-op cache: 1536 entries
- Rename / Dispatch width: 5
- ROB: 160+ entry
- Pipeline depth: 10 cycles
- Execution ports: 13
- SVE2 support
- CMN-700 mesh interconnect
= Neoverse N-Next =
Neoverse E-Series
The Neoverse E-Series processors are intended for edge computing. They are designed for increased data throughput at decreased power consumption.
= Neoverse E1 =
Neoverse E1 is derived from the Cortex-A65AE{{cite web | url=https://www.anandtech.com/show/13959/arm-announces-neoverse-n1-platform/5 | title=Arm Announces Neoverse N1 & E1 Platforms & CPUs: Enabling a Huge Jump in Infrastructure Performance }} and implements the ARMv8.2-A instruction set. It support SMT.
= Neoverse E2 =
Neoverse E2 is derived from the Cortex-A510{{cite web | url=https://www.anandtech.com/show/17575/arm-announces-neoverse-v2-and-e2-the-next-generation-of-arm-server-cpu-cores | title=Arm Announces Neoverse V2 and E2: The Next Generation of Arm Server CPU Cores }} and implements the ARMv9-A instruction set.
= Neoverse E-Next =
Matrix multiplication theoretical performance
| class="wikitable" style="text-align:right;"
|+ ops/cycle per core |
| style="text-align:left;"
! ! INT8 ! BF16 ! FP32 ! FP64 |
| style="text-align:left;" | Neoverse N1{{Cite web |title=Arm Announces Neoverse V1, N2 Platforms & CPUs, CMN-700 Mesh: More Performance, More Cores, More Flexibility |access-date=2023-04-16 |url= https://www.anandtech.com/show/16640/arm-announces-neoverse-v1-n2-platforms-cpus-cmn700-mesh/2 }}
| 64 | 32 | 16 | 8 |
|---|
| style="text-align:left;" | Neoverse N2
| 128 | 64 | 16 | 8 |
| style="text-align:left;" | Neoverse V1
| 256 | 128 | 32 | 16 |
| style="text-align:left;" | Intel 3rd Gen Xeon SP{{cite web |url=https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2022-12/accelerate-ai-with-amx-sb.pdf |title=Accelerate Artificial Intelligence (AI) Workloads with Intel Advanced Matrix Extensions (Intel AMX) |access-date=2023-04-13 |publisher=Intel}}
| 256 | {{n/a}} | 64 | 32 |
| style="text-align:left;" | Intel 4th Gen Xeon SP
| 2048 | 1024 | 64 | 32 |
Successors
With code name Poseidon a successor for Neoverse V1 (aka Zeus){{cite web | url=https://en.wikichip.org/wiki/arm_holdings/microarchitectures/poseidon | title=Poseidon - Microarchitectures - ARM - WikiChip }} was first publicly mentioned on TechCon 2018. Actual introduction (used by third party chip designers in their products) was given in form of a rough target date of 2021. Its initial realization process is said to be 5 nm by TSMC.