ARM big.LITTLE

For a given library of CMOS logic, active power increases as the logic switches more per second, while leakage increases with the number of transistors. So, CPUs designed to run fast are different from CPUs designed to save power. When a very fast out-of-order CPU is idling at very low speeds, a CPU with much less leakage (fewer transistors) could do the same work. For example, it might use a smaller (fewer transistors) memory cache, or a simpler microarchitecture such as removing out-of-order execution. big.LITTLE is a way to optimize for both cases: Power and speed, in the same system.

In practice, a big.LITTLE system can be surprisingly inflexible. One issue is the number and types of power and clock domains that the IC provides. These may not match the standard power management features offered by an operating system. Another is that the CPUs no longer have equivalent abilities, and matching the right software task to the right CPU becomes more difficult. Most of these problems are being solved by making the electronics and software more flexible.

There are three ways{{cite web | url=http://blogs.arm.com/soc-design/1009-ten-things-to-know-about-biglittle/ | title=Ten Things to Know About big.LITTLE | author=Brian Jeff | date=18 June 2013 | publisher=ARM Holdings | access-date=2013-09-17 | archive-url=https://web.archive.org/web/20130910163539/http://blogs.arm.com/soc-design/1009-ten-things-to-know-about-biglittle/ | archive-date=10 September 2013 | url-status=dead }} for the different processor cores to be arranged in a big.LITTLE design, depending on the scheduler implemented in the kernel.{{cite web | url=http://www.linaro.org/linaro-blog/2013/07/10/big-little-software-update/ | title=big.LITTLE Software Update | author=George Grey | publisher=Linaro | date=10 July 2013 | access-date=2013-09-17 | archive-url=https://web.archive.org/web/20131004230806/http://www.linaro.org/linaro-blog/2013/07/10/big-little-software-update/ | archive-date=4 October 2013 | url-status=dead }}

File:Big.Little Cluster Switching.png

The clustered model approach is the first and simplest implementation, arranging the processor into identically sized clusters of "big" or "LITTLE" cores. The operating system scheduler can only see one cluster at a time; when the load on the whole processor changes between low and high, the system transitions to the other cluster. All relevant data are then passed through the common L2 cache, the active core cluster is powered off and the other one is activated. A Cache Coherent Interconnect (CCI) is used. This model has been implemented in the Samsung Exynos 5 Octa (5410).{{cite web | url=http://www.embedded.com/electronics-news/4419448/Benchmarking-ARM-s-big-little-architecture | title=Benchmarking ARM's big-little architecture | author=Peter Clarke | date=6 August 2013 | access-date=2013-09-17}}

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File:In Kernel Switcher.jpg

CPU migration via the in-kernel switcher (IKS) involves pairing up a 'big' core with a 'LITTLE' core, with possibly many identical pairs in one chip. Each pair operates as one so-termed virtual core, and only one real core is (fully) powered up and running at a time. The 'big' core is used when the demand is high and the 'LITTLE' core is employed when demand is low. When demand on the virtual core changes (between high and low), the incoming core is powered up, running state is transferred, the outgoing is shut down, and processing continues on the new core. Switching is done via the cpufreq framework. A complete big.LITTLE IKS implementation was added in Linux 3.11. big.LITTLE IKS is an improvement of cluster migration ({{Section link||Clustered switching|nopage=y}}), the main difference being that each pair is visible to the scheduler.

A more complex arrangement involves a non-symmetric grouping of 'big' and 'LITTLE' cores. A single chip could have one or two 'big' cores and many more 'LITTLE' cores, or vice versa. Nvidia created something similar to this with the low-power 'companion core' in their Tegra 3 System-on-Chip.

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File:Global Task Scheduling.jpg

The most powerful use model of big.LITTLE architecture is heterogeneous multi-processing (HMP), which enables the use of all physical cores at the same time. Threads with high priority or computational intensity can in this case be allocated to the "big" cores while threads with less priority or less computational intensity, such as background tasks, can be performed by the "LITTLE" cores.{{citation|url=http://www.arm.com/files/downloads/big.LITTLE_Final.pdf |title=Big.LITTLE Processing with ARM Cortex-A15 & Cortex-A7 |date=September 2013 |publisher=ARM Holdings |access-date=2013-09-17 |url-status=dead |archive-url=https://web.archive.org/web/20120417183714/http://www.arm.com/files/downloads/big.LITTLE_Final.pdf |archive-date=17 April 2012 }}

This model has been implemented in the Samsung Exynos starting with the Exynos 5 Octa series (5420, 5422, 5430),{{cite web |title =Samsung Unveils New Products from its System LSI Business at Mobile World Congress |publisher =Samsung Tomorrow |url =http://global.samsungtomorrow.com/?p=34630 |access-date =26 February 2013 |archive-date =16 March 2014 |archive-url =https://web.archive.org/web/20140316044700/http://global.samsungtomorrow.com/?p=34630 |url-status =dead }} and Apple A series processors starting with the Apple A11.{{Cite news|url=https://www.apple.com/newsroom/2017/09/the-future-is-here-iphone-x/|title=The future is here: iPhone X|work=Apple Newsroom|access-date=2018-02-25|language=en-US}}

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The paired arrangement allows for switching to be done transparently to the operating system using the existing dynamic voltage and frequency scaling (DVFS) facility. The existing DVFS support in the kernel (e.g. cpufreq in Linux) will simply see a list of frequencies/voltages and will switch between them as it sees fit, just like it does on the existing hardware. However, the low-end slots will activate the 'Little' core and the high-end slots will activate the 'Big' core. This is the early solution provided by Linux's "deadline" CPU scheduler (not to be confused with the I/O scheduler with the same name) since 2012.{{cite web |last1=McKenney |first1=Paul |title=A big.LITTLE scheduler update |url=https://lwn.net/Articles/501501/ |website=LWN.net |date=12 June 2012}}

Alternatively, all the cores may be exposed to the kernel scheduler, which will decide where each process/thread is executed. This will be required for the non-paired arrangement but could possibly also be used on the paired cores. It poses unique problems for the kernel scheduler, which, at least with modern commodity hardware, has been able to assume all cores in a SMP system are equal rather than heterogeneous. A 2019 addition to Linux 5.0 called Energy Aware Scheduling is an example of a scheduler that considers cores differently.{{cite web |last1=Perret |first1=Quentin |title=Energy Aware Scheduling merged in Linux 5.0 |url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/energy-aware-scheduling-in-linux |website=community.arm.com |language=en |date=25 February 2019}}{{cite web |title=Energy Aware Scheduling |url=https://www.kernel.org/doc/html/latest/scheduler/sched-energy.html |website=The Linux Kernel documentation}}

• Finer-grained control of workloads that are migrated between cores. Because the scheduler is directly migrating tasks between cores, kernel overhead is reduced and power savings can be correspondingly increased.
• Implementation in the scheduler also makes switching decisions faster than in the cpufreq framework implemented in IKS.
• The ability to easily support non-symmetrical clusters (e.g. with 2 Cortex-A15 cores and 4 Cortex-A7 cores).
• The ability to use all cores simultaneously to provide improved peak performance throughput of the SoC compared to IKS.

In May 2017, ARM announced DynamIQ as the successor to big.LITTLE.{{cite news|last1=Humrick|first1=Matt|title=Exploring Dynamiq and ARM's New CPUs|url=http://www.anandtech.com/show/11441/dynamiq-and-arms-new-cpus-cortex-a75-a55|access-date=10 July 2017|publisher=Anandtech|date=29 May 2017}} DynamIQ is expected to allow for more flexibility and scalability when designing multi-core processors. In contrast to big.LITTLE, it increases the maximum number of cores in a cluster to 8 for Armv8.2 CPUs, 12 for Armv9 and 14 for Armv9.2{{Cite web |last=Ltd |first=Arm |title=DynamIQ – Arm® |url=https://www.arm.com/technologies/dynamiq |access-date=2023-10-18 |website=Arm {{!}} The Architecture for the Digital World |language=en}} and allows for varying core designs within a single cluster, and up to 32 total clusters. The technology also offers more fine grained per core voltage control and faster L2 cache speeds. However, DynamIQ is incompatible with previous ARM designs and is initially only supported by the Cortex-A75 and Cortex-A55 CPU cores and their successors.

{{Reflist|30em|refs=

{{cite press release | url=http://www.arm.com/about/newsroom/arm-unveils-its-most-energy-efficient-application-processor-ever-with-biglittle-processing.php | title=ARM Unveils its Most Energy Efficient Application Processor Ever; Redefines Traditional Power And Performance Relationship With big.LITTLE Processing | publisher=ARM Holdings | date=19 October 2011 | access-date=2012-10-31}}

{{cite press release | url=http://www.arm.com/about/newsroom/arm-launches-cortex-a50-series-the-worlds-most-energy-efficient-64-bit-processors.php | title=ARM Launches Cortex-A50 Series, the World's Most Energy-Efficient 64-bit Processors | publisher=ARM Holdings | access-date=2012-10-31}}

{{cite web | url=http://www.anandtech.com/show/7313/samsung-announces-biglittle-mp-support-in-exynos-5420 | title=Samsung Announces big.LITTLE MP Support in Exynos 5420 | publisher=AnandTech | date=2013-09-11 | author=Brian Klug | access-date=2013-09-16}}

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• {{cite web | url=https://lwn.net/Articles/534646/ | title=big.LITTLE MP status Jan 25, 2013 | publisher=LWN.net | date=25 January 2013 | author=David Zinman | access-date=2013-01-25}}
• {{cite web | url=https://lwn.net/Articles/481055/ | title=Linux support for ARM big.LITTLE | publisher=LWN.net | date=15 February 2012 | author=Nicolas Pitre | access-date=2012-10-18}}
• {{cite web | url=https://lwn.net/Articles/501501/ | title=A big.LITTLE scheduler update | publisher=LWN.net | date=12 June 2012 | author=Paul McKenney | access-date=2012-10-18}}
• {{cite web | url=https://lwn.net/Articles/514063/ | title=KS2012: ARM: A big.LITTLE update | publisher=LWN.net | date=5 September 2012 | author=Jake Edge | access-date=2012-10-18}}
• {{cite web | url=https://arstechnica.com/gadgets/2011/10/arms-new-cortex-a7-is-tailor-made-for-android-superphones/ | title=ARM's new Cortex A7 is tailor-made for Android superphones | publisher=Ars Technica | date=20 October 2011 | author = Jon Stokes | access-date=2012-10-31 }}
• {{cite web | url=https://arstechnica.com/information-technology/2012/10/arm-goes-64-bit-with-new-cortex-a53-and-cortex-a57-designs/ | title=ARM goes 64-bit with new Cortex-A53 and Cortex-A57 designs | publisher=Ars Technica | date=30 October 2012 | author=Andrew Cunningham | access-date=2012-10-31}}

• [https://web.archive.org/web/20121022055646/http://www.arm.com/products/processors/technologies/bigLITTLEprocessing.php big.LITTLE Processing]
• [https://web.archive.org/web/20131017064722/http://www.arm.com/files/downloads/big_LITTLE_Final_Final.pdf big.LITTLE Processing with ARM CortexTM-A15 & Cortex-A7] (PDF) (full technical explanation)

Category:ARM architecture

Category:Heterogeneous computing