CRUVI FPGA card

The CRUVI FPGA Card is a daughter card standard of Standardization Group for Embedded Technologies e.V. (SGET){{cite web|url=https://sget.org/standards/scruvi/|title=SGET Standard Development Team sCRUVI – FPGA Peripheral Module SDT.07|access-date=2025-06-17|language=en}} specifically tailored to the needs of FPGAs.

file:CRUVI Logo.png

Background

The expansion bus interface is designed to create an open ecosystem of function modules for high-performance peripheral connectivity. Its main focus is on supporting FPGA and FPGA SoC devices from all major manufacturers like Altera, Lattice, Microchip and Xilinx.

The word "CRUVI" is a combination of the Estonian word "KRUVI" for screw and the letter "C", which refers to the half of the hexagonal screw head. In this case, the "K" was replaced with "C" to emphasize the reference to the screw head.

Overview

It can be used to build high performance prototypes, for system integration and testing to build complex systems from smaller building blocks to iterate quickly and reduce cost. Create custom test systems for production functional testing.

It´s a perfect platform for your next high-performance semiconductor evaluation boards and systems.

The carrier module supplies the power supply, the input/output voltage and controls the functions of the peripheral modules.

The CRUVI open standard coexists between low speed, low pin-count like Pmod Interface devices and high-performance, high pin-count (HPC), 400 I/O FPGA Mezzanine Card (FMC) peripherals.

Three board-to-board connectors are specified: CRUVI-LS (Low Speed), CRUVI-HS (High Speed) and CRUVI-GT (Gigabit Transceiver) PCIe Gen 5.0 capable.

Bridging adapter exists to convert signals from Pmod to CRUVI-LS (CR00025), from FMC to CRUVI-HS (CR00101, CR00111) and FMC to CRUVI-GT (CR00112).

History of CRUVI specification

International contributors to define the open source CRUVI specification are Trenz Electronic GmbH, Arrow Electronics, Samtec, Flinders University, Synaptic Laboratories Ltd, Symbiotic EDA and MicroFPGA UG.

class="wikitable"

|+History of CRUVI

open source specification - FREE to use Apache License 2.0

! Year

! Version

! Notes

! Refs

2021

| 1.0.7 -alpha

| first release

2024

| 2.0.1 -alpha

| neu: CRUVI-GT (Gigabit Transceiver)

| {{cite web|url=https://github.com/micro-FPGA/CRUVI/blob/master/docs/CRUVI_Specification.pdf|title=CRUVI specification v2.0.1 (2024)|access-date=2024-05-17|language=en}}

The Standardization Group for Embedded Technologies e.V. (SGET) launches its call for participation to establish a new Standard Development Team (SDT) for the FPGA Peripheral Module standard with the working title sCRUVI. The founding meeting of the Standard Development Team (SDT.07) for FPGA Peripheral Modules was on May 6th 2025. This initiative aims to set a groundbreaking standard for peripheral modules used in FPGA and FPGA-SoC-based systems.

Structure and description of the carrier modules

Single, double or triple width modules are allowed and they have more mounting holes.

A triple size of space on carrier board is 67.72 x 57.5 mm² (2.66535 x 2.26378 inch²). There are 3 slots. The mounting holes (1 to 6) for M2 screws are 2.2 mm (0.0866 inch) diameter and need SMD spacer for mechanically fixing.

The CR99201 PCB template has LS and HS connectors named: AX, BY and CZ. The CR99500{{cite web|url=https://github.com/micro-FPGA/CRUVI/tree/master/CAD/Altium/templates|title=PCB Vorlage CRUVI peripheral Module|access-date=2024-05-17|language=en}} PCB template has LS, HS and GT connectors.

file:CR99210_triple_maximum_size_carrier_board.jpg

file:Triple_maximum_size_carrier_board_67.72_x_57.5.jpg

file:CR99500-1_triple_maximum_size_carrier_board.jpg

file:CR99500_Triple_maximum_size_carrier_board_67.72_x_57.5.jpg

It is recommended for all FPGA host boards with CRUVI slots provide LiteX platform support files.{{cite web|url=https://github.com/micro-FPGA/CRUVI/tree/master/tools/LiteX|title=LiteX platform support files for FPGA host boards with CRUVI slots|access-date=2024-05-17|language=en}}

Structure and description of the peripheral modules

There are different single peripheral module possible,

flexible and scalable by size LS, HS and GT connectors. Mounting holes are for M2 screws 2.2 mm (0.0866 inch) diameter.

CRUVI connector specification

class="wikitable" \|+ specification of connectors ! style="text-align:center;" \| ! style="text-align:center;" \| LS Low Speed ! style="text-align:center;" \| HS High Speed ! style="text-align:center;" \| GT Gigabit Transceiver
scope="row" \| Carrier side connector \| style="text-align:center;" \| CLT-106-02-F-D-A-K \| style="text-align:center;" \| SS4-30-3.50-L-D-K \| style="text-align:center;" \| ADF6-20-03.5-L-4-2
scope="row" \|3D STEP Model \| style="text-align:center;" \|100px \| style="text-align:center;" \|100px \| style="text-align:center;" \|100px
scope="row" \| Peripheral side connector \| style="text-align:center;" \| TMMH-106-04-F-DV-A-M \| style="text-align:center;" \| ST4-30-1.50-L-D-P \| style="text-align:center;" \| ADM6-20-01.5-L-4-2
scope="row" \|3D STEP Model \| style="text-align:center;" \|100px \| style="text-align:center;" \|100px \| style="text-align:center;" \|100px
scope="row" \| Pin no \| style="text-align:center;" \| 12 (6 per row) \| style="text-align:center;" \| 60 (30 per row) \| style="text-align:center;" \| 80 (20 per row)
scope="row" \| pitch [mm] / [inch] \| style="text-align:center;" \| 2 / 0.787 \| style="text-align:center;" \| 0.4 / 0.016 \| style="text-align:center;" \| 0.635 / 0.025
scope="row" \| stacked height [mm] / [inch] \| style="text-align:center;" \| 4.78 to 5.29 /0.188 to 0.208 \| colspan="2" style="text-align:center;" \| 5 / 0.197
scope="row" \| speed rating [GHz] / [Gbps] \| style="text-align:center;" \| 5.5 / 11 \| style="text-align:center;" \| 13.5 / 27 (single ended) 15.5 / 31 (differential) \| style="text-align:center;" \| 32
scope="row" \| Single ended I/O pins (VCCIO) \| style="text-align:center;" \| 8 \| style="text-align:center;" \| 37 (28 adj.) + (9 fixed 3.3V) \| style="text-align:center;" \| 8 + I2C
scope="row" \| max. differential I/O \| style="text-align:center;" \| no \| style="text-align:center;" \| max. 12 LVDS \| style="text-align:center;" \| max. 4 lanes + REFCLK
scope="row" \| Power Supply \| colspan="3" style="text-align:center;"\| adjustable, 3.3V, 5V
scope="row" \| Current rating per pin [A] \| style="text-align:center;" \| 4.1 (2-pin powered) \| style="text-align:center;" \| 1.6 (2-pin powered) \| style="text-align:center;" \| 1.34 (4-pin powered)
scope="row" \| max. Temperatur range [°C] \| colspan="3" style="text-align:center;"
55 to 125

class="wikitable"

|+ specification of connectors

! style="text-align:center;" |

! style="text-align:center;" | LS Low Speed

! style="text-align:center;" | HS High Speed

! style="text-align:center;" | GT Gigabit Transceiver

scope="row" | Carrier side connector

| style="text-align:center;" | CLT-106-02-F-D-A-K

| style="text-align:center;" | SS4-30-3.50-L-D-K

| style="text-align:center;" | ADF6-20-03.5-L-4-2

scope="row" |3D STEP Model

| style="text-align:center;" |100px

scope="row" | Peripheral side connector

| style="text-align:center;" | TMMH-106-04-F-DV-A-M

| style="text-align:center;" | ST4-30-1.50-L-D-P

| style="text-align:center;" | ADM6-20-01.5-L-4-2

scope="row" |3D STEP Model

| style="text-align:center;" |100px

scope="row" | Pin no

| style="text-align:center;" | 12 (6 per row)

| style="text-align:center;" | 60 (30 per row)

| style="text-align:center;" | 80 (20 per row)

scope="row" | pitch [mm] / [inch]

| style="text-align:center;" | 2 / 0.787

| style="text-align:center;" | 0.4 / 0.016

| style="text-align:center;" | 0.635 / 0.025

scope="row" | stacked height [mm] / [inch]

| style="text-align:center;" | 4.78 to 5.29 /0.188 to 0.208

| colspan="2" style="text-align:center;" | 5 / 0.197

scope="row" | speed rating [GHz] / [Gbps]

| style="text-align:center;" | 5.5 / 11

| style="text-align:center;" | 13.5 / 27 (single ended)

15.5 / 31 (differential)

| style="text-align:center;" | 32

scope="row" | Single ended I/O pins (VCCIO)

| style="text-align:center;" | 8

| style="text-align:center;" | 37 (28 adj.) + (9 fixed 3.3V)

| style="text-align:center;" | 8 + I2C

scope="row" | max. differential I/O

| style="text-align:center;" | no

| style="text-align:center;" | max. 12 LVDS

| style="text-align:center;" | max. 4 lanes + REFCLK

scope="row" | Power Supply

| colspan="3" style="text-align:center;"| adjustable, 3.3V, 5V

scope="row" | Current rating per pin [A]

| style="text-align:center;" | 4.1 (2-pin powered)

| style="text-align:center;" | 1.6 (2-pin powered)

| style="text-align:center;" | 1.34 (4-pin powered)

scope="row" | max. Temperatur range [°C]

| colspan="3" style="text-align:center;"

55 to 125

peripheral board specification

There are different single peripheral module possible,

flexible and scalable by size LS, HS and GT connectors. Mounting holes are for M2 screws

2.2 mm (0.0866 inch) diameter.

It is recommended to have EEPROM with I2C for identification of peripheral module with a specific address number.

class="wikitable" \|+ CRUVI peripheral boards !style="width:20%"\| L x H [mm²] / [inch²] !style="width:10%"\| speed !style="width:20%"\| PCB template {{cite web\|url=https://github.com/micro-FPGA/CRUVI/tree/master/CAD/Altium/templates\|title=PCB template CRUVI peripheral boards\|access-date=2023-12-19\|language=en}} !style="width:50%"\| Note
scope="row" \| 14 x 14 / 0.55 x 0.55 !scope="row" \| LS !scope="row" \| CR99001 \|style="text-align:center;" \| File:CR99001 CR99002 14 x 14 LS.jpg identification EEPROM is included; This template is usefull for I2C, I3C, SPI sensor, I2S PDM MEMS microphones, programmable oscillator, ADC, DAC or SPI (QSPI) Flash memory device in BGA24 or SO-8 package.
scope="row" \| 14 x 14 / 0.55 x 0.55 !scope="row" \| LS !scope="row" \| CR99002 \| style="text-align:center;" \| same as CR99001 with added u.Fl connectors for I/O
scope="row" \| 22 x 32 / 0.87 x 1.2598 !scope="row" \| LS !scope="row" \| CR99003 \| style="text-align:center;" \| File:CR99003 22 x 32 LS.jpg maximum size one-wide half-length, identification EEPROM is included
scope="row" \| 18 x 32 / 0.71 x 1.26 !scope="row" \| LS !scope="row" \| CR99004 \| style="text-align:center;" \| File:CR99004 18 x 32 LS.jpg This template is usefull to convert into Pmod compatible connector (CR00005).
scope="row" \| 22 x 30 / 0.87 x 1.18 !scope="row" \| LS !scope="row" \| CR99005 \| style="text-align:center;" \| File:CR99005 22 x 30 LS.jpg is half-length LS module with two SMA connectors
scope="row" \| 18 x 20 / 0.71 x 0.79 !scope="row" \| HS !scope="row" \| CR99101 \| style="text-align:center;" \| File:CR99101 18 x 20 HS.jpg minimal size HS Module; good for HyperRAM or HyperFlash (CR00041), eMMC (CR00049) or loopback adapter for CRUVI-HS (CR00091)
scope="row" \| 22 x 57.5 / 0.87 x 2.26 !scope="row" \| HS !scope="row" \| CR99102 \| style="text-align:center;" \| File:CR99102 22 x 57.5 HS.jpg maximum sized single-width HS module; good for signal test adapter to probed with scope or logic analyzer (CR00026), for high speed interfaces like USB-C, HDMI (CR00240), MIPI CSI/DSI, SDIO, xGMII Ethernet (CR0020x) and LVDS ADC (1 to 4 data lane)
scope="row" \| !scope="row" \| GT !scope="row" \| CR99103 \| style="text-align:center;" \| comming soon, good for HDMI output (CR00240), JESD204B ADC (CR00401), loopback adapter for CRUVI-GT (CR00092)

class="wikitable"

|+ CRUVI peripheral boards

!style="width:20%"| L x H [mm²] / [inch²]

!style="width:10%"| speed

!style="width:20%"| PCB template {{cite web|url=https://github.com/micro-FPGA/CRUVI/tree/master/CAD/Altium/templates|title=PCB template CRUVI peripheral boards|access-date=2023-12-19|language=en}}

!style="width:50%"| Note

scope="row" | 14 x 14 / 0.55 x 0.55

!scope="row" | LS

!scope="row" | CR99001

|style="text-align:center;" | File:CR99001 CR99002 14 x 14 LS.jpg

identification EEPROM is included; This template is usefull for I2C, I3C, SPI sensor, I2S PDM MEMS microphones, programmable oscillator, ADC, DAC or

SPI (QSPI) Flash memory device in BGA24 or SO-8 package.

scope="row" | 14 x 14 / 0.55 x 0.55

!scope="row" | LS

!scope="row" | CR99002

| style="text-align:center;" | same as CR99001 with added u.Fl connectors for I/O

scope="row" | 22 x 32 / 0.87 x 1.2598

!scope="row" | LS

!scope="row" | CR99003

| style="text-align:center;" | File:CR99003 22 x 32 LS.jpg

maximum size one-wide half-length, identification EEPROM is included

scope="row" | 18 x 32 / 0.71 x 1.26

!scope="row" | LS

!scope="row" | CR99004

| style="text-align:center;" | File:CR99004 18 x 32 LS.jpg

This template is usefull to convert into Pmod compatible connector (CR00005).

scope="row" | 22 x 30 / 0.87 x 1.18

!scope="row" | LS

!scope="row" | CR99005

| style="text-align:center;" | File:CR99005 22 x 30 LS.jpg

is half-length LS module with two SMA connectors

scope="row" | 18 x 20 / 0.71 x 0.79

!scope="row" | HS

!scope="row" | CR99101

| style="text-align:center;" | File:CR99101 18 x 20 HS.jpg

minimal size HS Module; good for HyperRAM or HyperFlash (CR00041), eMMC (CR00049) or loopback adapter for CRUVI-HS (CR00091)

scope="row" | 22 x 57.5 / 0.87 x 2.26

!scope="row" | HS

!scope="row" | CR99102

| style="text-align:center;" | File:CR99102 22 x 57.5 HS.jpg

maximum sized single-width HS module; good for signal test adapter to probed with scope or logic analyzer (CR00026), for high speed interfaces like USB-C, HDMI (CR00240), MIPI CSI/DSI, SDIO, xGMII Ethernet (CR0020x) and LVDS ADC (1 to 4 data lane)

scope="row" |

!scope="row" | GT

!scope="row" | CR99103

| style="text-align:center;" |

comming soon, good for HDMI output (CR00240), JESD204B ADC (CR00401), loopback adapter for CRUVI-GT (CR00092)

LS Low Speed, HS High Speed and GT Gigabit Transceiver connector

class="wikitable" \|+ CRUVI connector specification ! style="text-align:center;" \| Connector ! style="text-align:center;" \| LS Low Speed ! style="text-align:center;" \| HS High Speed ! style="text-align:center;" \| GT Gigabit Transceiver
scope="row" \| Carrier side connector \| style="text-align:center;" \| CLT-106-02-F-D-A-K \| style="text-align:center;" \| SS4-30-3.50-L-D-K \| style="text-align:center;" \| ADF6-20-03.5-L-4-2
scope="row" \|3D STEP Model \| style="text-align:center;" \|file:CLT-106-02-F-D-A-K_3D_Model_STEP.jpg \| style="text-align:center;" \|file:SS4-30-3.50-L-D-K_3D_Model_STEP.jpg \| style="text-align:center;" \|file:ADF6-20-03.5-L-4-2_3D_Model_STEP.jpg
scope="row" \| Peripheral side connector \| style="text-align:center;" \| TMMH-106-04-F-DV-A-M \| style="text-align:center;" \| ST4-30-1.50-L-D-P \| style="text-align:center;" \| ADM6-20-01.5-L-4-2
scope="row" \|3D STEP Model \| style="text-align:center;" \|file:TMMH-106-04-F-DV-A-M_3D_Model_STEP.jpg \| style="text-align:center;" \|file:ST4-30-1.50-L-D-P_3D_Model_STEP.jpg \| style="text-align:center;" \|file:ADM6-20-01.5-L-4-2_3D_Model_STEP.jpg
scope="row" \| Pin no \| style="text-align:center;" \| 12 (6 per row) \| style="text-align:center;" \| 60 (30 per row) \| style="text-align:center;" \| 80 (20 per row)
scope="row" \| pitch [mm] / [inch] \| style="text-align:center;" \| 2 / 0.787 \| style="text-align:center;" \| 0.4 / 0.016 \| style="text-align:center;" \| 0.635 / 0.025
scope="row" \| stacked height [mm] / [inch] \| style="text-align:center;" \| 4.78 to 5.29 /0.188 to 0.208 \| colspan="2" style="text-align:center;" \| 5 / 0.197
scope="row" \| speed rating [GHz] / [Gbps] \| style="text-align:center;" \| 5.5 / 11 \| style="text-align:center;" \| 13.5 / 27 (single ended) 15.5 / 31 (differential) \| style="text-align:center;" \| 32
scope="row" \| Single ended I/O pins (VCCIO) \| style="text-align:center;" \| 8 \| style="text-align:center;" \| 37 (28 adj.) + (9 fixed 3.3V) \| style="text-align:center;" \| 8 + I2C
scope="row" \| max. differential I/O \| style="text-align:center;" \| no \| style="text-align:center;" \| max. 12 LVDS \| style="text-align:center;" \| max. 4 lanes + REFCLK
scope="row" \| Power Supply \| colspan="3" style="text-align:center;"\| adj., 3.3V, 5V
scope="row" \| Current rating per pin [A] \| style="text-align:center;" \| 4.1 (2-pin powered) \| style="text-align:center;" \| 1.6 (2-pin powered) \| style="text-align:center;" \| 1.34 (4-pin powered)
scope="row" \| max. Temperatur range [°C] \| colspan="3" style="text-align:center;"
55 to 125

class="wikitable"

|+ CRUVI connector specification

! style="text-align:center;" | Connector

! style="text-align:center;" | LS Low Speed

! style="text-align:center;" | HS High Speed

! style="text-align:center;" | GT Gigabit Transceiver

scope="row" | Carrier side connector

| style="text-align:center;" | CLT-106-02-F-D-A-K

| style="text-align:center;" | SS4-30-3.50-L-D-K

| style="text-align:center;" | ADF6-20-03.5-L-4-2

scope="row" |3D STEP Model

| style="text-align:center;" |file:CLT-106-02-F-D-A-K_3D_Model_STEP.jpg

| style="text-align:center;" |file:SS4-30-3.50-L-D-K_3D_Model_STEP.jpg

| style="text-align:center;" |file:ADF6-20-03.5-L-4-2_3D_Model_STEP.jpg

scope="row" | Peripheral side connector

| style="text-align:center;" | TMMH-106-04-F-DV-A-M

| style="text-align:center;" | ST4-30-1.50-L-D-P

| style="text-align:center;" | ADM6-20-01.5-L-4-2

scope="row" |3D STEP Model

| style="text-align:center;" |file:TMMH-106-04-F-DV-A-M_3D_Model_STEP.jpg

| style="text-align:center;" |file:ST4-30-1.50-L-D-P_3D_Model_STEP.jpg

| style="text-align:center;" |file:ADM6-20-01.5-L-4-2_3D_Model_STEP.jpg

scope="row" | Pin no

| style="text-align:center;" | 12 (6 per row)

| style="text-align:center;" | 60 (30 per row)

| style="text-align:center;" | 80 (20 per row)

scope="row" | pitch [mm] / [inch]

| style="text-align:center;" | 2 / 0.787

| style="text-align:center;" | 0.4 / 0.016

| style="text-align:center;" | 0.635 / 0.025

scope="row" | stacked height [mm] / [inch]

| style="text-align:center;" | 4.78 to 5.29 /0.188 to 0.208

| colspan="2" style="text-align:center;" | 5 / 0.197

scope="row" | speed rating [GHz] / [Gbps]

| style="text-align:center;" | 5.5 / 11

| style="text-align:center;" | 13.5 / 27 (single ended)

15.5 / 31 (differential)

| style="text-align:center;" | 32

scope="row" | Single ended I/O pins (VCCIO)

| style="text-align:center;" | 8

| style="text-align:center;" | 37 (28 adj.) + (9 fixed 3.3V)

| style="text-align:center;" | 8 + I2C

scope="row" | max. differential I/O

| style="text-align:center;" | no

| style="text-align:center;" | max. 12 LVDS

| style="text-align:center;" | max. 4 lanes + REFCLK

scope="row" | Power Supply

| colspan="3" style="text-align:center;"| adj., 3.3V, 5V

scope="row" | Current rating per pin [A]

| style="text-align:center;" | 4.1 (2-pin powered)

| style="text-align:center;" | 1.6 (2-pin powered)

| style="text-align:center;" | 1.34 (4-pin powered)

scope="row" | max. Temperatur range [°C]

| colspan="3" style="text-align:center;"

55 to 125

CRUVI-LS pinout and signal description

class="wikitable" \|+ CRUVI-LS pinout and signal description ! Pin ! Primary ! Signal ! Pin ! Primary ! Signal
scope="row" \| 1 \| SDA \| I2C(SDA), SMBUS(SDA) ! scope="row" \| 7 \| D1 \| UART(RXD1), SD(D1), SPI(MISO), QSPI(D1), JTAG(TDI)
scope="row" \| 2 \| SCL \| I2C(SCL), SMBUS(SCL) ! scope="row" \| 8 \| CLK \| UART(RTS), SD(CLK), SPI(CLK), QSPI(CLK), JTAG(TCK)
scope="row" \| 3 \| D3 \| UART(RST), SD(TXD0), QSPI(D3), JTAG(nRST) ! scope="row" \| 9 \| D0 \| UART(TXD1), SD(D0), SPI(MOSI), QSPI(D0) JTAG(TDO)
scope="row" \| 4 \| SEL \| UART(CTS), SD(CMD), SPI(SEL), QSPI(SEL), JTAG(TMS) ! scope="row" \| 10 \| VCC \| Power 3.3V
scope="row" \| 5 \| D2 \| SMBUS(INT), UART(RXD0), SD(D2), QSPI(D2), JTAG(RFU) ! scope="row" \| 11 \| RFU \| tbd
scope="row" ! scope="row" \| 6 \| GND \| Ground ! scope="row" \| 12 \| VBUS \| Power 5V

class="wikitable"

|+ CRUVI-LS pinout and signal description

! Pin

! Primary

! Signal

! Pin

! Primary

! Signal

scope="row" | 1

| SDA

| I2C(SDA), SMBUS(SDA)

! scope="row" | 7

| D1

| UART(RXD1), SD(D1), SPI(MISO), QSPI(D1), JTAG(TDI)

scope="row" | 2

| SCL

| I2C(SCL), SMBUS(SCL)

! scope="row" | 8

| CLK

| UART(RTS), SD(CLK), SPI(CLK), QSPI(CLK), JTAG(TCK)

scope="row" | 3

| D3

| UART(RST), SD(TXD0), QSPI(D3), JTAG(nRST)

! scope="row" | 9

| D0

| UART(TXD1), SD(D0), SPI(MOSI), QSPI(D0) JTAG(TDO)

scope="row" | 4

| SEL

| UART(CTS), SD(CMD), SPI(SEL), QSPI(SEL), JTAG(TMS)

! scope="row" | 10

| VCC

| Power 3.3V

scope="row" | 5

| D2

| SMBUS(INT), UART(RXD0), SD(D2), QSPI(D2), JTAG(RFU)

! scope="row" | 11

| RFU

| tbd

scope="row" ! scope="row" | 6

| GND

| Ground

! scope="row" | 12

| VBUS

| Power 5V

CRUVI-HS pinout and signal description

class="wikitable" \|+ CRUVI-HS signal description ! Pin ! Primary Function ! Note ! Pin ! Primary Function ! Note ! Pin ! Primary Function ! Note ! Pin ! Primary Function ! Note
scope="row" \| 1 \| RFU1 \| ! scope="row" \| 16 \| A0_N \| Transceiver I/O ! scope="row" \| 31 \| GND \| Ground ! scope="row" \| 46 \| A5_N \| Transceiver I/O
scope="row" \| 2 \| HSIO \| ! scope="row" \| 17 \| B0_N \| Transceiver I/O ! scope="row" \| 32 \| A3_P \| ! scope="row" \| 47 \| B5_N \| Transceiver I/O
scope="row" \| 3 \| ALERT/IRQ \| ! scope="row" \| 18 \| GND \| Ground ! scope="row" \| 33 \| B3_P \| Transceiver I/O ! scope="row" \| 48 \| GND \| Ground
scope="row" \| 4 \| VCC \| 3,3V ! scope="row" \| 19 \| GND \| Ground ! scope="row" \| 34 \| A3_N \| ! scope="row" \| 49 \| GND \| Ground
scope="row" \| 5 \| SDA \| ! scope="row" \| 20 \| A1_P \| Transceiver I/O ! scope="row" \| 35 \| B3_N \| Transceiver I/O ! scope="row" \| 50 \| RFU2_P \|
scope="row" \| 6 \| HSO \| ! scope="row" \| 21 \| B1_P \| Transceiver I/O ! scope="row" \| 36 \| VADJ \| 1.2 to 3.3V ! scope="row" \| 51 \| DI/TDI \| JTAG, SPI(MISO)
scope="row" \| 7 \| SCL \| ! scope="row" \| 22 \| A1_N \| Transceiver I/O ! scope="row" \| 37 \| GND \| Ground ! scope="row" \| 52 \| RFU2_N \|
scope="row" \| 8 \| HSRST \| ! scope="row" \| 23 \| B1_N \| Transceiver I/O ! scope="row" \| 38 \| A4_P \| Transceiver I/O ! scope="row" \| 53 \| DO/TDO \| JTAG, SPI(MOSI)
scope="row" \| 9 \| VCC \| 3.3V ! scope="row" \| 24 \| GND \| Ground ! scope="row" \| 39 \| B4_P \| Transceiver I/O ! scope="row" \| 54 \| GND \| Ground
scope="row" \| 10 \| HSI \| ! scope="row" \| 25 \| GND \| Ground ! scope="row" \| 40 \| A4_N \| Transceiver I/O ! scope="row" \| 55 \| SEL/TMS \| JTAG, SPI(SEL)
scope="row" \| 11 \| REFCLK \| ! scope="row" \| 26 \| A2_P \| ! scope="row" \| 41 \| B4_N \| Transceiver I/O ! scope="row" \| 56 \| RFU_P \|
scope="row" \| 12 \| GND \| Ground ! scope="row" \| 27 \| B2_P \| Transceiver I/O ! scope="row" \| 42 \| GND \| Ground ! scope="row" \| 57 \| MODE \| JTAG EN
scope="row" \| 13 \| GND \| Ground ! scope="row" \| 28 \| A2_N \| ! scope="row" \| 43 \| GND \| Ground ! scope="row" \| 58 \| RFU_N \|
scope="row" \| 14 \| A0_P \| Transceiver I/O ! scope="row" \| 29 \| B2_N \| Transceiver I/O ! scope="row" \| 44 \| A5_P \| Transceiver I/O ! scope="row" \| 59 \| SCK/TCK \| JTAG, SPI(CLK)
scope="row" \| 15 \| B0_P \| Transceiver I/O ! scope="row" \| 30 \| GND \| Ground ! scope="row" \| 45 \| B5_P \| Transceiver I/O ! scope="row" \| 60 \| VBUS \| 5V

class="wikitable"

|+ CRUVI-HS signal description

! Pin

! Primary Function

! Note

! Pin

! Primary Function

! Note

! Pin

! Primary Function

! Note

! Pin

! Primary Function

! Note

scope="row" | 1

| RFU1

! scope="row" | 16

| A0_N

| Transceiver I/O

! scope="row" | 31

| GND

| Ground

! scope="row" | 46

| A5_N

| Transceiver I/O

scope="row" | 2

| HSIO

! scope="row" | 17

| B0_N

| Transceiver I/O

! scope="row" | 32

| A3_P

! scope="row" | 47

| B5_N

| Transceiver I/O

scope="row" | 3

| ALERT/IRQ

! scope="row" | 18

| GND

| Ground

! scope="row" | 33

| B3_P

| Transceiver I/O

! scope="row" | 48

| GND

| Ground

scope="row" | 4

| VCC

| 3,3V

! scope="row" | 19

| GND

| Ground

! scope="row" | 34

| A3_N

! scope="row" | 49

| GND

| Ground

scope="row" | 5

| SDA

! scope="row" | 20

| A1_P

| Transceiver I/O

! scope="row" | 35

| B3_N

| Transceiver I/O

! scope="row" | 50

| RFU2_P

scope="row" | 6

| HSO

! scope="row" | 21

| B1_P

| Transceiver I/O

! scope="row" | 36

| VADJ

| 1.2 to 3.3V

! scope="row" | 51

| DI/TDI

| JTAG, SPI(MISO)

scope="row" | 7

| SCL

! scope="row" | 22

| A1_N

| Transceiver I/O

! scope="row" | 37

| GND

| Ground

! scope="row" | 52

| RFU2_N

scope="row" | 8

| HSRST

! scope="row" | 23

| B1_N

| Transceiver I/O

! scope="row" | 38

| A4_P

| Transceiver I/O

! scope="row" | 53

| DO/TDO

| JTAG, SPI(MOSI)

scope="row" | 9

| VCC

| 3.3V

! scope="row" | 24

| GND

| Ground

! scope="row" | 39

| B4_P

| Transceiver I/O

! scope="row" | 54

| GND

| Ground

scope="row" | 10

| HSI

! scope="row" | 25

| GND

| Ground

! scope="row" | 40

| A4_N

| Transceiver I/O

! scope="row" | 55

| SEL/TMS

| JTAG, SPI(SEL)

scope="row" | 11

| REFCLK

! scope="row" | 26

| A2_P

! scope="row" | 41

| B4_N

| Transceiver I/O

! scope="row" | 56

| RFU_P

scope="row" | 12

| GND

| Ground

! scope="row" | 27

| B2_P

| Transceiver I/O

! scope="row" | 42

| GND

| Ground

! scope="row" | 57

| MODE

| JTAG EN

scope="row" | 13

| GND

| Ground

! scope="row" | 28

| A2_N

! scope="row" | 43

| GND

| Ground

! scope="row" | 58

| RFU_N

scope="row" | 14

| A0_P

| Transceiver I/O

! scope="row" | 29

| B2_N

| Transceiver I/O

! scope="row" | 44

| A5_P

| Transceiver I/O

! scope="row" | 59

| SCK/TCK

| JTAG, SPI(CLK)

scope="row" | 15

| B0_P

| Transceiver I/O

! scope="row" | 30

| GND

| Ground

! scope="row" | 45

| B5_P

| Transceiver I/O

! scope="row" | 60

| VBUS

| 5V

CRUVI-GT pinout and signal description

class="wikitable" \|+ CRUVI-GT Gigabit Transceiver pinout and signal description ! style="width:5em;"\| Pin ! style="width:10em;"\| Primary Function ! style="width:10em;"\| Note ! style="width:5em;"\| Pin ! style="width:10em;"\| Primary Function ! style="width:10em;"\| Note ! style="width:5em;"\| Pin ! style="width:10em;"\| Primary Function ! style="width:10em;"\| Note ! style="width:5em;"\| Pin ! style="width:10em;"\| Primary Function ! style="width:10em;"\| Note
scope="row" \| A1 \| GND \| Ground ! scope="row" \| B1 \| TCK \| JTAG ! scope="row" \| C1 \| TDI \| JTAG ! scope="row" \| D1 \| GND \| Ground
scope="row" \| A2 \| TX3_N \| ! scope="row" \| B2 \| TMS \| JTAG ! scope="row" \| C2 \| TDO \| JTAG ! scope="row" \| D2 \| RX3_N \|
scope="row" \| A3 \| TX3_P \| ! scope="row" \| B3 \| \| ! scope="row" \| C3 \| \| ! scope="row" \| D3 \| RX3_P \|
scope="row" \| A4 \| GND \| Ground ! scope="row" \| B4 \| \| ! scope="row" \| C4 \| \| ! scope="row" \| D4 \| GND \| Ground
scope="row" \| A5 \| TX2_N \| ! scope="row" \| B5 \| \| ! scope="row" \| C5 \| \| ! scope="row" \| D5 \| RX2_N \|
scope="row" \| A6 \| TX2_P \| ! scope="row" \| B6 \| \| ! scope="row" \| C6 \| D1_N \| ! scope="row" \| D6 \| RX2_P \|
scope="row" \| A7 \| GND \| Ground ! scope="row" \| B7 \| \| ! scope="row" \| C7 \| D1_P \| ! scope="row" \| D7 \| GND \| Ground
scope="row" \| A8 \| \| ! scope="row" \| B8 \| \| ! scope="row" \| C8 \| \| ! scope="row" \| D8 \| CLK0_N \| CLK
scope="row" \| A9 \| \| ! scope="row" \| B9 \| \| ! scope="row" \| C9 \| \| ! scope="row" \| D9 \| CLK0_P \| CLK
scope="row" \| A10 \| \| ! scope="row" \| B10 \| VADJ \| 1.2 to 3.3V ! scope="row" \| C10 \| VCC_5V \| 5V ! scope="row" \| D10 \| GND \| Ground
scope="row" \| A11 \| \| ! scope="row" \| B11 \| VCC_3.3V \| 3.3V ! scope="row" \| C11 \| VCC_12V \| 12V ! scope="row" \| D11 \| GND \| Ground
scope="row" \| A12 \| \| ! scope="row" \| B12 \| \| ! scope="row" \| C12 \| \| ! scope="row" \| D12 \| GBTCLK0_N \| CLK
scope="row" \| A13 \| \| ! scope="row" \| B13 \| \| ! scope="row" \| C13 \| \| ! scope="row" \| D13 \| GBTCLK0_P \| CLK
scope="row" \| A14 \| GND \| Ground ! scope="row" \| B14 \| \| ! scope="row" \| C14 \| D0_N \| ! scope="row" \| D14 \| GND \| Ground
scope="row" \| A15 \| TX1_N \| ! scope="row" \| B15 \| \| ! scope="row" \| C15 \| D0_P \| ! scope="row" \| D15 \| RX1_N \|
scope="row" \| A16 \| TX1_P \| ! scope="row" \| B16 \| S4_LS \| AUX IO ! scope="row" \| C16 \| S7_LS \| AUX IO ! scope="row" \| D16 \| RX1_P \|
scope="row" \| A17 \| GND \| Ground ! scope="row" \| B17 \| S5_LS \| AUX IO ! scope="row" \| C17 \| S6_LS \| AUX IO ! scope="row" \| D17 \| GND \| Ground
scope="row" \| A18 \| TX0_N \| ! scope="row" \| B18 \| S0_LS \| AUX IO ! scope="row" \| C18 \| S3_LS \| AUX IO ! scope="row" \| D18 \| RX0_N \|
scope="row" \| A19 \| TX0_P \| ! scope="row" \| B19 \| S1_LS \| AUX IO ! scope="row" \| C19 \| S2_LS \| AUX IO ! scope="row" \| D19 \| RX0_P \|
scope="row" \| A20 \| GND \| Ground ! scope="row" \| B20 \| SDA_LS \| SMBus ! scope="row" \| C20 \| SCL_LS \| SMBUs ! scope="row" \| D20 \| GND \| Ground

class="wikitable"

|+ CRUVI-GT Gigabit Transceiver pinout and signal description

! style="width:5em;"| Pin

! style="width:10em;"| Primary Function

! style="width:10em;"| Note

! style="width:5em;"| Pin

! style="width:10em;"| Primary Function

! style="width:10em;"| Note

! style="width:5em;"| Pin

! style="width:10em;"| Primary Function

! style="width:10em;"| Note

! style="width:5em;"| Pin

! style="width:10em;"| Primary Function

! style="width:10em;"| Note

scope="row" | A1

| GND

| Ground

! scope="row" | B1

| TCK

| JTAG

! scope="row" | C1

| TDI

| JTAG

! scope="row" | D1

| GND

| Ground

scope="row" | A2

| TX3_N

! scope="row" | B2

| TMS

| JTAG

! scope="row" | C2

| TDO

| JTAG

! scope="row" | D2

| RX3_N

scope="row" | A3

| TX3_P

! scope="row" | B3

! scope="row" | C3

! scope="row" | D3

| RX3_P

scope="row" | A4

| GND

| Ground

! scope="row" | B4

! scope="row" | C4

! scope="row" | D4

| GND

| Ground

scope="row" | A5

| TX2_N

! scope="row" | B5

! scope="row" | C5

! scope="row" | D5

| RX2_N

scope="row" | A6

| TX2_P

! scope="row" | B6

! scope="row" | C6

| D1_N

! scope="row" | D6

| RX2_P

scope="row" | A7

| GND

| Ground

! scope="row" | B7

! scope="row" | C7

| D1_P

! scope="row" | D7

| GND

| Ground

scope="row" | A8

! scope="row" | B8

! scope="row" | C8

! scope="row" | D8

| CLK0_N

| CLK

scope="row" | A9

! scope="row" | B9

! scope="row" | C9

! scope="row" | D9

| CLK0_P

| CLK

scope="row" | A10

! scope="row" | B10

| VADJ

| 1.2 to 3.3V

! scope="row" | C10

| VCC_5V

| 5V

! scope="row" | D10

| GND

| Ground

scope="row" | A11

! scope="row" | B11

| VCC_3.3V

| 3.3V

! scope="row" | C11

| VCC_12V

| 12V

! scope="row" | D11

| GND

| Ground

scope="row" | A12

! scope="row" | B12

! scope="row" | C12

! scope="row" | D12

| GBTCLK0_N

| CLK

scope="row" | A13

! scope="row" | B13

! scope="row" | C13

! scope="row" | D13

| GBTCLK0_P

| CLK

scope="row" | A14

| GND

| Ground

! scope="row" | B14

! scope="row" | C14

| D0_N

! scope="row" | D14

| GND

| Ground

scope="row" | A15

| TX1_N

! scope="row" | B15

! scope="row" | C15

| D0_P

! scope="row" | D15

| RX1_N

scope="row" | A16

| TX1_P

! scope="row" | B16

| S4_LS

| AUX IO

! scope="row" | C16

| S7_LS

| AUX IO

! scope="row" | D16

| RX1_P

scope="row" | A17

| GND

| Ground

! scope="row" | B17

| S5_LS

| AUX IO

! scope="row" | C17

| S6_LS

| AUX IO

! scope="row" | D17

| GND

| Ground

scope="row" | A18

| TX0_N

! scope="row" | B18

| S0_LS

| AUX IO

! scope="row" | C18

| S3_LS

| AUX IO

! scope="row" | D18

| RX0_N

scope="row" | A19

| TX0_P

! scope="row" | B19

| S1_LS

| AUX IO

! scope="row" | C19

| S2_LS

| AUX IO

! scope="row" | D19

| RX0_P

scope="row" | A20

| GND

| Ground

! scope="row" | B20

| SDA_LS

| SMBus

! scope="row" | C20

| SCL_LS

| SMBUs

! scope="row" | D20

| GND

| Ground

References

External links

[http://www.cruvi.com/ CRUVI Webpage]
[https://cruvi.readthedocs.io/en/latest/index.html CRUVI Modules and Carriers]
[https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/CRUVI Trenz Electronic develops and manufactures CRUVI + FPGA (SoC) modules for business and science]
[https://blog.samtec.com/post/samtec-and-arrow-partner-on-new-intel-agilex-5-e-series-soc-dev-kit/ Trenz Electronic and their partners created a new FPGA expansion bus called CRUVI] published 2023-05-11
[https://www.eejournal.com/article/arrow-reveals-first-dev-board-for-intel-agilex-5-fpgas-with-two-more-boards-planned/ Arrow reveals first Dev Board for Intel Agilex 5 FPGAs, with two more boards planned] published 2023-11-27
[https://vhdplus.com/docs/components/overview/ Software is integrated into VHDPlus IDE for CRUVI solutions]
[https://synaptic-labs.com/hw-trenz/ Synaptic Laboratories Ltd (SLL) is contributor to the exciting open source CRUVI standard for memory controller and related technologies. i.e. HyperBus, OctaBus, Xccela Bus and JEDEC xSPI memory]

Category:Field-programmable gate arrays

Category:Computer hardware standards