Libre-SOC

Libre-SOC began its life when Luke Leighton wanted there to be a completely free and libre system on a chip offering. He initially opted for a RISC-V base, but later switched to OpenPOWER when that seemed like a better fit for the project.[https://www.phoronix.com/scan.php?page=news_item&px=Libre-RISC-V-Performance-Target The Libre RISC-V Vulkan Accelerator Will Be Targeting 25 FPS @ 720p, 5~6 GFLOPs][https://www.phoronix.com/scan.php?page=news_item&px=LibreSOC-2021 LibreSOC Still Striving To Produce An Open-Source Hybrid CPU/GPU Built On OpenPOWER] It is the second processor written from scratch using the OpenPOWER ISA 3.0, and the first libre core that is completely independent of IBM.

The project is mostly funded through NLnet grants.[https://nlnet.nl/project/Libre-RISCV/ The Libre-RISCV SoC][https://www.crowdsupply.com/libre-risc-v/m-class/updates/nlnet-grants-approved-power-isa-under-consideration NLNet Grants approved, Power ISA under consideration]

While being developed as a "soft core" Libre-SOC will be fabricated in 180 nm by TSMC's "Open MPW Shuttle Program" through IMEC in 2021.[https://libre-soc.org/180nm_Oct2020/ Libre-SOC 180nm ASIC plan] The finished ASIC was sent to IMEC in July 2021.{{cite web|url=https://openpowerfoundation.org/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/|title=Libre-SOC 180nm Power ISA ASIC Submitted to Imec for Fabrication|website=openpowerfoundation.org|access-date=26 July 2023|archive-date=8 July 2021|archive-url=https://web.archive.org/web/20210708133851/https://openpowerfoundation.org/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/|url-status=dead}}

Libre-SOC is a 64-bit bi-endian scalar processor core, implementing a subset of the Power ISA 3.0 instruction set. It has 32× 64-bit general purpose registers. It uses Wishbone for the memory interface.

The Libre-SOC core will be a hybrid design, based around a precise-augmented version of the historic CDC 6600 microarchitecture,[https://libre-soc.org/3d_gpu/architecture/6600scoreboard/ 6600 scoreboard architecture] merging traditional general purpose, vector and graphics computing into a single execution unit reducing complexity and size of the complete chip as well as simplifying 3D driver development.[https://youtube.com/watch?v=FxFPFsT1wDw&t=12138 XDC2020 Libre-SOC talk] This constitutes the need to add a small addition to the OpenPOWER instruction set architecture called "Simple-V".[https://libre-soc.org/openpower/sv/ Simple-V Vectorisation for the OpenPOWER ISA][https://fosdem.org/2021/schedule/event/the_libresoc_project_simple_v_vectorisation/ The LibreSOC Project: Simple-V Vectorisation. Why we decided to invent a new Vector system on top of OpenPOWER]

SVP64, currently in draft,[http://libre-soc.org/openpower/sv/svp64 SVP64 Draft Specification] extends OpenPOWER register files to 128, including CR fields, in order to cope with modern 3D and Video workloads, effectively making Libre-SOC a Vector processor.

Like Microwatt, the initial development was done in around three months, included the entire integer processing functionality of the instruction set; the bare minimum to make it compliant, with no memory management unit and no floating-point unit. Libre-SOC's rapid development is, like Microwatt, down to the significant use of software engineering practices including thousands of unit tests[https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/test;hb=HEAD OpenPOWER ISA unit tests] and by Microwatt source code as a reference design.

Libre-SOC is unusual in that it is designed using [https://gitlab.com/nmigen nMigen], a Python-based hardware description language (HDL). Also, to retain full transparency associated with "libre", the ASIC layout[https://git.libre-soc.org/?p=soclayout.git;a=summary Libre-SOC git repository for GDS-II layout] is performed with [http://coriolis.lip6.fr/ coriolis2], a VLSI toolchain developed and maintained by Sorbonne University's Laboratoire d'Informatique de Paris 6.

• OpenPOWER Foundation
• IBM Power microprocessors
• List of open-source computing hardware

{{Reflist}}

• [https://libre-soc.org Libre-SOC's official page]
• [https://git.libre-soc.org Libre-SOC source code]
• [https://openpowerfoundation.org/cores-and-more/ OpenPOWER list of Libre/Open implementations of the POWER ISA]
• [https://libre-soc.org/3d_gpu/articles/ Articles about Libre-SOC]

{{Programmable Logic}}

{{Soft microprocessors}}

Category:Open microprocessors

Libre-SOC

Category:Soft microprocessors

Libre-SOC