Nios V
{{Short description|Processor architecture}}
{{other uses of|NIOS|Nios (disambiguation)}}
{{Infobox CPU architecture
| name = Nios V
| bits = 32-bit
| introduced =
| version =
| design = RISC
| type = Load–store
| encoding = Variable
| branching = Compare-and-branch
| endianness = Little
| page size = 4 KiB
| extensions =
| open = No
| gpr = {{plainlist|
- 16
- 32
}} (Includes one always-zero register)
| fpr = {{plainlist|
- 32
}} (Optional; width depends on available extensions)
}}
Nios V is a 32-bit embedded processor based on the RISC-V instruction set architecture (ISA) designed specifically for the Altera family of field-programmable gate array (FPGA).
Nios V is a successor to Altera's Nios II embedded processor, which had been the company's embedded processor offering for the previous 2 decades, but was discontinued by Intel in 2023.{{Cite web |title=Intel is discontinuing IP ordering codes listed in PDN2312 for Nios® II IP |url=https://www.intel.com/content/www/us/en/content-details/781327/intel-is-discontinuing-ip-ordering-codes-listed-in-pdn2312-for-nios-ii-ip.html |access-date=2025-01-22 |website=Intel}} The migration to the RISC-V ISA transitions Altera's embedded processor offering away from a proprietary ISA to an open architecture with support for industry standard software development and compilation tools.
Nios V CPU family
Nios V is offered in 3 different configurations: Nios V/g (general purpose), Nios V/m (microcontroller), and Nios V/c (compact microcontroller).
= Nios V/g =
The Nios V/g processor is a general-purpose CPU core based on the RISC-V RV32IMZicsr_Zicbom instruction set (optionally with “F” extension):{{Cite web |title=4. Nios® V/g Processor |url=https://www.intel.com/content/www/us/en/docs/programmable/683632/24-3-1/processor-87132.html |access-date=2025-03-19 |website=Intel |language=en}}
- RV32IM(F)Zicsr_Zicbom
- Highest performance Nios V processor
- Supports RTOS embedded system
= Nios V/m =
Nios V/m is a microcontroller core designed to maintain a balance between performance and FPGA resources and is based on the RV32IZicsr variant of the RISC-V architecture and supports either a pipelined or non-pipelined configuration:{{Cite web |title=3. Nios® V/m Processor |url=https://www.intel.com/content/www/us/en/docs/programmable/683632/24-3-1/processor-73511.html |access-date=2025-03-19 |website=Intel |language=en}}
- Balanced for performance and size
- Supports RTOS embedded system
- RV32IZicsr (Pipelined) & RV32IZicsr (Non-Pipelined)
- Pipelined
- Implements RV32IZicsr instruction set.
- Supports five-stages pipelined datapath.
- Non-pipelined
- Implements RV32IZicsr instruction set.
- Supports non-pipelined datapath.
= Nios V/c =
The Nios V/c a compact microcontroller core is designed for smallest possible logic utilization in FPGAs, and is based on the RISC-V RV32I instruction set:{{Cite web |title=2. Nios® V/c Processor |url=https://www.intel.com/content/www/us/en/docs/programmable/683632/24-3-1/processor-47252.html |access-date=2025-03-19 |website=Intel |language=en}}
- Smallest Nios V processor for non-interrupt-driven control application
- No debug features
- RV32I
Hardware generation process
{{unreferenced section|date= March 2025}}
Nios V hardware designers use the Platform Designer system integration tool, a component of the Quartus FPGA development tools, to configure and generate a Nios V system. The configuration graphical user interface (GUI) allows users to choose the Nios V variant, and to add peripheral and I/O-blocks (timers, memory-controllers, serial interface, etc.) to the embedded system. When the hardware specification is complete, Quartus performs the synthesis, place & route to implement the entire system on the selected FPGA target.
See also
References
{{Reflist}}
External links
- [https://community.intel.com/t5/Nios-V-II-Embedded-Design-Suite/bd-p/nios-II-embedded-design-suite Nios II Embedded Design Suite forum]
- RTEMS real-time operating system
{{Programmable Logic}}
{{RISC-based processor architectures}}
{{Soft microprocessors}}
{{DEFAULTSORT:Nios V}}