Pin grid array

{{Short description|Type of integrated circuit packaging with the pins mounted on the underside of the package}}

File:AMD Phenom II X6 1090T (HDT90ZFBK6DGR) CPU-pins PNr°0295.jpg

File:XC68020 bottom p1160085.jpg microprocessor]]

File:AMD Phenom X4 9750 (Underside).JPG X4 9750 processor that uses the AMD AM2+ socket]]

A pin grid array (PGA) is a type of integrated circuit packaging. In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package. The pins are commonly spaced 2.54 mm (0.1") apart,{{cite book|author=Vijay Nath|title=Proceedings of the International Conference on Nano-electronics, Circuits & Communication Systems|url=https://books.google.com/books?id=xvF5DgAAQBAJ&pg=PA304|date=24 March 2017|publisher=Springer|isbn=978-981-10-2999-8|page=304}} and may or may not cover the entire underside of the package.

PGAs are often mounted on printed circuit boards using the through hole method or inserted into a socket. PGAs allow for more pins per integrated circuit than older packages, such as dual in-line package (DIP).

Chip mounting

File:80486 open.jpg

The chip can be mounted either on the top or the bottom (the pinned side). Connections can be made either by wire bonding or through flip chip mounting. Typically, PGA packages use wire bonding when the chip is mounted on the pinned side, and flip chip construction when the chip is on the top side. Some PGA packages contain multiple dies, for example Zen 2 and Zen 3 Ryzen CPUs for the AM4 socket.

= Flip chip =

File:Ppga.jpg

A flip-chip pin grid array (FC-PGA or FCPGA) is a form of pin grid array in which the die faces downwards on the top of the substrate with the back of the die exposed. This allows the die to have a more direct contact with the heatsink or other cooling mechanism.

FC-PGA CPUs were introduced by Intel in 1999, for Coppermine core Pentium III and Celeron{{cite web | title=Intel Releases New Design for sub-$1,000 PCs | publisher=Philippine Daily Inquirer | date=April 24, 2000 }} processors based on Socket 370, and were produced until Socket G3 in 2013. FC-PGA processors fit into zero insertion force (ZIF) motherboard sockets; similar packages were also used by AMD.

Material

= Ceramic =

A ceramic pin grid array (CPGA) is a type of packaging used by integrated circuits. This type of packaging uses a ceramic substrate with pins arranged in a pin grid array. Some CPUs that use CPGA packaging are the AMD Socket A Athlons and the Duron.

A CPGA was used by AMD for Athlon and Duron processors based on Socket A, as well as some AMD processors based on Socket AM2 and Socket AM2+. While similar form factors have been used by other manufacturers, they are not officially referred to as CPGA. This type of packaging uses a ceramic substrate with pins arranged in an array.

File:VIA C3 C5XL CPGA.jpg|A 1.2 GHz VIA C3 microprocessor in a ceramic package

File:Pentium P54 Socket7 PGA.jpg|133 MHz Pentium chip in a ceramic package

= Organic =

File:AMD 754 - PGA ZIF demonstration - 2016.webm)]]

An organic pin grid array (OPGA) is a type of connection for integrated circuits, and especially CPUs, where the silicon die is attached to a plate made out of an organic plastic which is pierced by an array of pins which make the requisite connections to the socket.

File:SL3A2down.JPG|The underside of a Celeron-400 in a PPGA

File:AMD Athlon XP 2000 - Socket A - OPGA.jpg|An OPGA CPU. Note the brown color – many OPGA parts are colored green. The die is in the center of the device, and the four gray circles are foam spacers to relieve pressure from the die, caused by the heat sink.

= Plastic =

File:UpSL3A2.JPG-400 in a PPGA packing]]

Plastic pin grid array (PPGA) packaging was used by Intel for late-model Mendocino core Celeron processors based on Socket 370.{{cite book|author1=Robert Bruce Thompson|author2=Barbara Fritchman Thompson|title=PC Hardware in a Nutshell: A Desktop Quick Reference|url=https://books.google.com/books?id=kG8LcWfruOAC&pg=PT44|date=24 July 2003|publisher=O'Reilly Media, Inc.|isbn=978-0-596-55234-3|page=44}} Some pre-Socket 8 processors also used a similar form factor, although they were not officially referred to as PPGA.

File:Pentium 4 Underside Demonstrating PGA Socket.JPG in a PGA package]]

Pin layout

= Staggered pin =

The staggered pin grid array (SPGA) is used by Intel processors based on Socket 5 and Socket 7. Socket 8 used a partial SPGA layout on half the processor.

File:Socket 7.jpg

File:Cyrix IBM CPU 6x86MX PR200 bottom.jpg

It consists of two square arrays of pins, offset in both directions by half the minimum distance between pins in one of the arrays. Put differently: within a square boundary the pins form a diagonal square lattice. There is generally a section in the center of the package without any pins. SPGA packages are usually used by devices that require a higher pin density than what a PGA can provide, such as microprocessors.

= Stud =

A stud grid array (SGA) is a short-pinned pin grid array chip scale package for use in surface-mount technology. The polymer stud grid array or plastic stud grid array was developed jointly by the Interuniversity Microelectronics Centre (IMEC) and Laboratory for Production Technology, Siemens AG.{{cite web|url=http://www.jsits.com/bga-socket/bga_summary.htm |title=BGA socket/BGA 소켓 |publisher=Jsits.com |access-date=2015-06-05}}[http://www.atplas.com/de/index/mr_index/mr_news/mr_news_business/mr_news_business-fullpage.htm?printout=1&id=7921 link] {{in lang|de}} {{webarchive |url=https://web.archive.org/web/20111001232205/http://www.atplas.com/de/index/mr_index/mr_news/mr_news_business/mr_news_business-fullpage.htm?printout=1&id=7921 |date=October 1, 2011 }}

= rPGA =

The reduced pin grid array was used by the socketed mobile variants of Intel's Core i3/5/7 processors and features a reduced pin pitch of 1{{nbsp}}mm,{{cite web|title=Molex Sockets for Servers, Desktops and Notebooks Earn Intel® Validation|url=http://www.molex.com/mx_upload/editorial/833/Sockets_earn_intel_validation_pr.html|access-date=2016-03-15|archive-date=2019-12-09|archive-url=https://web.archive.org/web/20191209133509/http://www.molex.com/mx_upload/editorial/833/Sockets_earn_intel_validation_pr.html|url-status=dead}} as opposed to the 1.27{{nbsp}}mm pin pitch used by contemporary AMD processors and older Intel processors. It is used in the G1, G2, and G3 sockets.

References

Sources

{{cite web | url=https://www.theregister.co.uk/2000/08/04/what_the_hell/ | title=What the Hell is… a flip-chip? | publisher=The Register | date=August 4, 2010 | access-date=December 30, 2011 | author=Thomas, Andrew}}
{{cite web | url=http://reviews.cnet.com/soho-servers/xseries-335-xeon-dp/1707-3125_7-20584151.html | title=XSERIES 335 XEON DP-2.4G 512 MB | publisher=CNET | date=October 26, 2002 | access-date=December 30, 2011}}
{{cite web | url=http://www.topline.tv/SMT_Nomenclature.pdf | title=SURFACE MOUNT NOMENCLATURE AND PACKAGING }}

External links

[http://support.intel.com/support/processors/sb/CS-009863.htm Intel CPU Processor Identification]
[http://www.semiconductor.net/article/196993-Ball_Grid_Arrays_the_High_Pincount_Workhorses.php Ball Grid Arrays: the High-Pincount Workhorses]{{Dead link|date=May 2020 |bot=InternetArchiveBot |fix-attempted=yes }}, John Baliga, associate editor, Semiconductor International, 9/1/1999
[http://www.epp-online.de/epp/live/de/fachartikelarchiv/ha_artikel/detail/330473.html Spot on component packaging]{{Dead link|date=May 2020 |bot=InternetArchiveBot |fix-attempted=yes }}, 08/1998, Elektronik, Produktion & Prüftechnik
[http://sandbox.cz/~covex/nse/terminy.html Terminology]

Category:Chip carriers