Sparcle

The Sparcle is an experimental 32-bit microprocessor chip developed in 1992 by a consortium of MIT, LSI Corporation, and Sun Microsystems. It was an evolution Sun's SPARC RISC architecture with features geared towards "large-scale multiprocessing".{{cite journal |last1=Agarwal |first1=Anant |display-authors=etal |title=Sparcle: An Evolutionary Processor Design for Large-scale Multiprocessors |journal=IEEE Micro |date=June 1993 |volume=13 |issue=3 |pages=48–61 |doi=10.1109/40.216748 |s2cid=14678370 |url=https://people.eecs.berkeley.edu/~kubitron/cs252/handouts/papers/sparcle-micro-final.pdf |accessdate=Feb 5, 2020}} The chip was manufactured by LSI.

Besides these enhancements the Sparcle was otherwise unremarkable, incorporating 200,000 transistors and dissipating two watts. It included no cache and had a clock speed of less than 40 MHz. The new features included:

• Features to tolerate and synchronize memory and communications latencies
• Features supporting fine-grained synchronization
• Features to initiate actions on remote processors and quickly respond to asynchronous events

The Sparcle was used to build the experimental Alewife computer at MIT.