UltraSPARC T1

Afara Websystems pioneered a radical thread-heavy SPARC design. The company was purchased by Sun, and the intellectual property became the foundation of the CoolThreads line of processors, starting with the T1.

File:UltraSPARCT1 Die layout Fritzchens-Fritz-DavidHalko-zef.webp and floorplan of an UltraSPARC T1 (Niagara, 8-core)]]

File:Pipeline Niagara.svg]]

The UltraSPARC T1 was designed from scratch as a multi-threaded, special-purpose processor, and thus introduced a whole new architecture for obtaining performance. Rather than try to make each core as intelligent and optimized as they can, Sun's goal was to run as many concurrent threads as possible, and maximize utilization of each core's pipeline. The T1's cores are less complex than those of competing processors in order to allow 8 cores to fit on the same die. The cores do not feature out-of-order execution, or a sizable amount of cache.

Single-thread processors depend heavily on large caches for their performance because cache misses result in a wait while the data is fetched from main memory. By making the cache larger, the probability of a cache miss is reduced, but the impact of a miss is still the same.

The T1 cores largely side-step the issue of cache misses by multithreading. Each core is a barrel processor, meaning it switches between available threads each cycle. When a long-latency event occurs, such as cache miss, the thread is taken out of rotation while the data is fetched into cache in the background. Once the long-latency event completes, the thread is made available for execution again. Sharing of the pipeline by multiple threads may make each thread slower, but the overall throughput (and utilization) of each core is much higher. It also means that the impact of cache misses is greatly reduced, and the T1 can maintain high throughput with a smaller amount of cache. The cache no longer needs to be large enough to hold all or most of the "working set", just the recent cache misses of each thread.

Benchmarks demonstrate this approach has worked very well on commercial (integer), multithreaded workloads such as Java application servers, enterprise resource planning (ERP) application servers, email (such as Lotus Domino) servers, and web servers. These benchmarks suggest each core in the UltraSPARC T1 is more powerful than the circa 2001, single-core, single-threaded UltraSPARC III, and at a chip to chip comparison, significantly outperforms other processors on multithreaded integer workloads.{{citation needed|date=October 2011}}

The UltraSPARC T1 contains 279 million transistors and has an area of 378 mm². It was fabricated by Texas Instruments (TI) in their 90 nm complementary metal–oxide–semiconductor (CMOS) process with nine levels of copper interconnect.McGhan, Harlan (6 November 2006). "Niagara 2 Opens the Floodgates". Microprocessor Report. Each core has L1 16 KB instruction cache and 8 KB data cache. L2 cache is 3 MB and there is no L3 cache.

File:Badge and Bezel.jpg T1000 server]]

The T1 processor can be found in the following products from Sun and Fujitsu Computer Systems:

• Sun/Fujitsu/Fujitsu Siemens SPARC Enterprise T1000 and T2000 servers
• Sun Fire T1000 and T2000 servers
• Sun Netra T2000 Server
• Sun Netra CP3060 Blade
• Sun Blade T6300 Server Module

The UltraSPARC T1 microprocessor is unique in its strength and weaknesses, and as such is targeted at specific markets. Rather than being used for high-end number-crunching and ultra-high performance applications, the chip is targeted at network-facing high-demand servers, such as high-traffic web servers, and mid-tier Java, ERP, and CRM application servers, which often utilize a large number of separate threads. One of the limitations of the T1 design is that a single floating point unit (FPU) is shared between all 8 cores, making the T1 unsuitable for applications performing a lot of floating point mathematics. However, since the processor's intended markets do not typically make much use of floating-point operations, Sun did not expect this to be a problem. Sun provides a tool for analysing an application's level of parallelism and use of floating point instructions to determine if it is suitable for use on a T1 or T2 platform.{{cite web | url=https://blogs.oracle.com/WCP/entry/cooltst_cool_threads_selection_tool | title=cooltst: Cool Threads Selection Tool | work=Workload Characterization blog | publisher=Sun Microsystems | date=April 6, 2006 | access-date=2008-05-30}}

In addition to web and application tier processing, the UltraSPARC T1 may be well suited for smaller database applications which have a large user count. One customer has published results showing that a MySQL application running on an UltraSPARC T1 server ran 13.5 times faster than on an AMD Opteron server.{{cite web

| url = http://blogs.digitar.com/media/2/T2000_Experience.pdf

| title = Cruisin' with a T2k

| access-date = 2007-02-07

| author = Thomas Rampelberg

|author2=Jason J. W. Williams

| date = 2006-05-09

| page = 6

| publisher = DigiTar

}}

T1 is the first SPARC processor that supports the Hyper-Privileged execution mode. The SPARC Hypervisor runs in this mode, and it can partition a T1 system into 32 Logical Domains, each of which can run an operating system instance.

Currently{{When|date=March 2021}}, Solaris, Linux, NetBSD and OpenBSD are supported.

Traditionally, commercial software suites such as Oracle Database charge their customers based on the number of processors the software runs on. In early 2006, Oracle changed the licensing model by introducing the processor factor. With a processor factor of .25 for the T1, an 8-core T2000 requires only a 2-CPU license.{{cite web

| url = http://www.oracle.com/corporate/pricing/multicore_faq.pdf

| title = Multi-core Processors: Impact On Oracle Processor Licensing

| access-date = 2007-08-12

| publisher = Oracle

|archive-url = https://web.archive.org/web/20070320080851/http://www.oracle.com/corporate/pricing/multicore_faq.pdf |archive-date = 2007-03-20}}

The "Oracle Processor Core Factor Table"{{cite web|title=Oracle Processor Core Factor Table|url=http://www.oracle.com/us/corporate/contracts/processor-core-factor-table-070634.pdf|publisher=Oracle|access-date=8 September 2011}} has since been updated regularly as new CPUs came to market.

In Q3 2006, IBM introduced the concept of Value Unit (VU) pricing. Each core of the T1 is 30 PVUs (each T2 core is 50 PVUs, and T3 is 70 PVUs) instead of the default value of 100 PVUs per core.{{cite web

| url = http://www-01.ibm.com/software/lotus/passportadvantage/pvu_licensing_for_customers.html

| title = Processor Value Unit Licensing for Distributed SW

| access-date = 2011-06-15

| publisher = IBM

}}

The T1 only offered a single floating-point unit to be shared by the 8 cores, limiting usage in HPC environments. This weakness was mitigated with the follow-on UltraSPARC T2 processor, which included 8 floating point units, as well as other additional features.

Furthermore, the T1 was only available in uniprocessor systems, limiting vertical scalability in large enterprise environments. This weakness was mitigated with the follow-on UltraSPARC T2 Plus, as well as the next generation SPARC T3 and SPARC T4. The UltraSPARC T2+, SPARC T3, and SPARC T4 all offer single, dual, and quad socket configurations.

The T1 had outstanding throughput with massive numbers of threads supported by the processor, but older applications burdened with single thread bottlenecks occasionally exhibited poor overall performance. Single-threaded application weakness was mitigated with the follow-on SPARC T4 processor. The T4 core count was reduced to 8 (from 16 on the T3), the cores were made more complex, the clock rate was nearly doubled — all contributing to faster single thread performance (300% to 500% increase over previous generations).{{cite web

| url = https://www.theregister.co.uk/2011/08/22/oracle_sparc_t4_hot_chips/

| title = Oracle's Sparc T4 chip: Will you pay Larry's premium?

| access-date = 2012-06-21

| publisher = The Register

}} Additional effort was made to add the "critical thread API", where the operating system would detect a bottleneck and would temporarily allocate the resources of an entire core, instead of 1 (of 8) threads, to the targeted application processes exhibiting single threaded CPU bound behavior.{{cite web

| url = http://www.oracle.com/us/corporate/innovation/innovator-hetherington-191304.html

| title = Conversations with Oracle Innovators

| access-date = 2012-06-21

| publisher = Oracle}} This allowed the T4 to uniquely mitigate single threaded bottlenecks, while not having to compromise in the overall architecture to achieve massive multi-threaded throughput.

{{Application Tuning on the Coolthreads Platform}}

The "Coolthreads(TM)" architecture, beginning with the UltraSPARC T1 (with its positive and negative aspects), was certainly influential in the concurrent and future designs of SPARC processors.

{{Main|Rock processor}}

The original UltraSPARC T1 was designed for single CPU systems only and is not capable of SMP. "Rock" was a more ambitious project, intended to support multiple-chip server architectures, targeting traditional data-facing workloads such as databases. It was seen as more a follow-on to Sun's SMP processors such as UltraSPARC IV, rather than a replacement for the UltraSPARC T1 or T2, but was canceled in the timeframe of Oracle's acquisition of Sun.

{{Main|UltraSPARC T2}}

Formerly known by the codename Niagara 2, the follow-on to the UltraSPARC T1, the T2 provides eight cores. Unlike the T1, each core supports 8 threads per core, one FPU per core, one enhanced cryptographic unit per core, and CPU embedded 10 Gigabit Ethernet network controllers.

{{Clear}}

{{Main|UltraSPARC T2}}

In February 2007, Sun announced at its annual analyst summit that its third-generation simultaneous multithreading design, code-named Victoria Falls, was taped out in October 2006. A two-socket server (2 RU) will have 128 threads, 16 cores, and a 65× performance improvement over UltraSPARC III.{{cite web | url=http://www.sun.com/events/sas2007/docs/09_fowler_sas_07.pdf | title=Growth by Design | access-date=2007-02-07 | first=John | last=Fowler | date=February 6, 2007 | publisher=Sun Microsystems | page=21 }}

At the Hot Chips 19 conference, Sun announced that Victoria Falls will be in two-way and four-way servers. Thus, a single 4-way SMP server will support 256 concurrent hardware threads.{{cite web | url=http://www.opensparc.net/pubs/preszo/07/HC19.sphillips.v1.pdf | title=Victoria Falls: Scaling Highly-Threaded Processor Cores | access-date=2007-08-24 | first=Phillips | last=Stephen | date=August 21, 2007 | publisher=Sun Microsystems | page=24 }}

In April 2008, Sun released 2-way UltraSPARC T2 Plus servers, the SPARC Enterprise T5140 and T5240.

In October 2008, Sun released 4-way UltraSPARC T2 Plus SPARC Enterprise T5440 server.{{cite web | url=http://www.sun.com/aboutsun/pr/2008-10/sunflash.20081013.1.xml | title=Sun and Fujitsu's SPARC Enterprise T5440 Server Redefines Midrange Enterprise Computing with Industry-Leading Price Points, Power Management and Multiple World Record Benchmarks | access-date=2008-10-13 | date=October 13, 2008 | publisher=Sun Microsystems}}

{{Clear}}

{{Main|SPARC T3}}

In October 2006, Sun disclosed that Niagara 3 will be built with a 45 nm process.{{Citation needed|date=August 2008}} The Register, reported in June 2008 that the microprocessor will have 16 cores, incorrectly suggesting each core would have 16 threads. During the Hot Chips 21 conference Sun revealed the chip has a total of 16 cores and 128 threads.Sanjay Patel, Stephen Phillips and Allan Strong. "[http://www.hotchips.org/archives/hc21/3_tues/HC21.25.800.ServerSystemsII-Epub/HC21.25.810.Patel-SUN-RainbowFalls.pdf Sun's Next-Generation Multi-threaded Processor - Rainbow Falls: Sun's Next Generation CMT Processor] {{Webarchive|url=https://web.archive.org/web/20110723211022/http://www.hotchips.org/archives/hc21/3_tues/HC21.25.800.ServerSystemsII-Epub/HC21.25.810.Patel-SUN-RainbowFalls.pdf |date=2011-07-23 }}". HOT CHIPS 21.Stokes, Jon (February 9, 2010). "[https://arstechnica.com/business/news/2010/02/two-billion-transistor-beasts-power7-and-niagara-3.ars Two billion-transistor beasts: POWER7 and Niagara 3]". Ars Technica. According to the ISSCC 2010 presentation:

"A 16-core SPARC SoC processor enables up to 512 threads in a 4-way glueless system to

maximize throughput. The 6 MB L2 cache of 461 GB/s and the 308-pin SerDes I/O of 2.4 Tb/s

support the required bandwidth. Six clock and four voltage domains, as well as power

management and circuit techniques, optimize performance, power, variability and yield trade-offs

across the 377mm² die."J. Shin, K. Tam, D. Huang, B. Petrick, H. Pham, C. Hwang, H. Li, A. Smith, T. Johnson,

F. Schumacher, D. Greenhill, A. Leon, A. Strong. "A 40nm 16-Core 128-Thread CMT SPARC SoC Processor". ISSCC 2010.

{{main|SPARC T4}}

The T4 CPU was released in late 2011. The new T4 CPU will drop from 16 cores (on the T3) back to 8 cores (as used on the T1, T2, and T2+). The new T4 core design (named "S3") feature improved per-thread performance, due to introduction of out-of-order execution, as well as having additional improved performance for single-threaded programs.{{cite web|title=Oracle's SPARC T4 chip: Will you pay Larry's premium?|website=The Register|url=https://www.theregister.co.uk/2011/08/22/oracle_sparc_t4_hot_chips/}}{{citation|url=https://arstechnica.com/business/news/2011/09/sparc-t4-looks-to-be-good-enough-to-stave-off-defections-to-x86-linux.ars| title = SPARC T4 looks to be good enough to stave off defections to x86, Linux|author = Sean Gallagher| date = 28 September 2011| publisher = Ars Technica| work = arstechnica.com}}

In 2010, Larry Ellison announced that Oracle will offer Oracle Linux on the UltraSPARC platform, and the port was scheduled to be available in the T4 and T5 timeframe.{{cite web|last=Niccolai|first=James|title=Ellison: Oracle Enterprise Linux Coming to Sparc|url=http://www.pcworld.com/article/212564/ellison_oracle_enterprise_linux_coming_to_sparc.html|publisher=PCWorld}}

John Fowler, Executive Vice President Systems Oracle, in Openworld 2014 said Linux will be able to run on Sparc at some point.

{{cite web|title=Oracle says Sparc M7 chip will put an end to Heartbleed|url=http://www.theinquirer.net/inquirer/news/2373412/oracle-says-sparc-m7-chip-will-put-an-end-to-heartbleed|archive-url=https://web.archive.org/web/20141003001725/http://www.theinquirer.net/inquirer/news/2373412/oracle-says-sparc-m7-chip-will-put-an-end-to-heartbleed|url-status=unfit|archive-date=October 3, 2014|publisher=The Inquirer}}

{{cite web|title=binutils patches|url=http://sourceware.org/ml/binutils/2014-10/msg00038.html|publisher=binutils ml}}

{{cite web|title=linux kernel patches|url=http://marc.info/?l=linux-sparc&m=141015717530083|publisher=sparc linux ml}}

{{cite web|title=libc patches|url=http://sourceware.org/ml/libc-alpha/2014-11/msg00202.html|publisher=libc ml}}

{{main|SPARC T5}}

The new T5 CPU features 128 threads over 16 cores and is manufactured with a 28 nanometer technology.

{{Portal|Free and open-source software}}

On March 21, 2006, Sun made the UltraSPARC T1 processor design available under the GNU General Public License via the OpenSPARC project.{{cite web|url=https://www.oracle.com/servers/technologies/opensparc-t1-page.html |title=Open SPARC T1|access-date=2021-01-16 |website=oracle.com}} The published information includes:

• Verilog source code of the UltraSPARC T1 design;
• Verification suite and simulation models;
• ISA specification (UltraSPARC Architecture 2005);
• The Solaris 10 OS simulation images.

{{Reflist|30em}}

• [http://www.oracle.com/technetwork/systems/opensparc/opensparc-t1-page-1444609.html OpenSPARC T1 and Specifications]
• [http://www.opensparc.net/ OpenSPARC Overview]
• [https://web.archive.org/web/20060901143352/http://ogun.stanford.edu/%7ekunle/publications/niagra_spectrum.pdf Sun's Big Splash] by Linda Geppert, in IEEE Spectrum, January 2005
• [https://web.archive.org/web/20060901143530/http://ogun.stanford.edu/%7ekunle/publications/niagra_micro.pdf Niagara, a 32-way Multithreaded SPARC Processor] by Poonacha Kongetira, Kathirgamar Aingaran, Kunle Olukotun, in IEEE Micro, March–April 2005

{{Sun hardware}}

{{DEFAULTSORT:Ultrasparc T1}}

Category:Sun microprocessors

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