SPARC T4
File:Oracle SPARC T4 chip 028.jpg
{{Infobox CPU
| name = SPARC T4
| image =
| image_size =
| caption =
| produced-start = 2011
| produced-end =
| slowest = 2.85
| fastest = 3.0
| slow-unit = GHz
| fast-unit = GHz
| fsb-slowest =
| fsb-fastest =
| fsb-slow-unit =
| fsb-fast-unit =
| size-from = 40 nm
| size-to =
| soldby =
| designfirm =
| manuf1 =
| core1 = S3
| sock1 =
| pack1 =
| brand1 =
| arch = SPARC V9
| microarch =
| cpuid =
| code =
| numcores = 8
| l1cache = 8×(16+16) kB
| l2cache = 8×128 kB
| l3cache = 4 MB
| application =
| predecessor = SPARC T3
| successor = SPARC T5
}}
The SPARC T4 is a SPARC multicore microprocessor introduced in 2011 by Oracle Corporation. The processor is designed to offer high multithreaded performance (8 threads per core, with 8 cores per chip), as well as high single threaded performance from the same chip.{{citation|url= http://www.oracle.com/us/products/servers-storage/servers/sparc-enterprise/t-series/sparc-t4-processor-ds-497205.pdf | title = SPARC T4 Processor Data(archived) Sheet| publisher = Oracle Corporation| archive-url = https://web.archive.org/web/20120516005219/http://www.oracle.com/us/products/servers-storage/servers/sparc-enterprise/t-series/sparc-t4-processor-ds-497205.pdf| archive-date = 2012-05-16}} The chip is the 4th generation{{citation|url = http://www.oracle.com/us/products/servers-storage/servers/sparc-enterprise/idc-dce-2012-1612359.pdf | title = SPARC Servers: An Effective Choice for Efficiency in the Datacenter, p. 9 |author1=Jean S. Bozman |author2=Matthew Eastwood | date= April 2012 | publisher = IDC}} processor in the T-Series family. Sun Microsystems brought the first T-Series processor (UltraSPARC T1) to market in 2005.
The chip is the first Sun/Oracle SPARC chip to use dynamic threading{{citation|url=https://www.theregister.co.uk/2011/09/27/oracle_sparc_t4_chip_servers/| title = Oracle rises for Unix server push| author = Timothy Prickett Morgan| date =27 September 2011| publisher = The Register| work= www.theregister.co.uk|pages = 1–2}} and out-of-order execution.{{citation|url = http://www.computer.org/csdl/mags/mi/2012/02/index.html | title = IEEE Micro, vol. 32, no. 2, Sparc T4: A Dynamically Threaded Server-on-a-Chip, pp. 8-19 |author1=Manish Shah |author2=Robert Golla |author3=Gregory Grohoski |author4=Paul Jordan |author5=Jama Barreh |author6=Jeff Brooks |author7=Mark Greenberg |author8=Gideon Levinsky |author9=Mark Luttrell |author10=Christopher Olson |author11=Zeid Samoail |author12=Matt Smittle |author13=Tom Ziaja | date= March–April 2012 | publisher = IEEE Computer Society}} It incorporates one floating point unit and one dedicated cryptographic unit per core. The cores use the 64-bit SPARC Version 9 architecture running at frequencies between 2.85 GHz and 3.0 GHz, and are built in a 40 nm process with a die size of {{convert|403|mm2|sqin|abbr=on|lk=off}}.
History and design
An eight core, eight thread per core chip built in a 40 nm process and running at 2.5 GHz was described in Sun Microsystems' processor roadmap of 2009. It was codenamed "Yosemite Falls" and given an expected release date of late 2011. The processor was expected to introduce a new microarchitecture, codenamed "VT Core". The online technology website The Register speculated that this chip would be named "T4", being the successor to the SPARC T3.{{citation|url = https://www.theregister.co.uk/2009/09/11/sun_sparc_roadmap_revealed/| title = Sun's Sparc server roadmap revealed| author =Timothy Prickett Morgan| date= 11 September 2009 | work = www.theregister.co.uk| publisher = The Register| pages =1–2}} The Yosemite Falls CPU product remained on Oracle Corporation's processor roadmap after the company took over Sun in early 2010.{{citation|url = https://www.theregister.co.uk/2010/01/28/oracle_sun_systems_roadmap/ |pages=1–2| work = www.register.co.uk| author = Timothy Prickett Morgan| date = 28 January 2010| publisher = The Register|title=Oracle to invest in Sparc iron, clusters}} In December 2010 the T4 processor was confirmed by Oracle's VP of hardware development to be designed for improved per-thread performance, with eight cores, and with an expected release within one year.{{citation|url= https://www.theregister.co.uk/2010/12/23/oracle_sparc_t_chip_roadmap_revisited/| title = Oracle revisits Sparc T processor roadmap| author =Timothy Prickett Morgan|date =23 December 2010| work = www.theregister.co.uk| publisher = The Register}}{{citation| editor = Diana Reichardt| url = http://www.oracle.com/us/corporate/innovation/innovator-hetherington-191304.html| title = Rick Hetherington : Oracle Innovation Showcase (Conversations with Oracle Innovators)| publisher = Oracle Corporation| work = www.oracle.com}}
The processor design was presented at the 2011 Hot Chips conference.{{citation|url = http://www.hotchips.org/wp-content/uploads/hc_archives/hc23/HC23.19.7-Server/HC23.19.731-T4-Golla-Oracle-hotchips_corrected.pdf | title = T4: A Highly Threaded Server-on-a-Chip with Native Support for Heterogeneous Computing |author1=Robert Golla |author2=Paul Jordan | date= August 19, 2011 | publisher = Hot Chips}} The cores (renamed "S3" from "VT") included a dual-issue 16 stage integer pipeline, and 11-cycle floating point pipeline, both giving improvements over the previous ("S2") core used in the SPARC T3 processor. Each core has associated 16 KB data and 16 KB instruction L1 caches, and a unified 128 KB L2 Cache. All eight cores share 4 MB L3 cache, and the total transistor count is approximately 855 million. The design was the first Sun/Oracle SPARC processor with out-of-order execution{{citation| url = http://news.techeye.net/internet/oracles-ellison-spins-sparc-t4| title = Oracle's Ellison spins SPARC T4| work = news.techeye.net| date = 28 September 2011| author = Nick Farrell| publisher = TechEye| access-date = 28 September 2011| archive-url = https://web.archive.org/web/20140731132059/http://news.techeye.net/internet/oracles-ellison-spins-sparc-t4| archive-date = 31 July 2014| url-status = dead}} and was the first processor in the SPARC T-Series family to include the ability to issue more than one instruction per cycle to a core's execution units.{{citation|url=http://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/o11-090-sparc-t4-arch-496245.pdf| title =Oracle's SPARC T4-1, SPARC T4-2, SPARC T4-4, and SPARC T4-1B Server Architecture| publisher=Oracle Corporation}}
The T4 processor was officially introduced as part of Oracle's SPARC T4 servers in September 2011.{{citation|url = http://news.techeye.net/hardware/oracle-lords-it-over-hp-and-ibm-with-sparc-t4|title = Oracle lords it over HP and IBM with SPARC T4|author = Matthew Finnegan|work = news.techeye.net|publisher = TechEye|url-status = dead|archive-url = https://web.archive.org/web/20110929220438/http://news.techeye.net/hardware/oracle-lords-it-over-hp-and-ibm-with-sparc-t4|archive-date = 2011-09-29}} Initial product releases of a single processor T4-1 rack server ran at 2.85 GHz. The dual processor T4-2 ran at the same 2.85 GHz frequency, and the quad processor T4-4 server ran at 3.0 GHz.{{citation|url=http://www.oracle.com/us/products/servers-storage/servers/sparc-enterprise/t-series/sparc-t4-4-ds-486944.pdf | title = SPARC T4-4 Server Data Sheet| publisher = Oracle Corporation}}
The SPARC S3 core also include a thread priority mechanism (called "dynamic threading") whereby each thread is allocated resources based on need, giving increased performance. Most S3 core resources are shared among all active threads, up to 8 of them. Shared resources include branch prediction structures, various buffer entries, and out-of-order execution resources. Static resource allocation reserves the resources to the threads based on a policy whether the thread can use them or not. Dynamic threading allocates these resources to the threads that are ready and will use them, thus improving performance.
Cryptographic performance was also increased over the T3 chip by design improvements including a new set of cryptographic instructions. UltraSPARC T2 and T3's per-core cryptographic coprocessors were replaced with in-core accelerators and instruction-based cryptography. The implementation is designed to achieve wire speed encryption and decryption on the SPARC T4's 10-Gbit/s Ethernet ports.
The architectural changes are claimed to deliver a 5x improvement in single thread integer performance and twice the per-thread throughput performance compared to the previous generation T3. The published SPECjvm2008 result for a 16-core T4-2 is 454 ops/m{{citation|url=http://www.specbench.org/jvm2008/results/res2011q4/jvm2008-20111101-00011.peak/SPECjvm2008.peak.html | title = SPECjvm2008 Peak, Oracle SPARC T4-2 | date= November 2011 | publisher = Oracle Corporation}} and 321 ops/m{{citation|url=http://www.specbench.org/jvm2008/results/res2010q4/jvm2008-20100920-00010.peak/SPECjvm2008.peak.html | title = SPECjvm2008 Peak, Oracle SPARC T3-2 | date= October 2010 | publisher = Oracle Corporation}} for the 32-core T3-2 which is a ratio of 2.8x in performance per core.
References
{{Reflist|2}}
External links
- {{citation|url=http://www.oracle.com/us/corporate/features/sparc-t4-announcement-494846.html| title =SPARC T4 Processor Delivers Performance Boost for a Wide Range of Workloads| work = www.oracle.com| publisher = Oracle Corporation|ref=none}}
- {{citation|url=https://www.youtube.com/watch?v=If7kmiPyQjY | title =Geek Fest! Talking About the Design of the T4 and T5 SPARC Processor | work = www.oracle.com| publisher = Oracle Corporation|date=2012-10-12|ref=none}}
{{Sun hardware}}
Category:SPARC microprocessors
Category:Oracle microprocessors