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VIA PadLock

VIA PadLock is a central processing unit (CPU) instruction set extension to the x86 microprocessor instruction set architecture (ISA) found on processors produced by VIA Technologies and Zhaoxin. Introduced in 2003 with the VIA Centaur CPUs, the additional instructions provide hardware-accelerated random number generation (RNG), Advanced Encryption Standard (AES), SHA-1, SHA256, and Montgomery modular multiplication.{{cite web |date=August 4, 2005 |title=VIA PadLock Programming Guide |url=http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=261 |url-status=dead |archive-url=https://web.archive.org/web/20100526054140/http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=261 |archive-date=May 26, 2010}}{{cite web |title=VIA PadLock - Wicked Fast Encryption |url=http://www.logix.cz/michal/doc/article.xp/padlock-en |website=www.logix.cz}}

Instructions

The PadLock instruction set can be divided into four subsets:

  • Random number generation (RNG)
  • XSTORE: Store Available Random Bytes (aka XSTORERNG)
  • REP XSTORE: Store ECX Random Bytes
  • Advanced cryptography engine (ACE) - for AES crypto; two versions
  • REP XCRYPTECB: Electronic code book
  • REP XCRYPTCBC: Cipher Block Chaining
  • REP XCRYPTCTR: Counter Mode (ACE2)
  • REP XCRYPTCFB: Cipher Feedback Mode
  • REP XCRYPTOFB: Output Feedback Mode
  • SHA hash engine (PHE)
  • REP XSHA1: Hash Function SHA-1
  • REP XSHA256: Hash Function SHA-256
  • Montgomery multiplier (PMM)
  • REP MONTMUL

The padlock capability is indicated via a CPUID instruction with EAX = 0xC0000000. If the resultant EAX >= 0xC0000001, the CPU is aware of Centaur features. An additional request with EAX = 0xC0000001 then returns PadLock support in EDX. The padlock capability can be toggled on or off with MSR 0X1107.

VIA PadLock found on some Zhaoxin CPUs have SM3 hashing and SM4 block cipher added.{{cite web |title=Kaixian ZX-C+ Series 4-core CPU |url=http://en.zhaoxin.com/ZXC.aspx?seriesid=5 |website=Shanghai Zhaoxin Semiconductor Co., Ltd.}}

= CPUs with PadLock =

{{see also|List of VIA microprocessors}}

  • All VIA Nano CPUs support SHA, AES, and RNG.
  • All VIA Eden CPUs since 2003 (C3 Nehemiah) support AES and RNG. All these released since 2006 support AES, RNG, SHA, and PMM.
  • All VIA C7 CPUs support AES, RNG, SHA, and PMM.

Supporting software

  • Linux kernel since 2.6.11 has PadLock AES. PadLock SHA was introduced in 2.6.19. These are handled as "hardware crypto devices".{{cite web |title=VIA PadLock support for Linux |url=http://www.logix.cz/michal/devel/padlock/ |website=www.logix.cz}}
  • FreeBSD, NetBSD and OpenBSD support PadLock.{{man|4|padlock|FreeBSD}}
  • OpenSSL supports PadLock AES and SHA since 2004 (0.9.7f/0.9.8a).{{cite web |title=openssl/engines/e_padlock.c |url=https://github.com/openssl/openssl/blob/master/engines/e_padlock.c |website=GitHub |date=26 November 2022 |language=en}}
  • GNU assembler supports PadLock since 2004.{{cite web |title=Added new instructions for next version of VIA PadLock core. · bminor/binutils-gdb@30d1c83 |url=https://github.com/bminor/binutils-gdb/commit/30d1c83669cde497bd6816d05b62e1cfd37146d2#diff-7b0511339617c8293942595285f45b07 |website=GitHub |language=en}}

See also

References

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Category:Instruction processing

Category:X86 architecture

PadLock

Category:Computer-related introductions in 2003