Xeon Phi#Knights Mill
{{Short description|Series of x86 manycore processors from Intel}}
{{distinguish|text= the ATI Xenos, Xenon, or the regular Intel Xeon}}
{{Use dmy dates|date=October 2020}}
{{Infobox CPU
| name = Xeon Phi
| image = Intel Xeon Phi 5100.jpg
| produced-start = 2010
| slowest = 1.053
| fastest = 1.7
| numcores = 32-72
| l1cache = 32 KB per core
| l2cache = 512 KB per core
| created =
| size-from = 45 nm transistors
| size-to = 14 nm transistors (tri-gate)
| arch = x86-16 (except coprocessor form factor), IA-32, x86-64{{cite web|url=https://engineering.purdue.edu/~eigenman/ECE563/Handouts/intel-xeon-phi-systemsoftwaredevelopersguide.pdf#page=16|archive-url=https://web.archive.org/web/20240421095018/https://engineering.purdue.edu/~eigenman/ECE563/Handouts/intel-xeon-phi-systemsoftwaredevelopersguide.pdf|archive-date=21 Apr 2024|url-status=live|title=Intel® Xeon Phi™ Coprocessor System Software Developers Guide |publisher=Intel|date=8 Nov 2012|access-date=1 May 2024|pages=16}}
| extensions = AVX, AVX2, AVX-512
| sock1 = LGA 3647
| sock2 = PCI Express 3.0 x16
| model1 = {{unbulleted list|Xeon Phi 3100|Xeon Phi 5100|Xeon Phi 7100|Xeon Phi 7200}}
| predecessor =
| successor =
|soldby=Intel|designfirm=Intel|manuf1=Intel|memory1=Up to DDR4 115.4 GB/s with ECC support|amountmemory=Up to 384 GB and 16 GB|caption=Xeon Phi 5100 without heatsink|application=Supercomputers
High-performance computing|core1=Knights Ferry|core2=Knights Corner|core3=Knights Landing|core4=Knights Mill|core5=Knights Hill|memory2=MCDRAM 400+ GB/s|microarch=Larrabee}}
Xeon Phi is a discontinued series of x86 manycore processors designed and made by Intel. It was intended for use in supercomputers, servers, and high-end workstations. Its architecture allowed use of standard programming languages and application programming interfaces (APIs) such as OpenMP.{{cite web|url=https://software.intel.com/en-us/articles/best-known-methods-for-using-openmp-on-intel-many-integrated-core-intel-mic-architecture|title=Best Known Methods for Using OpenMP on Intel Many Integrated Core (Intel MIC) Architecture|author=robert-reed|date=4 February 2013|website=software.intel.com}}{{cite book|last1=Jeffers|first1=James|last2=Reinders|first2=James|title=Intel Xeon Phi Coprocessor High Performance Programming|publisher=Morgan Kaufmann|date=1 March 2013|isbn=978-0124104143}}
Xeon Phi launched in 2010. Since it was originally based on an earlier GPU design (codenamed "Larrabee") by Intel{{cite web|url=https://www.extremetech.com/extreme/290963-intel-quietly-kills-off-xeon-phi|title=Intel Quietly Kills Off Xeon Phi|first=Joel|last=Hruska|date=8 May 2019|website=ExtremeTech}} that was cancelled in 2009,{{cite web|url=https://www.reuters.com/article/us-intel/intel-scraps-graphics-chip-based-on-larrabee-idUSTRE5B51QR20091206?type=technologyNews|title=Intel scraps graphics chip based on Larrabee|date=6 December 2009|work=Reuters}} it shared application areas with GPUs. The main difference between Xeon Phi and a GPGPU like Nvidia Tesla was that Xeon Phi, with an x86-compatible core, could, with less modification, run software that was originally targeted to a standard x86 CPU.
Initially in the form of PCI Express-based add-on cards, a second-generation product, codenamed Knights Landing, was announced in June 2013.{{cite journal|last1=Sodani|first1=Avinash|display-authors=etal|title=Knights Landing: Second-Generation Intel Xeon Phi Product|journal=IEEE Micro|volume=36|issue=2|year=2016|pages=34–46|doi=10.1109/MM.2016.25|s2cid=28837176}} These second-generation chips could be used as a standalone CPU, rather than just as an add-in card.
File:Tianhe-2.jpg supercomputer uses Xeon Phi processors.]]
In June 2013, the Tianhe-2 supercomputer at the National Supercomputer Center in Guangzhou (NSCC-GZ) was announced{{cite web|title=TOP500 - June 2013|url=https://www.top500.org/lists/2013/06/|publisher=TOP500|access-date=18 June 2013}} as the world's fastest supercomputer ({{As of|2023|06|lc=y}}, it is {{Numero|10}}{{Cite web |title=June 2023 {{!}} TOP500 Supercomputer Sites |url=https://www.top500.org/lists/top500/list/2023/06/ |access-date= |website=www.top500.org |language=en}}). It used Intel Xeon Phi coprocessors and Ivy Bridge-EP Xeon E5 v2 processors to achieve 33.86 petaFLOPS.{{cite web|url=https://newsroom.intel.com/community/intel_newsroom/blog/2013/06/17/intel-powers-the-worlds-fastest-supercomputer-reveals-new-and-future-high-performance-computing-technologies|title=Intel Powers the World's Fastest Supercomputer, Reveals New and Future High Performance Computing Technologies|access-date=21 June 2013}}
The Xeon Phi product line directly competed with Nvidia's Tesla and AMD Radeon Instinct lines of deep learning and GPGPU cards. It was discontinued due to a lack of demand and Intel's problems with its 10 nm node.{{cite web|url=https://www.techpowerup.com/246237/intel-is-giving-up-on-xeon-phi-eight-more-models-declared-end-of-life|title=Intel is Giving up on Xeon Phi - Eight More Models Declared End-Of-Life|author=W1zzard|date=24 July 2018|website=TechPowerUp}}
History
| class="wikitable" | ||
| Code name | Process | Comments |
|---|---|---|
| Knights Ferry | 45 nm | offered as PCI Express card; derived from Larrabee project |
| Knights Corner | 22 nm | style="max-width:0"| derived from P54C; vector processing unit; first device to be announced as Xeon Phi; AVX-512-like encoding |
| Knights Landing | 14 nm | derived from Silvermont/Airmont (Intel Atom);{{cite web|url=https://www.golem.de/news/knights-landing-intel-veroeffentlicht-xeon-phi-mit-bis-zu-7-teraflops-1606-121642.html|title=Knights Landing: Intel veröffentlicht Xeon Phi mit bis zu 7 Teraflops - Golem.de|author=Marc Sauter|date=20 June 2016|language=de|website=www.golem.de}} AVX-512 |
| Knights Mill | 14 nm | nearly identical to Knights Landing but optimized for deep learning |
| Knights Hill | 10 nm | cancelled |
=Background=
The Larrabee microarchitecture (in development since 2006{{citation |url=https://www.theinquirer.net/inquirer/news/1029138/new-from-intel-its-mini-cores |archive-url=https://web.archive.org/web/20090829084338/http://www.theinquirer.net/inquirer/news/1029138/new-from-intel-its-mini-cores |url-status=unfit |archive-date=29 August 2009 |title= New from Intel: It's Mini-Cores! |author= Charlie Demerjian |date= 3 July 2006 |work= theinquirer.net |publisher= The Inquirer}}) introduced very wide (512-bit) SIMD units to an x86 architecture based processor design, extended to a cache-coherent multiprocessor system connected via a ring bus to memory; each core was capable of four-way multithreading. Due to the design being intended for GPU as well as general purpose computing, the Larrabee chips also included specialised hardware for texture sampling.{{cite journal|last2=Cavin|first2=D.|last3=Espasa|first3=E.|last4=Grochowski|first4=T.|last5=Juan|first5=M.|last6=Hanrahan|first6=P.|last7=Carmean|first7=S.|last8=Sprangle|first8=A.|last9=Forsyth|first9=J.|date=August 2008|title=Larrabee: A Many-Core x86 Architecture for Visual Computing|url=https://download-software.intel.com/sites/default/files/m/9/4/9/larrabee_manycore.pdf|journal=ACM Transactions on Graphics|series=Proceedings of ACM SIGGRAPH 2008|volume=27|issue=3|pages=18:11|doi=10.1145/1360612.1360617|issn=0730-0301|first1=L.|last1=Seiler|first10=R.|last10=Abrash|first11=R.|last11=Dubey|first12=E.|last12=Junkins|first13=T.|last13=Lake|first14=P.|last14=Sugerman|s2cid=52799248|access-date=2008-08-06|archive-url=https://web.archive.org/web/20150910141236/https://software.intel.com/sites/default/files/m/9/4/9/larrabee_manycore.pdf|archive-date=2015-09-10|url-status=dead}}{{citation
|url=https://www.stanford.edu/class/ee380/Abstracts/100106-slides.pdf
|title= SIMD Programming with Larrabee
|author= Tom Forsyth
|publisher= Intel
}} The project to produce a retail GPU product directly from the Larrabee research project was terminated in May 2010.{{citation
|url= https://www.anandtech.com/show/3738/intel-kills-larrabee-gpu-will-not-bring-a-discrete-graphics-product-to-market
|title= Intel Kills Larrabee GPU, Will Not Bring a Discrete Graphics Product to Market\
|author= Ryan Smith
|date= 25 May 2010
|publisher= AnandTech |website= www.anandtech.com
}}
Another contemporary Intel research project implementing x86 architecture on a many-multicore processor was the 'Single-chip Cloud Computer' (prototype introduced 2009{{citation|url=https://www.pcworld.com/article/183653/intel_48core_singlechip_cloud_computer_improves_power_efficiency.html |title= Intel 48-Core "Single-Chip Cloud Computer" Improves Power Efficiency |author= Tony Bradley |publisher= PCWorld |work= pcworld.com |date= 3 December 2009}}), a design mimicking a cloud computing computer datacentre on a single chip with multiple independent cores: the prototype design included 48 cores per chip with hardware support for selective frequency and voltage control of cores to maximize energy efficiency, and incorporated a mesh network for inter-chip messaging. The design lacked cache-coherent cores and focused on principles that would allow the design to scale to many more cores.{{citation|url= http://techresearch.intel.com/ProjectDetails.aspx?Id=1 |title= Intel Research : Single-Chip Cloud Computer |publisher= Intel |work= techresearch.intel.com}}
The Teraflops Research Chip (prototype unveiled 2007{{citation |url= https://www.pcworld.com/article/128924/intel_tests_chip_design_with_80core_processor.html |title= Intel Tests Chip Design With 80-Core Processor |author= Ben Ames |publisher= IDG News |date= 11 February 2007 |work= pcworld.com |access-date= 14 November 2018 |archive-date= 17 January 2012 |archive-url= https://web.archive.org/web/20120117194144/https://www.pcworld.com/article/128924/intel_tests_chip_design_with_80core_processor.html |url-status= dead }}) is an experimental 80-core chip with two floating-point units per core, implementing a 96-bit VLIW architecture instead of the x86 architecture.{{cite web|url=http://www.xbitlabs.com/news/cpu/display/20070212224710.html|title=Intel Details 80-Core Teraflops Research Chip - X-bit labs|work=xbitlabs.com|access-date=27 August 2015|url-status=dead|archive-url=https://web.archive.org/web/20150205070552/http://www.xbitlabs.com/news/cpu/display/20070212224710.html|archive-date=5 February 2015}} The project investigated intercore communication methods, per-chip power management, and achieved 1.01 TFLOPS at 3.16 GHz consuming 62 W of power.{{citation|url=https://download.intel.com/pressroom/kits/Teraflops/Teraflops_Research_Chip_Overview.pdf |title= Intel's Teraflops Research Chip |publisher= Intel |work= download.intel.com |archive-url=https://web.archive.org/web/20210516003332/https://download.intel.com/pressroom/kits/Teraflops/Teraflops_Research_Chip_Overview.pdf |archive-date=2021-05-16 |url-status=dead}}{{citation |url= http://www.xbitlabs.com/news/cpu/display/20070212224710.html |title= Intel Details 80-Core Teraflops Research Chip |author= Anton Shilov |date= 12 February 2007 |publisher= Xbit laboratories |work= xbitlabs.com |url-status= dead |archive-url= https://web.archive.org/web/20150205070552/http://www.xbitlabs.com/news/cpu/display/20070212224710.html |archive-date= 5 February 2015}}
={{anchor|Knights Ferry}}Knights Ferry=
Intel's Many Integrated Core (MIC) prototype board, named Knights Ferry, incorporating a processor codenamed Aubrey Isle was announced 31 May 2010. The product was stated to be a derivative of the Larrabee project and other Intel research including the Single-chip Cloud Computer.{{citation |url= http://www.zdnet.co.uk/news/desktop-hardware/2010/06/01/intel-unveils-many-core-knights-platform-for-hpc-40089093/ |title= Intel unveils many-core Knights platform for HPC |author= Rupert Goodwins |publisher= ZDNet |date= 1 June 2010 |work= zdnet.co.uk}}{{citation |url= https://www.intel.com/pressroom/archive/releases/2010/20100531comp.htm |title= Intel News Release : Intel Unveils New Product Plans for High-Performance Computing |date= 31 May 2010 |work= intel.com |publisher= Intel}}
The development product was offered as a PCIe card with 32 in-order cores at up to 1.2 GHz with four threads per core, 2 GB GDDR5 memory,{{citation|title=Runners and riders in GPU steeplechase|date=24 June 2010|url=http://people.maths.ox.ac.uk/gilesm/talks/nag_tpc10.pdf|author=Mike Giles|work=people.maths.ox.ac.uk|pages=8–10}} and 8 MB coherent L2 cache (256 KB per core with 32 KB L1 cache), and a power requirement of ≈300 W, built at a 45 nm process. In the Aubrey Isle core a 1,024-bit ring bus (512-bit bi-directional) connects processors to main memory.{{citation |url= http://www.many-core.group.cam.ac.uk/ukgpucc2/talks/Elgar.pdf |title= Intel Many Integrated Core Architecture |date= December 2010 |publisher= Intel |work= many-core.group.cam.ac.uk |url-status= dead |archive-url= https://web.archive.org/web/20120402211714/http://www.many-core.group.cam.ac.uk/ukgpucc2/talks/Elgar.pdf |archive-date= 2 April 2012}} Single-board performance has exceeded 750 GFLOPS. The prototype boards only support single-precision floating-point instructions.{{citation |url= https://www.eetimes.com/electronics-news/4217092/OEMs-show-systems-with-Intel-MIC-chips |title= OEMs show systems with Intel MIC chips |author= Rick Merritt |date=20 June 2011 |work=EE Times}}
Initial developers included CERN, Korea Institute of Science and Technology Information (KISTI) and Leibniz Supercomputing Centre. Hardware vendors for prototype boards included IBM, SGI, HP, Dell and others.{{citation |url= http://www.linleygroup.com/newsletters/newsletter_detail.php?num=4729 |title= Intel Shows MIC Progress |date= 18 July 2011 |author= Tom R. Halfhill |work= linleygroup.com|publisher= The Linley Group}}
=Knights Corner=
The Knights Corner product line is made at a 22 nm process size, using Intel's Tri-gate technology with more than 50 cores per chip, and is Intel's first many-cores commercial product.{{citation |url= http://www.thinq.co.uk/2011/6/20/intel-pushes-hpc-space-knights-corner/ |title= Intel pushes for HPC space with Knights Corner |publisher= Net Communities Limited, UK |work= thinq.co.uk |date= 20 June 2011 |author= Gareth Halfacree}}
In June 2011, SGI announced a partnership with Intel to use the MIC architecture in its high-performance computing products.{{citation |url= http://news.techeye.net/hardware/sgi-wants-intel-for-super-supercomputer |title= SGI wants Intel for super supercomputer |date= 20 June 2011 |author= Andrea Petrou |work= news.techeye.net |url-status= dead |archive-url= https://web.archive.org/web/20110916013050/http://news.techeye.net/hardware/sgi-wants-intel-for-super-supercomputer |archive-date= 16 September 2011}} In September 2011, it was announced that the Texas Advanced Computing Center (TACC) will use Knights Corner cards in their 10-petaFLOPS "Stampede" supercomputer, providing 8 petaFLOPS of compute power.{{cite press release |url= http://www.tacc.utexas.edu/news/press-releases/2011/stampede |title= "Stampede's" Comprehensive Capabilities to Bolster U.S. Open Science Computational Resources |date= 22 September 2011 |publisher= Texas Advanced Computing Center |access-date= 23 September 2011 |archive-date= 5 August 2012 |archive-url= https://web.archive.org/web/20120805125957/http://www.tacc.utexas.edu/news/press-releases/2011/stampede |url-status= dead }} According to "Stampede: A Comprehensive Petascale Computing Environment" the "second-generation Intel (Knights Landing) MICs will be added when they become available, increasing Stampede's aggregate peak performance to at least 15 PetaFLOPS."{{cite web|url=http://www.ieeecluster.org/2011/images/program/Stampede_Abstracts.pdf|title=Stampede: A Comprehensive Petascale Computing Environment|work=IEEE Cluster 2011 Special Topic|access-date=16 November 2011|url-status=dead|archive-url=https://www.webcitation.org/6AyMCTibp?url=http://www.ieeecluster.org/2011/images/program/Stampede_Abstracts.pdf|archive-date=26 September 2012}}
On 15 November 2011, Intel showed an early silicon version of a Knights Corner processor.{{citation|url=https://www.tomshardware.com/news/intel-knights-corner-mic-co-processor,14002.html |title=Intel's Knights Corner: 50+ Core 22nm Co-processor|access-date=16 November 2011 |date=16 November 2011 |first= Marcus |last=Yam |work= tomshardware.com |publisher=Tom's Hardware}}{{citation|url=https://www.eetimes.com/electronics-news/4230654/Intel-unveils-1-TFLOP-s-Knight-s-Corner |title=Intel unveils 1 TFLOP/s Knights Corner|access-date=16 November 2011 |author= Sylvie Barak |date= 16 November 2011 |work=EE Times}}
On 5 June 2012, Intel released open source software and documentation regarding Knights Corner.{{citation|url=https://software.intel.com/en-us/blogs/2012/06/05/knights-corner-open-source-software-stack|title=Knights Corner: Open source software stack |publisher= Intel|author= James Reinders |date= 5 June 2012}}
On 18 June 2012, Intel announced at the 2012 Hamburg International Supercomputing Conference that Xeon Phi will be the brand name used for all products based on their Many Integrated Core architecture.{{cite news|url=https://newsroom.intel.com/community/intel_newsroom/blog/2012/06/18/intel-names-the-technology-to-revolutionize-the-future-of-hpc--intel-xeon-phi-product-family|title=Chip Shot: Intel Names the Technology to Revolutionize the Future of HPC - Intel Xeon Phi Product Family|date=18 June 2012|publisher=Intel|author=Radek|access-date=12 December 2012}}{{citation |url= https://www.theregister.co.uk/2012/06/18/intel_mic_xeon_phi_cray/ |title= Intel slaps Xeon Phi brand on MIC coprocessors |first= Timothy |last= Prickett Morgan |date= 18 June 2012 |work= 222.theregister.co.uk}}{{citation |url= http://www.marketwatch.com/story/latest-intelr-xeonr-processors-e5-product-family-achieves-fastest-adoption-of-new-technology-on-top500-list-2012-06-18 |title= Latest Intel Xeon Processors E5 Product Family Achieves Fastest Adoption of New Technology on Top500 List |date= 18 June 2012 |quote= Intel Xeon Phi is the new brand name for all future Intel Many Integrated Core Architecture based products targeted at HPC, enterprise, datacenters and workstations. The first Intel Xeon Phi product family member is scheduled for volume production by the end of 2012 |author= Intel Corporation |work= marketwatch.com |access-date= 18 June 2012 |archive-date= 20 June 2012 |archive-url= https://web.archive.org/web/20120620222352/http://www.marketwatch.com/story/latest-intelr-xeonr-processors-e5-product-family-achieves-fastest-adoption-of-new-technology-on-top500-list-2012-06-18 |url-status= dead }}{{cite news |title=Intel Xeon Phi coprocessors accelerate the pace of discovery and innovation |author=Raj Hazra |publisher=Intel |url=https://blogs.intel.com/technology/2012/06/intel-xeon-phi-coprocessors-accelerate-discovery-and-innovation/ |date=18 June 2012 |access-date=12 December 2012}}{{cite news |title=Cray will use Intel MIC, branded Xeon Phi |author=Rick Merritt |publisher=EETimes |url=https://www.eetimes.com/electronics-news/4375500/Cray-will-use-Intel-MIC--branded-Xeon-Phi |date=18 June 2012 |access-date=12 December 2012}}{{cite news |title=Intel christens its 'Many Integrated Core' products Xeon Phi, eyes exascale milestone |author=Terrence O'Brien |publisher=Engadget |url=https://www.engadget.com/2012/06/18/intel-christens-its-mic-products-xeon-phi/ |date=18 June 2012 |access-date=12 December 2012}}{{cite news |title=Intel Wraps Xeon Phi Branding Around MIC Coprocessors |author=Jeffrey Burt |publisher=eWeek |url=https://www.eweek.com/networking/intel-wraps-xeon-phi-branding-around-mic-coprocessors/ |date=18 June 2012 |access-date=7 March 2022}} In June 2012, Cray announced it would be offering 22 nm 'Knight's Corner' chips (branded as 'Xeon Phi') as a co-processor in its 'Cascade' systems.{{citation |url= https://www.eetimes.com/electronics-news/4375500/Cray-will-use-Intel-MIC--branded-Xeon-Phi |work= eetimes.com |title= Cray will use Intel MIC, branded Xeon Phi |first= Rick |last= Merritt |date= 8 June 2012}}{{citation |url= https://www.theinquirer.net/inquirer/news/2184891/cray-support-intels-xeon-phi-cascade-clusters |archive-url= https://web.archive.org/web/20120622064502/http://www.theinquirer.net/inquirer/news/2184891/cray-support-intels-xeon-phi-cascade-clusters |url-status= unfit |archive-date= 22 June 2012 |title= Cray to support Intel's Xeon Phi in Cascade clusters |first= Lawrence|last= Latif |date= 19 June 2012 |work= theinquirer.net}}
In June 2012, ScaleMP announced a virtualization update allowing Xeon Phi as a transparent processor extension, allowing legacy MMX/SSE code to run without code changes.{{cite press release |url= http://www.scalemp.com/scalemp-vsmp-foundation-to-support-intel-xeon-phi |title= ScaleMP vSMP Foundation to Support Intel Xeon Phi |publisher= ScaleMP |date= 20 June 2012 |archive-url=https://web.archive.org/web/20130520072517/http://www.scalemp.com/media-hub-item/scalemp-vsmp-foundation-to-support-intel-xeon-phi/ |archive-date=2013-05-20 |url-status=dead}}
An important component of the Intel Xeon Phi coprocessor's core is its vector processing unit (VPU).{{cite web|url=https://software.intel.com/en-us/articles/intel-xeon-phi-coprocessor-codename-knights-corner|title=Intel Xeon Phi X100 Family Coprocessor - the Architecture|author=George Chrysos|date=12 November 2012|website=software.intel.com}}
The VPU features a novel 512-bit SIMD instruction set, officially known as Intel Initial Many Core Instructions (Intel IMCI). Thus, the VPU can execute 16 single-precision (SP) or 8 double-precision (DP) operations per cycle. The VPU also supports Fused Multiply-Add (FMA) instructions and hence can execute 32 SP or 16 DP floating point operations per cycle. It also provides support for integers.
The VPU also features an Extended Math Unit (EMU) that can execute operations such as reciprocal, square root, and logarithm, thereby allowing these operations to be executed in a vector fashion with high bandwidth. The EMU operates by calculating polynomial approximations of these functions.
On 12 November 2012, Intel announced two Xeon Phi coprocessor families using the 22 nm process size: the Xeon Phi 3100 and the Xeon Phi 5110P.{{cite news|url=https://newsroom.intel.com/community/intel_newsroom/blog/2012/11/12/intel-delivers-new-architecture-for-discovery-with-intel-xeon-phi-coprocessors|title=Intel Delivers New Architecture for Discovery with Intel Xeon Phi Coprocessors|date=12 November 2012|publisher=Intel|author=IntelPR|access-date=12 December 2012}}{{cite magazine |title=Intel ships 60-core Xeon Phi processor |author=Agam Shah |magazine=Computerworld |url=https://www.computerworld.com/s/article/9233498/Intel_ships_60_core_Xeon_Phi_processor |date=12 November 2012 |access-date=12 December 2012 |archive-date=12 March 2013 |archive-url=https://web.archive.org/web/20130312145710/http://www.computerworld.com/s/article/9233498/Intel_ships_60_core_Xeon_Phi_processor |url-status=dead }}{{cite news |title=The Xeon Phi at work at TACC |author=Johan De Gelas |publisher=AnandTech |url=https://www.anandtech.com/show/6451/the-xeon-phi-at-work-at-tacc |date=14 November 2012 |access-date=12 December 2012}} The Xeon Phi 3100 will be capable of more than 1 teraFLOPS of double-precision floating-point instructions with 240 GB/s memory bandwidth at 300 W. The Xeon Phi 5110P will be capable of 1.01 teraFLOPS of double-precision floating-point instructions with 320 GB/s memory bandwidth at 225 W. The Xeon Phi 7120P will be capable of 1.2 teraFLOPS of double-precision floating-point instructions with 352 GB/s memory bandwidth at 300 W.
On 17 June 2013, the Tianhe-2 supercomputer was announced by TOP500 as the world's fastest. Tianhe-2 used Intel Ivy Bridge Xeon and Xeon Phi processors to achieve 33.86 petaFLOPS. It was the fastest on the list for two and a half years, lastly in November 2015.{{cite web
|title=Tianhe-2 (MilkyWay-2)
|publisher=Top500.org
|url=https://top500.org/system/177999
|date=14 November 2015 |access-date=6 May 2016}}
==Design and programming==
The cores of Knights Corner are based on a modified version of P54C design, used in the original Pentium.{{cite web |url=https://www.extremetech.com/extreme/133541-intels-64-core-champion-in-depth-on-xeon-phi |title=Intel's 50-core champion: In-depth on Xeon Phi |last1=Hruska |first1=Joel |date=30 July 2012 |work=ExtremeTech |publisher=Ziff Davis, Inc. |access-date=2 December 2012}} The basis of the Intel MIC architecture is to leverage x86 legacy by creating an x86-compatible multiprocessor architecture that can use existing parallelization software tools. Programming tools include OpenMP,{{cite conference |last1=Barker |first1=J |last2=Bowden |first2=J |year=2013 |title=Manycore Parallelism through OpenMP |conference=IWOMP |book-title=OpenMP in the Era of Low Power Devices and Accelerators |publisher=Springer |series=Lecture Notes in Computer Science, vol 8122|volume=8122 |pages=45–57 |doi=10.1007/978-3-642-40698-0_4 |isbn=978-3-642-40697-3 }} OpenCL,{{citation |url= https://www.eetimes.com/electronics-news/4217092/OEMs-show-systems-with-Intel-MIC-chips |title= OEMs show systems with Intel MIC chips |author= Rick Merritt |date= 20 June 2011 |work= EE Times}} Cilk/Cilk Plus and specialised versions of Intel's Fortran, C++{{citation |arxiv= 1211.5530|title= Efficient Hybrid Execution of C++ Applications using Intel Xeon Phi Coprocessor |date= 23 November 2012|bibcode= 2012arXiv1211.5530D|last1= Dokulil |first1= Jiri |last2= Bajrovic |first2= Enes |last3= Benkner |first3= Siegfried |last4= Pllana |first4= Sabri |last5= Sandrieser |first5= Martin |last6= Bachmayer |first6= Beverly }} and math libraries.{{citation|url=https://newsroom.intel.com/servlet/JiveServlet/download/2152-4-5220/ISC_Intel_MIC_factsheet.pdf |title=News Fact Sheet: Intel Many Integrated Core (Intel MIC) Architecture ISC'11 Demos and Performance Description |work=newsroom.intel.com |publisher=Intel |date=20 June 2011 |url-status=dead |archive-url=https://web.archive.org/web/20120324101552/https://newsroom.intel.com/servlet/JiveServlet/download/2152-4-5220/ISC_Intel_MIC_factsheet.pdf |archive-date=24 March 2012 }}
Design elements inherited from the Larrabee project include x86 ISA, 4-way SMT per core, 512-bit SIMD units, 32 KB L1 instruction cache, 32 KB L1 data cache, coherent L2 cache (512 KB per core[https://cug.org/proceedings/cug2013_proceedings/includes/files/pap199.pdf Tesla vs. Xeon Phi vs. Radeon. A Compiler Writer's Perspective] // The Portland Group (PGI), CUG 2013 Proceedings), and ultra-wide ring bus connecting processors and memory.
The Knights Corner 512-bit SIMD instructions share many intrinsic functions with AVX-512 extension . The instruction set documentation is available from Intel under the extension name of KNC.{{cite web|url=https://software.intel.com/en-us/forums/showthread.php?t=105443|title=Intel Many Integrated Core Architecture (Intel MIC Architecture) - RESOURCES (including downloads)|publisher=Intel|access-date=6 January 2014}}{{cite web|url=https://software.intel.com/sites/default/files/forum/278102/327364001en.pdf|title=Intel Xeon Phi Coprocessor Instruction Set Architecture Reference Manual|publisher=Intel|date=7 September 2012|access-date=6 January 2014}}{{cite web|url=https://software.intel.com/mic-developer|title=Intel Developer Zone: Intel Xeon Phi Coprocessor|publisher=Intel|access-date=6 January 2014|archive-url=https://web.archive.org/web/20140201085819/https://software.intel.com/mic-developer|archive-date=1 February 2014|url-status=dead}}{{Cite web|title=Intel® Intrinsics Guide|url=https://software.intel.com/sites/landingpage/IntrinsicsGuide/#techs=KNC|access-date=2020-08-04|website=software.intel.com}}
=Knights Landing=
File:Intel@14nm@Xeon Phi@Knights Landing@Xeon(ES)@QHL6 DSCx1.jpg]]
File:Intel@14nm@Xeon Phi@Knights Landing@Xeon(ES)@QHL6 DSCx3.jpg]]
File:Intel@14nm@Xeon Phi@Knights Landing@Xeon(ES)@QHL6 DSCx7@5x.jpg
Code name for the second-generation MIC architecture product from Intel. Intel officially first revealed details of its second-generation Intel Xeon Phi products on 17 June 2013. Intel said that the next generation of Intel MIC Architecture-based products will be available in two forms, as a coprocessor or a host processor (CPU), and be manufactured using Intel's 14 nm process technology. Knights Landing products will include integrated on-package memory for significantly higher memory bandwidth.
Knights Landing contains up to 72 Airmont (Atom) cores with four threads per core,{{cite web|url=https://wccftech.com/intel-xeon-phi-knights-landing-features-integrated-memory-500-gbs-bandwidth-ddr4-memory-support-architecture-detailed/|title=Intel Xeon Phi 'Knights Landing' Features Integrated Memory With 500 GB/s Bandwidth and DDR4 Memory Support - Architecture Detailed|work=WCCFtech|access-date=27 August 2015|date=2013-11-25}}{{citation |url=https://www.extremetech.com/extreme/171678-intel-unveils-72-core-x86-knights-landing-cpu-for-exascale-supercomputing |title=Intel unveils 72-core x86 Knights Landing CPU for exascale supercomputing |date=26 November 2013 |author=Sebastian Anthony |publisher= ExtremeTech}} using LGA 3647 socket[https://www.tomshardware.com/news/intel-xeon-phi-knights-landing,32121.html Tom's Hardware: Intel Xeon Phi Knights Landing Now Shipping; Omni Path Update, Too]. 20 June 2016 supporting up to 384 GB of "far" DDR4 2133 RAM and 8–16 GB of stacked "near" 3D MCDRAM, a version of the Hybrid Memory Cube. Each core has two 512-bit vector units and supports AVX-512 SIMD instructions, specifically the Intel AVX-512 Foundational Instructions (AVX-512F) with Intel AVX-512 Conflict Detection Instructions (AVX-512CD), Intel AVX-512 Exponential and Reciprocal Instructions (AVX-512ER), and Intel AVX-512 Prefetch Instructions (AVX-512PF). Support for IMCI has been removed in favor of AVX-512.{{citation |url=https://software.intel.com/en-us/blogs/2013/avx-512-instructions |title=AVX-512 Instructions |date=23 July 2013 |author=James Reinders |publisher= Intel}}
The National Energy Research Scientific Computing Center announced that Phase 2 of its newest supercomputing system "Cori" would use Knights Landing Xeon Phi coprocessors.{{cite web|url=https://www.nersc.gov/users/computational-systems/cori|title=Cori|website=www.nersc.gov|access-date=14 November 2018|archive-date=17 May 2019|archive-url=https://web.archive.org/web/20190517164940/https://www.nersc.gov/users/computational-systems/cori/|url-status=dead}}
On 20 June 2016, Intel launched the Intel Xeon Phi product family x200 based on the Knights Landing architecture, stressing its applicability to not just traditional simulation workloads, but also to machine learning.{{cite web|url=https://vimeo.com/intelpr/review/171590720/0bb679ec36|title=2016 ISC High Performance: Intel's Rajeeb Hazra Delivers Keynote Address|website=Vimeo}}{{cite web|url=https://software.intel.com/en-us/blogs/2016/06/20/how-xeon-phi-processors-benefit-machine-and-deep-learning-apps-frameworks|title=How Intel Xeon Phi Processors Benefit Machine Learning/Deep Learning Apps and Frameworks|author=Pradeep Dubey|date=20 June 2016|website=software.intel.com}} The model lineup announced at launch included only Xeon Phi of bootable form-factor, but two versions of it: standard processors and processors with integrated Intel Omni-Path architecture fabric.{{cite web |url=https://www.intel.com/content/www/us/en/processors/xeon/xeon-phi-detail.html |title=Introducing the Intel Xeon Phi Processor – Your Path to Deeper Insight |website=Intel |archive-url=https://web.archive.org/web/20170127023125/https://www.intel.com/content/www/us/en/processors/xeon/xeon-phi-detail.html |archive-date=27 January 2017 |url-status=dead}} The latter is denoted by the suffix F in the model number. Integrated fabric is expected to provide better latency at a lower cost than discrete high-performance network cards.
On 14 November 2016, the 48th list of TOP500 contained two systems using Knights Landing in the Top 10.{{Cite web|url=https://top500.org/lists/top500/2016/11/highlights/|title=Highlights - November 2016 | TOP500|website=top500.org}}
The PCIe based co-processor variant of Knight's Landing was never offered to the general market and was discontinued by August 2017.{{cite news|last1=Larabel|first1=Michael|title=Intel Quietly Drops Xeon Phi 7200 Coprocessors|url=https://www.phoronix.com/scan.php?page=news_item&px=No-More-Xeon-Phi-7200-Cards|access-date=25 August 2017|publisher=Phoronix|date=24 August 2017}} This included the 7220A, 7240P and 7220P coprocessor cards.
Intel announced they were discontinuing Knights Landing in summer 2018.{{cite web |url=https://qdms.intel.com/dm/i.aspx/9C54A9A7-BF37-4496-B268-BD2746EA54D3/PCN116378-00.pdf |title=Product Change Notification 116378 - 00 |access-date=25 July 2018 |website= Intel.com}}
==Models==
All models can boost to their peak speeds, adding 200 MHz to their base frequency when running just one or two cores. When running from three to the maximum number of cores, the chips can only boost 100 MHz above the base frequency. All chips run high-AVX code at a frequency reduced by 200 MHz.{{cite web|title=Intel Xeon Phi processor: Your Path to Deeper Insight|url=https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/xeon-phi-processor-product-brief.pdf|website=Intel.com|access-date=25 February 2017|archive-url=https://web.archive.org/web/20170226034124/https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/xeon-phi-processor-product-brief.pdf|archive-date=26 February 2017|url-status=dead}}
| class="wikitable sortable"
|+Models of Xeon Phi X200 Coprocessor Series ! rowspan="2" | Name ! rowspan="2" | Serial Code ! rowspan="2" | Cores ! colspan="2" | Clock (MHz) ! rowspan="2" | L2 ! colspan="2" | MCDRAM memory ! colspan="2" |DDR4 memory ! rowspan="2" | TDP ! rowspan="2" | Cooling ! rowspan="2" | Form factor ! rowspan="2" | Released |
| class="unsortable" | Base
! class="unsortable" | Turbo ! Quantity ! BW ! colspan="1" | Capacity !BW |
|---|
| Xeon Phi 7220A{{Cite web|url=https://www.cpu-world.com/CPUs/Xeon_Phi/Intel-Xeon%20Phi%207220A.html|title=Intel Xeon Phi 7220A - SC7220A / SC7220AEB}}
|SC7220A | rowspan="3" |68 (272) | rowspan="2" | 1200 | rowspan="2" | 1400 | rowspan="3" |34 MB | rowspan="3" |16 GB | rowspan="3" |400+ GB/s | rowspan="3" |384 GB | rowspan="3" |102.4 GB/s | rowspan="3" |275 |Active heatsink | rowspan="3" | PCIe 3.0 x16 card | rowspan="3" |??? |
| Xeon Phi 7220P{{Cite web|url=https://www.cpu-world.com/CPUs/Xeon_Phi/Intel-Xeon%20Phi%207220P.html|title=Intel Xeon Phi 7220P - SC7220P}}
|SC7220P | rowspan="2" |Passive heatsink |
| Xeon Phi 7240P{{Cite web|url=https://www.cpu-world.com/CPUs/Xeon_Phi/Intel-Xeon%20Phi%207240P.html|title=Intel Xeon Phi 7240P - SC7240P}}
|SC7240P | 1300 | 1500 |
=Knights Mill=
Knights Mill is Intel's codename for a Xeon Phi product specialized in deep learning,{{cite news|last1=Smith|first1=Ryan|title=Intel Announces Knight's Mill: A Xeon Phi for Deep Learning|url=https://www.anandtech.com/show/10575/intel-announces-knights-mill-a-xeon-phi-for-deep-learning|access-date=17 August 2016|publisher=Anandtech|date=17 August 2016}} initially released in December 2017.{{cite news|last1=Cutress|first1=Ian|title=Intel Lists Knights Mill Xeon Phi on ARK: Up to 72 cores at 320W with QFMA and VNNI|url=https://www.anandtech.com/show/12172/intel-lists-knights-mill-xeon-phi-on-ark-up-to-72-cores-at-320w-with-qfma-and-vnni|access-date=19 December 2017|publisher=Anandtech|date=19 December 2017}} Nearly identical in specifications to Knights Landing, Knights Mill includes optimizations for better utilization of AVX-512 instructions. Single-precision and variable-precision floating-point performance increased, at the expense of double-precision floating-point performance.
==Models==
| class="wikitable sortable"
|+Models of Xeon Phi X205 CPU Series ! rowspan="2" | Xeon Phi ! rowspan="2" | sSpec ! rowspan="2" | Cores ! colspan="2" | Clock (MHz) ! rowspan="2" | L2 ! colspan="2" | MCDRAM memory ! colspan="2" | DDR4 memory ! rowspan="2" | Peak DP ! rowspan="2" | TDP ! rowspan="2" class="unsortable" | Socket ! rowspan="2" class="unsortable" | Release date ! rowspan="2" |Part number |
| class="unsortable" | Base
! class="unsortable" | Turbo ! class="unsortable" | Quantity ! class="unsortable" | BW ! class="unsortable" | Capacity ! class="unsortable" | BW |
|---|
| Xeon Phi 7235
|SR3VF (A0) | 64 (256) | 1300 | 1400 | 32 MB | rowspan="4" | 16 GB | rowspan="4" | 400+ GB/s | rowspan="4" | 384 GB | 102.4 GB/s | {{TBA}} | 250 | rowspan="4" | SVLCLGA3647 | rowspan="4" | Q4 2017 |HJ8068303823900 |
| Xeon Phi 7255
|SR3VG (A0) | 68 (272) | 1100 | 1200 | 34 MB | 115.2 GB/s | {{TBA}} | 215 |HJ8068303826300 |
| Xeon Phi 7285
|SR3VE (A0) | 68 (272) | 1300 | 1400 | 34 MB | 115.2 GB/s | {{TBA}} | 250 |HJ8068303823800 |
| Xeon Phi 7295
|SR3VD (A0) | 72 (288) | 1500 | 1600 | 36 MB | 115.2 GB/s | {{TBA}} | 320 |HJ8068303823700 |
=Knights Hill=
Knights Hill was the codename for the third-generation MIC architecture, for which Intel announced the first details at SC14.SC14: Supercomputing '14; International Conference for High Performance Computing, Networking, Storage and Analysis in year 2014 It was to be manufactured in a 10 nm process.{{citation |author=Eric Gardner |title=What public disclosures has Intel made about Knights Landing? |date=25 November 2014 |url=https://software.intel.com/en-us/articles/what-disclosures-has-intel-made-about-knights-landing/ |publisher=Intel Corporation |archive-url=https://web.archive.org/web/20150223090350/https://software.intel.com/en-us/articles/what-disclosures-has-intel-made-about-knights-landing/ |archive-date=23 February 2015 |url-status=dead}}
Knights Hill was expected to be used in the United States Department of Energy Aurora supercomputer, to be deployed at Argonne National Laboratory.{{citation |author=ALCF staff |title=Introducing Aurora |date=9 April 2015 |url=https://www.alcf.anl.gov/articles/introducing-aurora}}{{citation |author=ALCF staff |title=Aurora |date=9 April 2015 |url=https://aurora.alcf.anl.gov/}} However, Aurora was delayed in favor of using an "advanced architecture" with a focus on machine learning.{{cite news |last1=Hemsoth |first1=Nicole |date=23 May 2017 |title=Some Surprises in the 2018 DoE Budget for Supercomputing |url=https://www.nextplatform.com/2017/05/23/surprises-2018-doe-budget-supercomputing/ |access-date=13 November 2017 |publisher=Next Platform}}{{cite news |last1=Brueckner |first1=Rich |date=16 June 2017 |title=Is Aurora Morphing into an Exascale AI Supercomputer? |url=https://insidehpc.com/2017/06/told-aurora-morphing-novel-architecture-ai-supercomputer/ |access-date=13 November 2017 |publisher=Inside HPC}}
In 2017, Intel announced that Knights Hill had been canceled in favor of another architecture built from the ground up to enable Exascale computing in the future. This new architecture was expected for 2020–2021;{{cite news |last1=Damkroger |first1=Trish |date=13 November 2017 |title=Unleashing high performance computing today and tomorrow |url=https://itpeernetwork.intel.com/unleashing-high-performance-computing/ |publisher=Intel IT Peer Network}}{{cite news |last1=Kampman |first1=Jeff |date=13 November 2017 |title=Intel quietly kills off next-gen Knights Hill Xeon Phi chips |url=https://techreport.com/news/32829/intel-quietly-kills-off-next-gen-knights-hill-xeon-phi-chips |access-date=13 November 2017 |publisher=Tech Report}} however, this was also cancelled due to the discontinuation of the Xeon Phi.
Programming
One performance and programmability study reported that achieving high performance with Xeon Phi still needs help from programmers and that merely relying on compilers with traditional programming models is insufficient.{{cite conference |last1=Fang |first1=Jianbin |last2=Sips |first2=Henk |last3=Zhang |first3=Lilun |last4=Xu |first4=Chuanfu |last5=Yonggang |first5=Che |last6=Varbanescu |first6=Ana Lucia |year=2014 |title=Test-Driving Intel Xeon Phi |url=https://research.spec.org/icpe_proceedings/2014/p137.pdf |conference=2014 ACM/SPEC International Conference on Performance Engineering |archive-url=https://web.archive.org/web/20171111044329/https://research.spec.org/icpe_proceedings/2014/p137.pdf |archive-date=11 November 2017 |access-date=30 December 2013 |url-status=dead}} Other studies in various domains, such as life sciences{{citation |arxiv= 1506.08612|title= Accelerating DNA Sequence Analysis using Intel Xeon Phi |date= 29 June 2015|bibcode= 2015arXiv150608612M|last1= Memeti |first1= Suejb |last2= Pllana |first2= Sabri |last3= Benkner |first3= Siegfried |last4= Pllana |first4= Sabri |last5= Sandrieser |first5= Martin |last6= Bachmayer |first6= Beverly }} and deep learning,{{citation |arxiv= 1506.09067|title= The Potential of the Intel Xeon Phi for Supervised Deep Learning |date= 30 June 2015|bibcode= 2015arXiv150609067V|last1= Viebke |first1= Andre |last2= Pllana |first2= Sabri |last3= Benkner |first3= Siegfried |last4= Pllana |first4= Sabri |last5= Sandrieser |first5= Martin |last6= Bachmayer |first6= Beverly }} have shown that exploiting the thread- and SIMD-parallelism of Xeon Phi achieves significant speed-ups.
Competitors
- Nvidia Tesla, a direct competitor in the HPC market{{cite web|url=https://arstechnica.com/business/news/2011/06/intel-takes-wraps-off-of-50-core-supercomputing-coprocessor-plans.ars|title=Intel takes wraps off 50-core supercomputing processor plans |author= Jon Stokes |date= 20 June 2011 |website= Ars Technica}}
- AMD Radeon Pro and AMD Radeon Instinct direct competitors in the HPC market
See also
- Texas Advanced Computing Center{{snd}} "Stampede" supercomputer incorporates Xeon Phi chips.{{cite news |title=Intel's Xeon Phi in 10 Petaflops supercomputer |author=Johan De Gelas |publisher=AnandTech |url=https://www.anandtech.com/show/6265/intels-xeon-phi-in-10-petaflops-supercomputer |date=11 September 2012 |access-date=12 December 2012}} Stampede is capable of 10 petaFLOPS.
- AVX-512
- Cell (microprocessor)
- Intel Tera-Scale
- Massively parallel
- Xeon
References
{{reflist}}
External links
{{commons category|Xeon Phi}}
- Intel pages: [https://www.intel.com/content/www/us/en/products/processors/xeon-phi/xeon-phi-processors.html Intel Xeon Phi Processors]
- Chips and Cheese, December 8, 2022, [https://chipsandcheese.com/2022/12/08/knights-landing-atom-with-avx-512/ Knight's Landing: Atom with AVX-512]
{{Intel processors}}
Category:Intel microprocessors