Zen 5

Zen 5 was first officially mentioned during AMD's Ryzen Processors: One Year Later presentation on April 9, 2018.{{cite web |title=Ryzen Processors: One Year Later |url=https://www.youtube.com/watch?v=iQ_4C2TKHQ0 |website=YouTube |language=en-US |date=April 9, 2018 |access-date=August 23, 2024}}

A roadmap shown during AMD's Financial Analyst Day on June 9, 2022 confirmed that Zen 5 and Zen 5c would be launching in 3nm and 4nm variants in 2024.{{cite web |title=AMD FAD 2022 AMD CPU Core Roadmap To Zen 5 |url=https://www.servethehome.com/amd-technology-roadmap-from-amd-financial-analyst-day-2022/amd-fad-2022-amd-cpu-core-roadmap-to-zen-5/ |website=ServeTheHome |language=en-US |access-date=June 3, 2024}} The earliest details on the Zen 5 architecture promised a "re-pipelined front end and wide issue" with "integrated AI and Machine Learning optimizations".

During AMD's Q4 2023 earnings call on January 30, 2024, AMD CEO Lisa Su stated that Zen 5 products would be "coming in the second half of the year".{{cite web |title=AMD reaffirms Ryzen CPUs with Zen5 architecture are coming in the second half of 2024 |url=https://videocardz.com/newz/amd-reaffirms-ryzen-cpus-with-zen5-architecture-are-coming-in-the-second-half-of-2024 |website=VideoCardz |language=en-US |date=January 31, 2024 |access-date=June 3, 2024}}

File:AMD@4nmCCD(6nmIOD)@Zen5@Granite Ridge@Ryzen 5 9600X@100-000001405 BY 2429SUY 9AEQ579S40073 DSCx14 CCD poly@5xExt.jpg

Zen 5 is a ground-up redesign of Zen 4 with a wider front-end, increased floating point throughput and more accurate branch prediction.{{cite web |last=Bonshor |first=Gavin |date=June 2, 2024 |title=AMD Unveils Ryzen 9000 CPUs For Desktop, Zen 5 Takes Center Stage at Computex 2024 |url=https://www.anandtech.com/show/21415/amd-unveils-ryzen-9000-cpus-for-desktop-zen-5-takes-center-stage-at-computex-2024 |website=AnandTech |language=en-US |access-date=June 3, 2024}}

Zen 5 was designed with both 4nm and 3nm processes in mind. This acted as an insurance policy for AMD in the event that TSMC's mass production of its N3 nodes were to face delays, significant wafer defect issues or capacity issues. One industry analyst estimated early N3 wafer yields to be at 55% while others estimated yields to be similar to those of N5 at between 60-80%.{{cite web |last=Norem |first=Josh |date=July 14, 2023 |title=Analyst: TSMC Hitting 55% Yields on 3nm Node for Apple's A17 Bionic, M3 SoCs |url=https://www.extremetech.com/computing/analyst-tsmc-hitting-55-yields-on-3nm-node-for-apples-a17-bionic-m3-socs |website=ExtremeTech |language=en-US |access-date=June 3, 2024}}{{cite web |last=Shilov |first=Anton |date=December 31, 2022 |title=Analysts Estimate TSMC's 3nm Yields Between 60% and 80% |url=https://www.tomshardware.com/news/analysts-estimate-tsmc-n3-yields-between-60-and-80-percent |website=Tom's Hardware |language=en-US |access-date=June 3, 2024}} Additionally, Apple, as TSMC's largest customer, is given priority access to the latest process nodes. In 2022, Apple was responsible for 23% of TSMC's $72 billion in total revenue.{{cite web |last=Norem |first=Josh |date=August 8, 2023 |title=Apple Bought All of TSMC's 3nm Capacity for an Entire Year |url=https://www.extremetech.com/computing/apple-bought-all-of-tsmcs-3nm-capacity-for-an-entire-year |website=ExtremeTech |language=en-US |access-date=June 3, 2024}} After N3 began ramping at the end of 2022, Apple bought up the entirety of TSMC's early N3B wafer production capacity to fabricate their A17 and M3 SoCs.{{cite web |last=Norem |first=Josh |date=April 27, 2023 |title=TSMC Says It Can't Keep Up With Apple's Demands for 3nm Wafers |url=https://www.extremetech.com/computing/tsmc-says-it-cant-keep-up-with-apples-demands-for-3nm-wafers |website=ExtremeTech |language=en-US |access-date=June 3, 2024}} Zen 5 desktop and server processors continue to use the N6 node for the I/O die fabrication.{{cite web |last=Bonshor |first=Gavin |date=2024-06-02 |title=AMD Unveils Ryzen 9000 CPUs For Desktop, Zen 5 Takes Center Stage at Computex 2024 |url=https://www.anandtech.com/show/21415/amd-unveils-ryzen-9000-cpus-for-desktop-zen-5-takes-center-stage-at-computex-2024 |url-status=live |archive-url=https://web.archive.org/web/20240603033848/https://www.anandtech.com/show/21415/amd-unveils-ryzen-9000-cpus-for-desktop-zen-5-takes-center-stage-at-computex-2024 |archive-date=2024-06-03 |access-date=2024-06-02 |work=AnandTech |language=en-US}}

Zen 5 CCDs are fabricated on TSMC's N4X node which is intended to accommodate higher frequencies for high-performance computing (HPC) applications.{{cite web |last=Norem |first=Josh |date=July 22, 2024 |title=AMD's Zen 5 Architectures Boast a 28% Increase in Density Over Zen 4 |url=https://www.extremetech.com/computing/amds-zen-5-architectures-boast-a-28-increase-in-density-over-zen-4 |website=ExtremeTech |language=en-US |access-date=September 16, 2024}} Zen 4-based mobile processors were fabricated on the N4P node which is targeted more towards power efficiency. N4X maintains IP compatibility with N4P and offers a 6% frequency gain over N4P at the same power but comes with the trade-off of moderate leakage.{{cite web |title=Advanced Technologies for HPC: N4/N4P/N4X |url=https://www.tsmc.com/english/dedicatedFoundry/technology/platform_HPC_tech_advancedTech |website=TSMC |language=en |access-date=June 3, 2024}} Compared to the N5 node used to produce Zen 4 CCDs, N4X can enable up to 15% higher frequencies while running at 1.2V.{{cite web |last=Shilov |first=Anton |date=December 17, 2021 |title=TSMC Unveils N4X Node: Extreme High-Performance at High Voltages |url=https://www.anandtech.com/show/17123/tsmc-unveils-n4x-node-high-voltages-for-high-clocks |website=AnandTech |language=en-US |access-date=June 3, 2024}}

The Zen 5 CCD, codenamed "Eldora", has a die size of 70.6mm², a 0.5% reduction in area from Zen 4's 71mm² CCD while achieving a 28% increase in transistor density due to the N4X process node.{{cite web |title=AMD Granite Ridge and Strix Point Zen 5 Die-sizes and Transistor Counts Confirmed |url=https://www.techpowerup.com/324562/amd-granite-ridge-and-strix-point-zen-5-die-sizes-and-transistor-counts-confirmed |website=TechPowerUp |language=en |date=July 16, 2024 |access-date=September 16, 2024}} Zen 5's CCD contains 8.315 billion transistors compared to the Zen 4 CCD's 6.5 billion transistors.{{cite web |last=Shilov |first=Anton |date=July 18, 2024 |title=AMD's Zen 5 chips pack in 8.315 billion transistors per compute die, a 28% increase in density |url=https://www.tomshardware.com/pc-components/cpus/amds-zen-5-chips-pack-in-8315-billion-transistors-per-compute-die-a-28-increase-in-density |website=Tom's Hardware |language=en-US |access-date=September 16, 2024}} The size of an individual Zen 5 core is actually larger than a Zen 4 core but the CCD has been reduced via shrinking the L3 cache. The monolithic die used by "Strix Point" mobile processors, fabricated on TSMC's lower power N4P node, measures 232.5mm² in area.

Zen 5's changes to branch prediction are the most significant divergence from any previous Zen microarchitecture. The branch predictor in a core tries to predict the outcome when there are diverging code paths.

Zen 5's branch predictor is able to operate two-ahead where it can predict up to two branches per clock cycle. Previous architectures were limited to one branch instruction per clock cycle, limiting the instruction fetch throughput of branch-heavy programs.{{cite web |last=Posch |first=Maya |date=July 28, 2024 |title=AMD Returns to 1996 With Zen 5's Two-Block Ahead Branch Predictor |url=https://hackaday.com/2024/07/28/amd-returns-to-1996-with-zen-5s-two-block-ahead-branch-predictor/ |website=Hackaday |language=en-US |access-date=September 16, 2024}} Two-ahead branch predictors have been discussed in academic research dating back to André Seznec et al.'s 1996 paper "Multiple-block ahead branch predictors".{{cite book |last1=Seznec |first1=André |last2=Jourdan |first2=Stéphan |last3=Sainrat |first3=Pascal |last4=Michaud |first4=Pierre |chapter=Multiple-block ahead branch predictors |year=1996 |title=Proceedings of the seventh international conference on Architectural support for programming languages and operating systems |chapter-url=https://dl.acm.org/doi/pdf/10.1145/237090.237169 |pages=116–127 |language=en-US |doi=10.1145/237090.237169|isbn=0-89791-767-7 }} 28 years after it was first proposed in academic research, AMD's Zen 5 architecture became the first microarchitecture to fully implement two-ahead branch prediction. Increased data prefetching assists the branch predictor.

Zen 5 contains 6 Arithmetic Logic Units (ALUs), up from 4 ALUs in prior Zen architectures. A greater number of ALUs that handle common integer operations can increase per-cycle scalar integer throughput by 50%.{{cite web |last=Lam |first=Chester |date=October 8, 2023 |title=Zen 5's Leaked Slides |url=https://chipsandcheese.com/2023/10/08/zen-5s-leaked-slides/ |website=Chips and Cheese |language=en-US |access-date=June 3, 2024}}

The vector engine in Zen 5 features 4 floating point pipes compared to 3 pipes in Zen 4. Zen 4 introduced AVX-512 instructions. AVX-512 capabilities have been expanded with Zen 5 with a doubling of the floating point pipe width to a native 512-bit floating point datapath. The AVX-512 datapath is configurable depending on the product. Ryzen 9000 series desktop processors and EPYC 9005 server processors feature the full 512-bit datapath but Ryzen AI 300 mobile processors feature a 256-bit datapath in order to reduce power consumption. AVX-512 instruction has been extended to VNNI/VEX instructions. Additionally, there is greater bfloat16 throughput which is beneficial for AI workloads.

The wider front end in the Zen 5 architecture necessitates larger caches and higher memory bandwidth in order to keep the cores fed with data. The L1 cache per core is increased from 64 KB to 80 KB per core. The L1 instruction cache remains the same at 32 KB but the L1 data cache is increased from 32 KB to 48 KB per core. Furthermore, the bandwidth of the L1 data cache for 512-bit floating point unit pipes has also been doubled. The L1 data cache's associativity has increased from 8-way to 12-way in order to accommodate its larger size.

The L2 cache remains at 1 MB but its associativity has increased from 8-way to 16-way. Zen 5 also has a doubled L2 cache bandwidth of 64 bytes per clock.

The L3 cache is filled from L2 cache victims and in-flight misses. Latency for accessing the L3 cache has been reduced by 3.5 cycles.{{cite web |last=Kennedy |first=Patrick |date=August 27, 2024 |title=AMD Zen 5 Core is at Hot Chips 2024 |url=https://www.servethehome.com/amd-zen-5-core-is-at-hot-chips-2024/ |website=ServeTheHome |language=en-US |access-date=September 16, 2024}} A Zen 5 Core Complex Die (CCD) contains 32 MB of L3 cache shared between the 8 cores. In Zen 5 3D V-Cache CCDs, a piece of silicon containing 64 MB of extra L3 cache is placed under the cores rather than on top like in prior generations for a total of 96 MB.{{cite news |last1=Lilly |first1=Paul |date=October 31, 2024 |title=AMD Ryzen 7 9800X3D Unveiled With A 3D V-Cache Tweak For Gamers And Overclockers |url=https://hothardware.com/news/amd-ryzen-7-9800x3d-kicks-off-zen-5-3d-v-cache-party |website=HotHardware |language=en-US |access-date=November 1, 2024}} This allows for increased core frequency compared to previous generation 3D V-Cache implementations which were sensitive to higher voltages. The Zen 5-based Ryzen 7 9800X3D has a 500 MHz increased base frequency over the Zen 4-based Ryzen 7 7800X3D and allows overclocking for the first time.{{cite news |last1=Tyson |first1=Mark |date=October 31, 2024 |title=AMD crowns the Ryzen 7 9800X3D a 'gaming legend' in a surprise announcement — chipmaker claims $479 Zen 5 3D V-Cache chip is up to an average 20% faster than Intel Core Ultra 9 flagship |url=https://www.tomshardware.com/pc-components/cpus/amd-crowns-the-ryzen-7-9800x3d-a-gaming-legend-in-a-surprise-announcement-chipmaker-claims-usd479-zen-5-3d-v-cache-chip-is-up-to-an-average-20-percent-faster-than-intel-core-ultra-9-flagship |website=Tom's Hardware |language=en-US |access-date=November 1, 2024}}

Ryzen AI 300 APUs, codenamed "Strix Point", features 24 MB of total L3 cache which is split into two separate cache arrays. 16 MB of dedicated L3 cache is shared the 4 Zen 5 cores and 8 MB is shared by the 8 Zen 5c cores.{{cite web |title=AMD's Strix Point: Zen 5 Hits Mobile |url=https://chipsandcheese.com/2024/08/10/amds-strix-point-zen-5-hits-mobile/ |website=Chips and Cheese |language=en-US |date=August 10, 2024 |access-date=September 16, 2024}} Zen 5c cores are not able to access the 16 MB L3 cache array and vice versa.{{cite web |title=AMD Strix Point SoC Reintroduces Dual-CCX CPU, Other Interesting Silicon Details Revealed |url=https://www.techpowerup.com/324872/amd-strix-point-soc-reintroduces-dual-ccx-cpu-other-interesting-silicon-details-revealed |website=TechPowerUp |language=en |date=July 24, 2024 |access-date=September 16, 2024}}

Other features and changes in the Zen 5 architecture, compared to Zen 4, include:

• Memory speeds up to DDR5-5600 (From DDR5-5200) and LPDDR5X-7500 are officially supported.{{Cite web |last=Bonshor |first=Gavin |title=AMD Unveils Ryzen 9000 CPUs For Desktop, Zen 5 Takes Center Stage at Computex 2024 |url=https://www.anandtech.com/show/21415/amd-unveils-ryzen-9000-cpus-for-desktop-zen-5-takes-center-stage-at-computex-2024 |access-date=2024-06-15 |website=www.anandtech.com}}

AMD announced an initial lineup of four models of Ryzen 9000 processors on June 3, 2024, including one Ryzen 5, one Ryzen 7 and two Ryzen 9 models. Manufactured on a 4 nm process, the processors feature between 6 and 16 cores.{{cite web |date=June 3, 2024 |title=AMD introduces Ryzen 9000 Zen5 desktop CPUs "Granite Ridge" |url=https://videocardz.com/newz/amd-introduces-ryzen-9000-zen5-desktop-cpus-granite-ridge |website=VideoCardz |language=en-US |access-date=June 3, 2024}} Ryzen 9000 processors were released in August 2024.

{{AMD Ryzen 9000 Series}}

AMD announced the Threadripper 9000 series of high-end desktop processors at Computex 2025, slated for release in July 2025. These processors succeed the Zen 4 "Storm Peak" lineup and feature up to 96 Zen 5 cores. The new processors come in two variants—the consumer "Threadripper" models and the more expensive workstation "Threadripper PRO" variants, which support more memory channels and PCIe lanes.{{cite web |date=May 20, 2025 |title=AMD Introduces New Radeon Graphics Cards and Ryzen Threadripper Processors at COMPUTEX 2025 |url=https://ir.amd.com/news-events/press-releases/detail/1253/amd-introduces-new-radeon-graphics-cards-and-ryzen-threadripper-processors-at-computex-2025 |language=en-US |access-date=May 22, 2025}}

Threadripper 9000 processors officially support up to 6400 MT/s DDR5 memory, a significant increase from 5200 MT/s in the previous generation.{{cite web |date=May 20, 2025 |title = AMD Ryzen™ Threadripper™ PRO 9995WX |url=https://www.amd.com/en/products/processors/workstations/ryzen-threadripper/9000-wx-series/amd-ryzen-threadripper-pro-9995wx.html |language=en-US |access-date=May 22, 2025}}

The Ryzen AI 300 series of high-performance ultrathin notebook processors were announced on June 3, 2024. Codenamed Strix Point, these processors are named under a new model numbering system similar to Intel's Core and Core Ultra model numbering. Strix Point features a 3rd gen Ryzen AI engine based on XDNA 2, providing up to 50 TOPS of neural processing unit performance. The integrated graphics is upgraded to RDNA 3.5, and top end models have 16 CUs of GPU and 12 cores of CPU, an increase from the maximum of 8 CPU cores on previous generation Ryzen ultrathin mobile processors.{{cite web |last1=Alcorn |first1=Paul |title=AMD unwraps Ryzen AI 300 series 'Strix Point' processors — 50 TOPS of AI performance, Zen 5c density cores come to Ryzen 9 for the first time |url=https://www.tomshardware.com/pc-components/cpus/amd-unwraps-ryzen-ai-300-series-strix-point-processors-50-tops-of-ai-performance-zen-5c-density-cores-come-to-ryzen-9-for-the-first-time |website=Tom's Hardware |access-date=3 June 2024 |language=en |date=3 June 2024}} Notebooks featuring Ryzen AI 300 series processors were released on July 17.{{cite web |last1=Shanto |first1=Abid Ahsan |title=Asus confirms delayed launch of AMD Ryzen AI 300 series laptops |url=https://www.notebookcheck.net/Asus-confirms-delayed-launch-of-AMD-Ryzen-AI-300-series-laptops.856408.0.html |website=NotebookCheck |access-date=4 July 2024 |date=3 July 2024}}

{{AMD Ryzen AI Mobile 300 series}}

Common features of Ryzen 9000 Fire Range series:

• Socket: FL1.
• All models support dual-channel DDR5-5600 with a maximum capacity of 96 GB.
• All models support 28 PCIe 5.0 lanes.
• Native USB 3.2 Gen 2 (10 Gbps): 4.
• Native USB 2.0 (480 Mbps): 1.
• iGPU: AMD Radeon 610M (2 CU @ 2200 MHz).
• No NPU.
• Fabrication process: TSMC N4 FinFET (CCD) + TSMC N6 FinFET (I/OD).

Alongside Granite Ridge desktop and Strix Point mobile processors, the Epyc 9005 series of high-performance server processors, codenamed Turin, were also announced at Computex on June 3, 2024. It uses the same SP5 socket as the previous Epyc 9004 series processors, and will pack up to 128 cores and 256 threads on the top-end model. Turin will be built on a TSMC 4 nm process.{{cite web |last1=Alcorn |first1=Paul |title=AMD announces 3nm EPYC Turin with 192 cores and 384 threads — 5.4X faster than Intel Xeon in AI work, launches second half of 2024 |url=https://www.tomshardware.com/pc-components/cpus/amd-announces-3nm-epyc-turin-launching-with-192-cores-and-384-threads-in-second-half-of-2024-54x-faster-than-intel-xeon-in-ai-workload |website=Tom's Hardware |access-date=3 June 2024 |language=en |date=3 June 2024}}

{{AMD EPYC 9000 Series}}

A variant of Epyc 9005 using Zen 5c ("Prometheus") cores was also shown off at Computex. It will feature a maximum of 192 cores and 384 threads, and be manufactured on a 3 nm process.

{{AMD EPYC Dense 9000 Series}}

Zen 5c ("Prometheus") is a compact variant of the Zen 5 ("Nirvana") core, primarily targeted at hyperscale cloud compute server customers.{{Cite web |last=Smith |first=Ryan |date=June 9, 2022 |title=AMD Zen Architecture Roadmap: Zen 5 in 2024 With All-New Microarchitecture |url=https://www.anandtech.com/show/17439/amd-zen-architecture-roadmap-zen-5-in-2024-with-allnew-microarchitecture |website=AnandTech |language=en-US |access-date=December 11, 2022}} It will succeed the Zen 4c ("Dionysus") and Zen 4 ("Persephone") core.

• Arrow Lake - a competing x86 CPU lineup from Intel

{{reflist}}

{{AMD processors}}

{{AMD processor roadmap}}

Category:AMD microarchitectures

Category:AMD x86 microprocessors

Category:X86 microarchitectures

Category:Computer-related introductions in 2024