transistor aging
{{Short description|Process of silicon transistors developing flaws over time as they are used}}
{{More footnotes needed|date=June 2020}}
Transistor aging (sometimes called silicon aging) is the process of silicon transistors developing flaws over time as they are used, degrading performance and reliability, and eventually failing altogether. Despite the name, similar mechanisms may affect transistors made of any kind of semiconductor. Manufacturers compensate for this (as well as manufacturing defects) by running chips at slower speeds than they are initially capable of (underclocking).
Causes
The main causes of transistor aging in MOSFETs are electromigration and charge trapping.
Electromigration is the movement of ions caused by momentum from the transfer of electrons in the conductor. This results in degradation of the material, causing intermittent glitches that are very difficult to diagnose, and eventual failure.
Charge trapping is related to time-dependent gate oxide breakdown, and manifests as an increase in resistance and threshold voltage (the voltage needed for the transistor to conduct), and a decrease in drain current. This degrades the chip performance over time, until ultimately the thresholds collapse. Charge trapping occurs in several ways:
- Hot carrier injection (HCI) is where electrons gain enough energy to leak into the oxide, becoming trapped there and possibly damaging it.
- Random telegraph noise (RTN) can also result, where the drain current fluctuates between several discrete levels, and is worsened with increasing temperature.
- Bias temperature instability (BTI) is where charge leaks into the oxide when voltage is applied to the gate, even with no current flowing through the transistor. When the voltage is removed from the gate, the charges gradually dissipate between milliseconds or hours.
Charge trapping was determined by John Szedon and Ting L. Chu to be a viable means of storing digital information, and was developed into the SONOS, MirrorBit, and 3D NAND flash memory technologies (charge trap flash).
See also
References
- {{cite magazine |title=Transistor Aging |date=25 Apr 2011 |first1=John |last1=Keane |first2=Chris H |last2=Kim |work=IEEE Spectrum |url=https://spectrum.ieee.org/transistor-aging |access-date=25 Jun 2024}}
- {{cite web |title=Silicon Aging and Signal Integrity |first=Alan |last=Sguigna |date=25 Aug 2013 |publisher=ASSET InterTech |url=https://blog.asset-intertech.com/test_data_out/2013/08/silicon-aging-and-signal-integrity.html |accessdate=25 Jun 2024}}
- {{cite web |title=Chip Aging Becomes Design Problem| url=https://semiengineering.com/chip-aging-becomes-design-problem/ |date=9 Aug 2018 |accessdate=19 Jul 2024 |first=Brian |last=Bailey |publisher=semiengineering.com}}
- {{cite web |title=Transistor Aging Intensifies At 10/7nm And Below |url=https://semiengineering.com/transistor-aging-intensifies-10nm/ |date=13 Jul 2017 |accessdate=19 Jul 2024 |first=Ann Steffora |last=Mutschler |publisher=semiengineering.com}}