SONOS

File:SONOS cell structure.svg drawing of a SONOS memory cell]]

A SONOS memory cell is formed from a standard polysilicon N-channel MOSFET transistor with the addition of a small sliver of silicon nitride inserted inside the transistor's gate oxide. The sliver of nitride is non-conductive but contains a large number of charge trapping sites able to hold an electrostatic charge. The nitride layer is electrically isolated from the surrounding transistor, although charges stored on the nitride directly affect the conductivity of the underlying transistor channel. The oxide/nitride sandwich typically consists of a 2 nm thick oxide lower layer, a 5 nm thick silicon nitride middle layer, and a 5–10 nm oxide upper layer.

When the polysilicon control gate is biased positively, electrons from the transistor source and drain regions tunnel through the oxide layer and get trapped in the silicon nitride. This results in an energy barrier between the drain and the source, raising the threshold voltage V_t (the gate-source voltage necessary for current to flow through the transistor). The electrons can be removed again by applying a negative bias on the control gate.

A SONOS memory array is constructed by fabricating a grid of SONOS transistors which are connected by horizontal and vertical control lines (wordlines and bitlines) to peripheral circuitry such as address decoders and sense amplifiers. After storing or erasing the cell, the controller can measure the state of the cell by passing a small voltage across the source-drain nodes; if current flows the cell must be in the "no trapped electrons" state, which is considered a logical "1". If no current is seen the cell must be in the "trapped electrons" state, which is considered as "0" state. The needed voltages are normally about 2 V for the erased state, and around 4.5 V for the programmed state.

Generally SONOS is very similar to traditional FG (floating gate) type memory cell,{{rp|117}}

but hypothetically offers higher quality storage. This is due to the smooth homogeneity of the Si₃N₄ film compared with polycrystalline film which has tiny irregularities. Flash requires the construction of a very high-performance insulating barrier on the gate leads of its transistors, often requiring as many as nine different steps, whereas the oxide layering in SONOS can be more easily produced on existing lines and more easily combined with CMOS logic.

Additionally, traditional flash is less tolerant of oxide defects{{Citation needed|reason=As is described in the History section, in 1980, Intel realized tolerant device with double layered polysilicon structure, which is much more tolerant than SONOS structure in that era.|date=March 2018}} because a single shorting defect will discharge the entire polysilicon floating gate. The nitride in the SONOS structure is non-conductive, so a short only disturbs a localized patch of charge. Even with the introduction of new insulator technologies this has a definite "lower limit" around 7 to 12 nm, which means it is difficult for flash devices to scale smaller than about 45 nm linewidths.

But, Intel-Micron group have realized 16 nm planar flash memory with traditional FG technology.{{rp|13}}

SONOS, on the other hand, requires a very thin layer of insulator in order to work, making the gate area smaller than flash. This allows SONOS to scale to smaller linewidth, with recent examples being produced on 40 nm fabs and claims that it will scale to 20 nm.[http://electroiq.com/blog/2006/09/samsung-unwraps-40nm-charge-trap-flash-device/ Samsung unwraps 40nm "charge trap flash" device] // ElectroIQ, 2006-09 The linewidth is directly related to the overall storage of the resulting device, and indirectly related to the cost; in theory, SONOS' better scalability will result in higher capacity devices at lower costs.

Additionally, the voltage needed to bias the gate during writing is much smaller than in traditional flash. In order to write flash, a high voltage is first built up in a separate circuit known as a charge pump, which increases the input voltage to between 9 V to 20 V. This process takes some time, meaning that writing to a flash cell is much slower than reading, often between 100 and 1000 times slower. The pulse of high power also degrades the cells slightly, meaning that flash devices can only be written to between 10,000 and 100,000 times, depending on the type. SONOS devices require much lower write voltages, typically 5–8 V, and do not degrade in the same way. SONOS does suffer from the converse problem however, where electrons become strongly trapped in the ONO layer and cannot be removed again. Over long usage this can eventually lead to enough trapped electrons to permanently set the cell to the "0" state, similar to the problems in flash. However,{{Citation needed|reason=Because 100 million is corrected to 100 thousands by citation, now it is comparable to legacy flash.|date=March 2018}} in SONOS this requires on the order of a 100 thousands write/erase cycles,{{cite book|last1=Wang|first1=S. Y.|last2=Lue|first2=H. T.|last3=Hsu|first3=T. H.|last4=Du|first4=P. Y.|last5=Lai|first5=S. C.|last6=Hsiao|first6=Y. H.|last7=Hong|first7=S. P.|last8=Wu|first8=M. T.|last9=Hsu|first9=F. H.|last10=Lian|first10=N. T.|last11=Lu|first11=C. P.|last12=Hsieh|first12=J. Y.|last13=Yang|first13=L. W.|last14=Yang|first14=T.|last15=Chen|first15=K. C.|last16=Hsieh|first16=K. Y.|last17=Lu|first17=C. Y.|title=2010 IEEE International Reliability Physics Symposium |chapter=A high-endurance (≫100K) BE-SONOS NAND flash with a robust nitrided tunnel oxide/Si interface |date=2010|pages=951–955|doi=10.1109/IRPS.2010.5488698|isbn=978-1-4244-5430-3|s2cid=23505564 }}

10 to 100 times worse compared with legacy FG memory cell.{{cite book|last1=Arai|first1=F.|last2=Maruyama|first2=T.|last3=Shirota|first3=R.|title=1998 IEEE International Reliability Physics Symposium Proceedings 36th Annual (Cat No 98CH36173) RELPHY-98 |chapter=Extended data retention process technology for highly reliable flash EEPROMs of 10/Sup 6/ To 10/Sup 7/ W/E cycles |date=1998|pages=378–382|doi=10.1109/RELPHY.1998.670672|isbn=0-7803-4400-6|s2cid=110355820 }}

{{See|Metal–nitride–oxide–semiconductor transistor}}

In 1957, Frosch and Derick were able to manufacture the first silicon dioxide field effect transistors at Bell Labs, the first transistors in which drain and source were adjacent at the surface.{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |pages=547 |doi=10.1149/1.2428650|url-access=subscription }} Subsequently, Dawon Kahng led a paper demonstrating a working MOSFET with their Bell Labs team in 1960. Their team included E. E. LaBate and E. I. Povilonis who fabricated the device; M. O. Thurston, L. A. D’Asaro, and J. R. Ligenza who developed the diffusion processes, and H. K. Gummel and R. Lindner who characterized the device.{{Cite journal |last=KAHNG |first=D. |date=1961 |title=Silicon-Silicon Dioxide Surface Device |url=https://doi.org/10.1142/9789814503464_0076 |journal=Technical Memorandum of Bell Laboratories |pages=583–596 |doi=10.1142/9789814503464_0076 |isbn=978-981-02-0209-5|url-access=subscription }}{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}

Later, Kahng went on to invent the floating-gate MOSFET with Simon Min Sze at Bell Labs, and they proposed its use as a floating-gate (FG) memory cell, in 1967.{{cite journal |last1=Kahng |first1=Dawon |author1-link=Dawon Kahng |last2=Sze |first2=Simon Min |author2-link=Simon Sze |title=A floating gate and its application to memory devices |journal=The Bell System Technical Journal |date=July{{ndash}}August 1967 |volume=46 |issue=6 |pages=1288–1295 |doi=10.1002/j.1538-7305.1967.tb01738.x|bibcode=1967ITED...14Q.629K }} This was the first form of non-volatile memory based on the injection and storage of charges in a floating-gate MOSFET,{{cite book |last1=Ioannou-Soufleridis |first1=V. |last2=Dimitrakis |first2=Panagiotis |last3=Normand |first3=Pascal |chapter=Chapter 3: Charge-Trap Memories with Ion Beam Modified ONO Stracks |title=Charge-Trapping Non-Volatile Memories: Volume 1 – Basic and Advanced Devices |date=2015 |publisher=Springer |isbn=9783319152905 |pages=65–102 (65) |chapter-url=https://books.google.com/books?id=7vFUCgAAQBAJ&pg=PA65}} which later became the basis for EPROM (erasable PROM), EEPROM (electrically erasable PROM) and flash memory technologies.{{cite news |title=Not just a flash in the pan |url=https://www.economist.com/technology-quarterly/2006/03/11/not-just-a-flash-in-the-pan |newspaper=The Economist |date=March 11, 2006 |accessdate=10 September 2019}}

Charge trapping at the time was an issue in MNOS transistors, but John Szedon and Ting L. Chu revealed in June 1967 that this difficulty could be harnessed to produce a nonvolatile memory cell. Subsequently, in late 1967, a Sperry research team led by H.A. Richard Wegener invented the metal–nitride–oxide–semiconductor transistor (MNOS transistor),{{cite conference|last1=Wegener|first1=H. A. R.|last2=Lincoln|first2=A. J.|last3=Pao|first3=H. C.|last4=O'Connell|first4=M. R.|last5=Oleksiak|first5=R. E.|last6=Lawrence|first6=H.|title=The variable threshold transistor, a new electrically-alterable, non-destructive read-only storage device|conference=1967 International Electron Devices Meeting|date=October 1967|volume=13|pages=70|doi=10.1109/IEDM.1967.187833}} a type of MOSFET in which the oxide layer is replaced by a double layer of nitride and oxide.{{cite book |last1=Brodie |first1=Ivor |last2=Muray |first2=Julius J. |title=The Physics of Microfabrication |date=2013 |publisher=Springer Science & Business Media |isbn=9781489921604 |page=74 |url=https://books.google.com/books?id=GQYHCAAAQBAJ&pg=PA74}} Nitride was used as a trapping layer instead of a floating gate, but its use was limited as it was considered inferior to a floating gate.{{cite book |last1=Prall |first1=Kirk |last2=Ramaswamy |first2=Nirmal |last3=Goda |first3=Akira |chapter=Chapter 2: A Synopsis on the State of the Art of NAND Memories |title=Charge-Trapping Non-Volatile Memories: Volume 1 – Basic and Advanced Devices |date=2015 |publisher=Springer |isbn=9783319152905 |pages=37–64 (39) |chapter-url=https://books.google.com/books?id=7vFUCgAAQBAJ&pg=PA39}} Charge trap (CT) memory was introduced with MNOS devices in the late 1960s. It had a device structure and operating principles similar to floating-gate (FG) memory, but the main difference is that the charges are stored in a conducting material (typically a doped polysilicon layer) in FG memory, whereas CT memory stored charges in localized traps within a dielectric layer (typically made of silicon nitride).

SONOS was first conceptualized in the 1960s. MONOS is realized in 1968 by Westinghouse Electric Corporation.

{{cite book|last1=Dummer|first1=G. W. A.|title=Electronic Inventions and Discoveries: Electronics from Its Earliest Beginnings to the Present Day (Google Books)|date=2013|publisher=Elsevier|isbn=9781483145211|url=https://books.google.com/books?id=PbYgBQAAQBAJ&dq=MONOS&pg=PA185|language=en}}

{{cite book|last1=Keshavan|first1=B. V.|title=1968 International Electron Devices Meeting|last2=Lin|first2=H. C.|chapter=MONOS memory element|date=October 1968|volume=14|pages=140–142|doi=10.1109/IEDM.1968.188066}}

In the early 1970s initial commercial devices were realized using PMOS transistors and a metal-nitride-oxide (MNOS) stack with a 45 nm nitride storage layer. These devices required up to 30V to operate.

In 1977, P.C.Y. Chen of Fairchild Camera and Instrument introduced a SONOS cross sectional structured MOSFET with tunnel silicon dioxide of 30 Ångström thickness for EEPROM.{{cite journal|last1=Chen|first1=P. C. Y.|title=Threshold-alterable Si-gate MOS devices|journal=IEEE Transactions on Electron Devices|date=1977|volume=24|issue=5|pages=584–586|doi=10.1109/T-ED.1977.18783|issn=0018-9383|bibcode=1977ITED...24..584C|s2cid=25586393 }}

According to NCR Corporation's patent application in 1980, SONOS structure required +25 volts and −25 volts for writing and erasing, respectively.

{{cite web|last1=TRUDEL|first1=L|last2=DHAM|first2=V|title=Application WO1981000790: Silicon gate non-volatile memory device|url=https://patents.google.com/patent/WO1981000790A1/en?q=SONOS|website=Google Patents|publisher=NCR Corporation|date=1980-09-11|quote=The initialization procedure (steps 1, 4 and 7), i.e. obtaining the initial written and erased state threshold voltages, involved applying +25 volts for three seconds and -25 volts for three seconds, respectively, at room temperature to the gates of the memory FETs. Source, drain and substrate were all tied to ground during this initialization.}}

It was improved to +12 V by PMOS-based MNOS (metal-nitride-oxide-semiconductor) structure.{{cite web|last1=TRUDEL|first1=MURRAY L|last2=LOCKWOOD|first2=GEORGE C|last3=EVANS|first3=EVANS G|title=Patent US4353083: Low voltage nonvolatile memory device|url=https://patents.google.com/patent/US4353083A/en?q=SONOS|website=Google Patents|publisher=NCR Corporation|date=1980-10-01}}

By the early 1980s, polysilicon NMOS-based structures were in use with operating voltages under 20 V. By the late 1980s and early 1990s PMOS SONOS structures

were demonstrating program/erase voltages in the range of 5–12 volts.{{Cite journal |doi = 10.1109/101.857747|title = On the go with SONOS|journal = IEEE Circuits and Devices Magazine|volume = 16|issue = 4|pages = 22–31|year = 2000|last1 = White|first1 = M.H.|last2 = Adams|first2 = D.A.|last3 = Bu|first3 = J.}} On the other hand, in 1980, Intel realized highly reliable EEPROM with double layered polysilicon structure, which is named FLOTOX,{{cite book|last1=Johnson|first1=W.|last2=Perlegos|first2=G.|last3=Renninger|first3=A.|last4=Kuhn|first4=G.|last5=Ranganath|first5=T.|title=1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |chapter=A 16Kb electrically erasable nonvolatile memory |date=1980|volume=XXIII|pages=152–153|doi=10.1109/ISSCC.1980.1156030|s2cid=44313709 }} both for erase and write cycling endurance and for data retention term.

{{cite book|last1=Euzent|first1=B.|title=19th International Reliability Physics Symposium|last2=Boruta|first2=N.|last3=Lee|first3=J.|last4=Jenq|first4=C.|chapter=Reliability Aspects of a Floating Gate E2 PROM|date=1981|pages=11–16|doi=10.1109/IRPS.1981.362965|s2cid=41116025 |quote=
The Intel 2816 uses the FLOTOX structure, which has been discussed in detail in the literaturel. Basically, it utilizes an oxide of less than 200A thick between the floating polysilicon gate and the N+ region as shown in Figure 1.}}

SONOS has been in the past produced by Philips Semiconductors, Spansion, Qimonda and Saifun Semiconductors.

In 2002, AMD and Fujitsu, formed as Spansion in 2003 and later merged with Cypress Semiconductor in 2014, developed a SONOS-like MirrorBit technology based on the license from Saifun Semiconductors, Ltd.'s NROM technology.{{cite web|title=AMD, FUJITSU AND SAIFUN ANNOUNCE COLLABORATION - News Room - FUJITSU|url=https://pr.fujitsu.com/en/news/2002/07/31-1.html|website=pr.fujitsu.com}}

{{cite web|last1=Vogler|first1=Debra|title=Spansion makes diversity play with SONOS-based MirrorBit technology {{!}} Solid State Technology|url=http://electroiq.com/blog/2007/11/spansion-makes-diversity-play-with-sonos-based-mirrorbit-technology/|website=electroiq.com|accessdate=23 March 2018|date=November 2007}}

{{cite web|title=Spansion Unveils Plans for SONOS-based MirrorBit(R) ORNAND(TM) Family|url=http://www.cypress.com/news/spansion-unveils-plans-sonos-based-mirrorbitr-ornandtm-family|website=www.cypress.com|publisher=Spansion Inc.}}

As of 2011 Cypress Semiconductor developed SONOS memories for multiple processes,

{{cite news|last1=Ramkumar|first1=Krishnaswamy|last2=Jin|first2=Bo|title=Advantages of SONOS memory for embedded flash technology|url=http://www.eetimes.com/document.asp?doc_id=1279116|publisher=EE Times|date=29 Sep 2011}}

and started to sell them as IP to embed in other devices.

[http://www.cypress.com/cypress-sonos-technology Cypress SONOS Technology]

UMC has already used SONOS since 2006 {{cite news|last1=LaPedus|first1=Mark|title=UMC fabs Sonos memory chip|url=http://www.eetimes.com/document.asp?doc_id=1160826|publisher=EE Times|date=19 Apr 2006}} and has licensed Cypress for 40 nm[http://investors.cypress.com/releasedetail.cfm?releaseid=892211 Cypress Press Release, 21 Jan 2015] and other nodes. Shanghai Huali Microelectronics Corporation (HLMC) has also announced{{cite news|title=HLMC and Cypress Announce Initial Production Milestone of Embedded Flash Using 55-Nanometer Low Power Process Technology with SONOS Flash|url=http://www.prnewswire.com/news-releases/hlmc-and-cypress-announce-initial-production-milestone-of-embedded-flash-using-55-nanometer-low-power-process-technology-with-sonos-flash-300437787.html|publisher=PRNewswire|date=12 Apr 2017}} to be producing Cypress SONOS at 40 nm and 55 nm.

In 2006, Toshiba developed a new double tunneling layer technology with SONOS structure, which utilize Si₉N₁₀ silicon nitride.

{{cite book|last1=Ohba|first1=R.|title=2006 International Electron Devices Meeting|last2=Mitani|first2=Y.|last3=Sugiyama|first3=N.|last4=Fujita|first4=S.|chapter=25 nm Planar Bulk SONOS-type Memory with Double Tunnel Junction|date=2006|pages=1–4|doi=10.1109/IEDM.2006.346945|isbn=1-4244-0438-X|s2cid=5676069 }}

{{cite web|last1=LaPedus|first1=Mark|title=Toshiba puts new twist on SONOS {{!}} EE Times|url=https://www.eetimes.com/document.asp?doc_id=1167609|website=EETimes|date=2007-12-12}}

Toshiba also researches MONOS ("Metal-Oxide-Nitride-Oxide-Silicon") structure for their 20 nm node NAND gate type flash memories.

{{cite book|last1=Sakamoto|first1=W.|title=2009 IEEE International Electron Devices Meeting (IEDM)|last2=Yaegashi|first2=T.|last3=Okamura|first3=T.|last4=Toba|first4=T.|last5=Komiya|first5=K.|last6=Sakuma|first6=K.|last7=Matsunaga|first7=Y.|last8=Ishibashi|first8=Y.|last9=Nagashima|first9=H.|last10=Sugi|first10=M.|last11=Kawada|first11=N.|last12=Umemura|first12=M.|last13=Kondo|first13=M.|last14=Izumida|first14=T.|last15=Aoki|first15=N.|last16=Watanabe|first16=T.|chapter=Reliability improvement in planar MONOS cell for 20nm-node multi-level NAND Flash memory and beyond|date=2009|pages=1–4|doi=10.1109/IEDM.2009.5424211|isbn=978-1-4244-5639-0|s2cid=29253924 }}

Renesas Electronics uses MONOS structure in 40 nm node era.

{{cite book|last1=Kono|first1=T.|title=2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers|last2=Ito|first2=T.|last3=Tsuruda|first3=T.|last4=Nishiyama|first4=T.|last5=Nagasawa|first5=T.|last6=Ogawa|first6=T.|last7=Kawashima|first7=Y.|last8=Hidaka|first8=H.|last9=Yamauchi|first9=T.|chapter=40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data|date=2013|pages=212–213|doi=10.1109/ISSCC.2013.6487704|isbn=978-1-4673-4516-3|s2cid=29355030 }}

{{cite journal|last1=Fischer|first1=T.|last2=Nam|first2=B. G.|last3=Chang|first3=L.|last4=Kuroda|first4=T.|last5=Pertijs|first5=M. A. P.|title=Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions|journal=IEEE Journal of Solid-State Circuits|date=2013|volume=49|issue=1|pages=4–8|doi=10.1109/JSSC.2013.2284658|issn=0018-9200|doi-access=free}}

{{rp|5}}

which is the result of collaboration with TSMC.

{{cite web|last1=Yoshida|first1=Junko|title=Renesas, TSMC tout licensable MCU platform using 40-nm eFlash {{!}} EE Times|url=https://www.eetimes.com/document.asp?doc_id=1264488|website=EETimes|date=2012-05-28}}

While other companies still use FG (floating gate) structure.

{{cite book|last1=Dimitrakis|first1=Panagiotis|title=Charge-Trapping Non-Volatile Memories: Volume 2--Emerging Materials and Structures (Google Books)|date=2017|publisher=Springer|isbn=9783319487052|url=https://books.google.com/books?id=LTcjDgAAQBAJ&dq=MONOS&pg=PA50|language=en}}

{{rp|50}}

For example, GlobalFoundries use floating-gate-based split-gate SuperFlash ESF3 cell for their 40 nm products.

{{cite book|last1=Luo|first1=L. Q.|title=2016 IEEE 8th International Memory Workshop (IMW)|last2=Teo|first2=Z. Q.|last3=Kong|first3=Y. J.|last4=Deng|first4=F. X.|last5=Liu|first5=J. Q.|last6=Zhang|first6=F.|last7=Cai|first7=X. S.|last8=Tan|first8=K. M.|last9=Lim|first9=K. Y.|last10=Khoo|first10=P.|last11=Jung|first11=S. M.|last12=Siah|first12=S. Y.|last13=Shum|first13=D.|last14=Wang|first14=C. M.|last15=Xing|first15=J. C.|last16=Liu|first16=G. Y.|last17=Diao|first17=Y.|last18=Lin|first18=G. M.|last19=Tee|first19=L.|last20=Lemke|first20=S. M.|last21=Ghazavi|first21=P.|last22=Liu|first22=X.|last23=Do|first23=N.|last24=Pey|first24=K. L.|last25=Shubhakar|first25=K.|chapter=Functionality Demonstration of a High-Density 2.5V Self-Aligned Split-Gate NVM Cell Embedded into 40nm CMOS Logic Process for Automotive Microcontrollers |date=May 2016|pages=1–4|doi=10.1109/IMW.2016.7495271|chapter-url=https://www.globalfoundries.com/sites/default/files/technicalpaper/tp-40nm_embedded_self-aligned_split-gate_flash_technology_for_high-density_automotive_microcontrollers.pdf|isbn=978-1-4673-8833-7|s2cid=36398631 }}

Some new structure for FG (floating gate) type flash memories are still intensively studied.

{{cite journal|last1=Zhou|first1=Ye|last2=Han|first2=Su-Ting|last3=Yan|first3=Yan|last4=Huang|first4=Long-Biao|last5=Zhou|first5=Li|last6=Huang|first6=Jing|last7=Roy|first7=V. A. L.|title=Solution processed molecular floating gate for flexible flash memories|journal=Scientific Reports|date=31 October 2013|volume=3|issue=1|pages=3093|doi=10.1038/srep03093|pmid=24172758|pmc=3813938|url=|publisher=Macmillan Publishers Limited|language=En|issn=2045-2322|bibcode=2013NatSR...3E3093Z}}

In 2016, GlobalFoundries developed FG-based 2.5V Embedded flash macro.

>{{cite book|last1=Luo|first1=L. Q.|title=2016 IEEE 8th International Memory Workshop (IMW)|last2=Teo|first2=Z. Q.|last3=Kong|first3=Y. J.|last4=Deng|first4=F. X.|last5=Liu|first5=J. Q.|last6=Zhang|first6=F.|last7=Cai|first7=X. S.|last8=Tan|first8=K. M.|last9=Lim|first9=K. Y.|last10=Khoo|first10=P.|last11=Jung|first11=S. M.|last12=Siah|first12=S. Y.|last13=Shum|first13=D.|last14=Wang|first14=C. M.|last15=Xing|first15=J. C.|last16=Liu|first16=G. Y.|last17=Diao|first17=Y.|last18=Lin|first18=G. M.|last19=Tee|first19=L.|last20=Lemke|first20=S. M.|last21=Ghazavi|first21=P.|last22=Liu|first22=X.|last23=Do|first23=N.|last24=Pey|first24=K. L.|last25=Shubhakar|first25=K.|chapter=Functionality Demonstration of a High-Density 2.5V Self-Aligned Split-Gate NVM Cell Embedded into 40nm CMOS Logic Process for Automotive Microcontrollers|date=May 2016|pages=1–4|doi=10.1109/IMW.2016.7495271|chapter-url=https://www.researchgate.net/publication/303566288|chapter-format=PDF|isbn=978-1-4673-8833-7|s2cid=36398631 }}

In 2017, Fujitsu announced to license FG-based ESF3/FLOTOX structure,

which is originally developed by Intel in 1980, from Silicon Storage Technology for their embedded non-volatile memory solutions.

{{cite web|title=Mie Fujitsu and SST Announce Automotive Platform Development on 40nm Technology : MIE FUJITSU SEMICONDUCTOR LIMITED|url=http://www.fujitsu.com/jp/group/mifs/en/resources/news/press-releases/2017/0807.html|website=www.fujitsu.com|language=en-uk|date=2017-08-07}}

{{cite web|title=Embedded Non-Volatile Memory Solutions : MIE FUJITSU SEMICONDUCTOR LIMITED|url=http://www.fujitsu.com/jp/group/mifs/en/services/tech/envm/|website=www.fujitsu.com|publisher=Fujitsu|language=en-uk}}

{{cite web|last1=Broome|first1=Sarah|title=Mie Fujitsu and SST Announce Automotive Platform Development on 40nm Technology|url=http://www.sst.com/about-sst/press-release/mie-fujitsu-and-sst-announce-automotive-platform-development-on-40nm-technology|website=www.sst.com|publisher=Silicon Storage Technology}}

As of 2016, Intel-Micron group have disclosed that they stayed traditional FG technology in their 3-dimensional NAND flash memory.{{cite web|title=NAND Flash Memory Roadmap|url=http://www.techinsights.com/techservices/TechInsights-NAND-Flash-Roadmap-2016.pdf|publisher=TechInsights Inc.|date=June 2016|access-date=2018-03-23|archive-date=2018-06-25|archive-url=https://web.archive.org/web/20180625075602/http://www.techinsights.com/techservices/TechInsights-NAND-Flash-Roadmap-2016.pdf|url-status=dead}}

They also use FG technology for 16 nm planar NAND flash.

{{cite web|last1=CHOE|first1=JEONGDONG|title=Deep dive into the Intel/Micron 3D 32L FG-NAND|url=http://www.techinsights.com/techinsights/about-techinsights/articles/deep-dive-into-the-intel-micron-3D-32L-FG-NAND/|website=www.techinsights.com}}

• Polycrystalline silicon
• Silicon dioxide
• Silicon nitride
• Silicon
• MOSFET
• Charge trap flash
• Floating-gate MOSFET
• EEPROM
• Flash memory

{{reflist}}

• {{cite journal |doi = 10.1109/T-ED.1977.18783|title = Threshold-alterable Si-gate MOS devices|journal = IEEE Transactions on Electron Devices|volume = 24|issue = 5|pages = 584–586|year = 1977|last1 = Chen|first1 = P.C.Y.|bibcode = 1977ITED...24..584C| s2cid=25586393 }}
• {{cite book |doi = 10.1109/NVMT.2004.1380804|chapter = Characterization of scaled SONOS EEPROM memory devices for space and military systems|title = Proceedings. 2004 IEEE Computational Systems Bioinformatics Conference|pages = 51–59|year = 2004|last1 = White|first1 = M.H.|last2 = Adams|first2 = D.A.|last3 = Murray|first3 = J.R.|last4 = Wrazien|first4 = S.|last5 = Yijie Zhao|last6 = Yu Wang|last7 = Khan|first7 = B.|last8 = Miller|first8 = W.|last9 = Mehrotra|first9 = R.|isbn = 0-7803-8726-0| s2cid=3034615 }}
• [http://static.usenix.org/legacy/events/sec01/full_papers/gutmann/gutmann_html/ Gutmann (2001) papaer: "Data Remanence in Semiconductor Devices" {{!}} USENIX]

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Category:Computer memory

Category:Non-volatile memory

Category:MOSFETs