z/Architecture#Vector facility
{{Short description|IBM's 64-bit instruction set architecture implemented by its mainframe computers}}
{{lowercase title}}
{{About|z/Architecture mode|z/Architecture in ESA/390 mode|ESA/390}}
{{Infobox CPU architecture
| name = z/Architecture
| designer = IBM
| bits = 64-bit
| introduced = {{Start date and age|2000}}
| version = ARCHLVL 2 and ARCHLVL 3 (2008)
| design = CISC
| type = Register–Register
Register–Memory
Memory–Memory
| encoding = Variable (2, 4 or 6 bytes long)
| branching = Condition code, indexing, counting
| endianness = Big
| extensions =
| open =
| predecessor = ESA/390
| gpr = 16× 64-bit
| fpr = 16× 64-bit (hexadecimal and IEEE binary; IEEE decimal starting with IBM System z9)
| vpr = 32× 128-bit, VR0–VR15 contain FPR0–FPR15
| registers = Access 16× 32, breaking-event-address register (BEAR) 64-bit, Control 16×64, Floating-Point Control 32-bit, Prefix 64-bit, PSW 128-bit }}
{{IBM mainframes}}
z/Architecture, initially and briefly called ESA Modal Extensions (ESAME), is IBM's 64-bit complex instruction set computer (CISC) instruction set architecture, implemented by its mainframe computers. IBM introduced its first z/Architecture-based system, the z900, in late 2000.{{cite journal |url=https://www.cl.cam.ac.uk/teaching/0607/CompArch/ibm-z-plambeck.pdf |title=Development and Attributes of z/Architecture |archive-url=https://web.archive.org/web/20131212140538/https://www.cl.cam.ac.uk/teaching/0607/CompArch/ibm-z-plambeck.pdf |archive-date=2013-12-12 |url-status=live |journal=IBM Journal of Research and Development |volume=45 |issue=4/5 |date=July–September 2002}} Subsequent z/Architecture systems include the IBM z800, z990, z890, System z9, System z10, zEnterprise 196, zEnterprise 114, zEC12, zBC12, z13, z14, z15, z16, and z17.
z/Architecture retains backward compatibility with previous 32-bit-data/31-bit-addressing architecture ESA/390 and its predecessors back to the 32-bit-data/24-bit-addressing System/360. The IBM z13 is the last z Systems server to support running an operating system in ESA/390 architecture mode.{{Cite web |url=https://www.ibm.com/support/knowledgecenter/en/SSLTBW_2.1.0/com.ibm.zos.v2r1.e0zm100/z132012hw1.htm |title=Accommodate functions for the z13 server to be discontinued on future servers |website=IBM |date=25 June 2015 |access-date=2017-09-18 |archive-date=2017-09-15 |archive-url=https://web.archive.org/web/20170915023438/https://www.ibm.com/support/knowledgecenter/en/SSLTBW_2.1.0/com.ibm.zos.v2r1.e0zm100/z132012hw1.htm |url-status=live }} However, all 24-bit and 31-bit problem-state application programs originally written to run on the ESA/390 architecture will be unaffected by this change.
Features
{{stub-section|date=June 2024}}
z/Architecture includes almost all{{efn|The ESA asynchronous-pageout, asynchronous-data-mover, program-call-fast, and ESA/390 vector facilities are not present in z/Architecture. The z/Architecture vector feature has been replaced by a very different vector facility starting with the z13.}} of the features of ESA/390, and adds some new features. Among the features{{efn|For a complete list see Chapter 1. Introduction in Principle of Operation.{{sfn|z|pp=1-2 – 1-7|loc=[https://www.vm.ibm.com/library/other/22783213.pdf#page=60 Highlights of Original z/Architecture]}}{{sfn|z|pp=1-7 – 1-31|loc=[https://www.vm.ibm.com/library/other/22783213.pdf#page=65 Additions to z/Architecture]}}}} of z/Architecture are
:A channel subsystem with the architecture introduced by S/370-XA
:Branch relative instructions introduced by ESA/390
:Trimodal (24/31/64-bit) addresses
:16 32-bit access registers (ARs) introduced by ESA/370
:16 64-bit general registers (GRs), 32-bit on older architectures
:16 64-bit control registers (CRs) introduced by System/370 as 32-bit
:16 64-bit floating-point registers (FPRs)
:32 128-bit vector registers (VRs); bits 0–63 of VR0–VR15 contain FPR0–FPR15
:1 32-bit floating-point control (FPC) register
:1 128-bit program-status word{{efn|Although the PSW in z is a quadword and in older architectures a double word, IBM has always used the nomenclature Program-Status Word for this register.}} (PSW), which includes a 64-bit instruction address
:An 8-KiB prefix storage area (PSA)
:Cryptographic Facility
:IEEE Binary-floating-point instructions added by ESA/390
:IEEE Decimal-floating-point instructions
For information on when each feature was introduced, consult the Principles of Operation.{{sfn|z|pp=1-2 – 1-7|loc=[https://www.vm.ibm.com/library/other/22783213.pdf#page=60 Highlights of Original z/Architecture]}}{{sfn|z|pp=1-7 – 1-31|loc=[https://www.vm.ibm.com/library/other/22783213.pdf#page=65 Additions to z/Architecture]}}
=Vector facility=
The z13 introduced the Vector Facility{{efn|Despite the similarity in name, Vector Facility for z/Architecture is not compatible with the Vector Facility on the 3090.}} for z/Architecture. It adds 32 vector registers, each 128 bits wide; the existing 16 floating-point registers are overlaid on the new vector registers. The new architecture adds over 150 new instructions to operate on data in vector registers, including integer, floating-point, and string data types. The z13 implementation includes two independent SIMD units to operate on vector data.{{cite web |url=https://www.ibm.com/developerworks/community/files/form/anonymous/api/library/ff4563be-756e-49bf-9de9-6a04a08026f1/document/3dff8d34-fcf9-4939-9efc-11f15a3ce0f8/media/IBM%2520z%2520Systems%2520Processor%2520Optimization%2520Primer.pdf |title=IBM z Systems Processor Optimization Primer|website=IBM }}
=Neural-network-processing-assist facility=
The z16 introduced the Neural-network-processing-assist facility,{{sfn|z|p=1-23|loc=[https://www.vm.ibm.com/library/other/22783213.pdf#page=83 Neural-Network-Processing-Assist Facility]}}{{sfn|z|pp=26-1 – 26-126|loc=[https://www.vm.ibm.com/library/other/22783213.pdf#page=1735 Chapter 26. Specialized-Function-Assist Instructions]}} which introduces several instructions performing operations on model-dependent data types. For the z16 this is the 16-bit NNP-Data-Type-1 Format.
The new instructions include tensor operations useful for AI and neural network applications.
Registers
{{stub-section|date=July 2024}}
| class="infobox" style="font-size:88%"
|+ align="center" | IBM z/Architecture registers |
| style="border-style: none;" |
{| class="wikitable" style="font-size:75%" |+ General Registers 0–15 |
| colspan=34 style="border-style: none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| colspan=32 | Two's complement value | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 0 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 31 | style="width:.5%; text-align:left; border-style: none none none none;" | |
| colspan=34 style="border-style: none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| colspan=32 | Two's complement value (continued) | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 32 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 63 | style="width:.5%; text-align:left; border-style: none none none none;" | |
|-
| style="border-style: none;" |
| class="wikitable" style="font-size:75%"
|+ Access Registers 0–15{{sfn|z|loc=[https://www.vm.ibm.com/library/other/22783213.pdf#page=354 Access-Register-Specified Address Spaces]|p=5-50}} |
| colspan=34 style="border-style: none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | P | colspan=8 | ALESN | colspan=16 | ALEN | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 0 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | 6 | style="width:1%; text-align:left; border-style: none none none none;" | 7 | style="width:1%; text-align:left; border-style: none none none none;" | 8 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | 15 | style="width:1%; text-align:left; border-style: none none none none;" | 16 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 31 | style="width:.5%; text-align:left; border-style: none none none none;" | |
| colspan="34" style="border-style: none;"|
{| class="wikitable mw-collapsible autocollapse" |+ {{nowrap|z/Architecture Access register abbreviations}} |
| style="width:10%; text-align:left;"| Bits
! style="width:10%; text-align:left;"| Field ! style="width:80%; text-align:left;"| Meaning |
|---|
| 0–6
| | 0000000 |
| 7
| P | Primary |
| 8–15
| ALESN | access-list-entry sequence number |
| 16–31
| ALEN | access-list-entry number |
|}
|-
| style="border-style: none;" |
| class="wikitable" style="font-size:75%" |
| colspan=34 style="border-style: none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| colspan=32 | See Principles of Operation{{sfn|z|loc=Breaking-Event-Address Register|p=[https://www.vm.ibm.com/library/other/22783213.pdf#page=246 4-46]}} | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 0 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 31 | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| colspan=32 | (continued) | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 32 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 63 | style="width:.5%; text-align:left; border-style: none none none none;" | |
|-
| style="border-style: none;" |
| class="wikitable" style="font-size:75%"
|+ Control Registers 0–15 |
| colspan=34 style="border-style: none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| colspan=32 | See Principles of Operation{{sfn|z|loc=[https://www.vm.ibm.com/library/other/22783213.pdfpage=209 Figure 4-5. Assignment of Control-Register Fields]|pp=4-9 – 4-11}} or Control Registers | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 0 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 31 | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| colspan=32 | (continued) | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 32 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 63 | style="width:.5%; text-align:left; border-style: none none none none;" | |
|-
| style="border-style: none;" |
| class="wikitable" style="font-size:75%"
|+ Floating-Point Registers (hexadecimal) 0–15 |
| colspan=34 style="border-style: none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| S | colspan=7 | Biased exponent | colspan=24 | Mantissa | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 0 | style="width:1%; text-align:left; border-style: none none none none;" | 1 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 7 | style="width:1%; text-align:left; border-style: none none none none;" | 8 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 31 | style="width:.5%; text-align:left; border-style: none none none none;" | |
| colspan=34 style="border-style: none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| colspan=32 | Mantissa (continued) | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 32 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 63 | style="width:.5%; text-align:left; border-style: none none none none;" | |
|-
| style="border-style: none;" |
| class="wikitable" style="font-size:75%"
|+ Floating-Point Registers (binary, single precision) 0–15 |
| colspan=34 style="border-style: none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| S | colspan=8 | Biased exponent | colspan=23 | Mantissa | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 0 | style="width:1%; text-align:left; border-style: none none none none;" | 1 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | 8 | style="width:1%; text-align:left; border-style: none none none none;" | 9 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 31 | style="width:.5%; text-align:left; border-style: none none none none;" | |
|-
| style="border-style: none;" |
| class="wikitable" style="font-size:75%"
|+ Floating-Point Registers (binary, double precision) 0–15 |
| colspan=34 style="border-style: none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| S | colspan=11 | Biased exponent | colspan=20 | Mantissa | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 0 | style="width:1%; text-align:left; border-style: none none none none;" | 1 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | 11 | style="width:1%; text-align:left; border-style: none none none none;" | 12 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 31 | style="width:.5%; text-align:left; border-style: none none none none;" | |
| colspan=34 style="border-style: none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| colspan=32 | Mantissa (continued) | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 32 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 63 | style="width:.5%; text-align:left; border-style: none none none none;" | |
|-
| style="border-style: none;" |
| class="wikitable" style="font-size:75%"
|+ Prefix register{{sfn|z|loc=[https://www.vm.ibm.com/library/other/22783213.pdf#page=128 Prefixing in the z/Architecture Architectural Mode]|pp=3-22–3-23}} |
| colspan=34 style="border-style: none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:left;" | 0 | style="width:.9%; text-align:right;" | 0 | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 0 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 31 | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:.9%; text-align:left;" | 0 | colspan="18" style="text-align:center" | Prefix Bits 33–50 | style="width:.9%; text-align:left;" | 0 | colspan="12" style="text-align:center" | n/a | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 32 | style="width:1%; text-align:left; border-style: none none none none;" | 33 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | 50 | style="width:1%; text-align:left; border-style: none none none none;" | 51 | style="width:1%; text-align:left; border-style: none none none none;" | 52 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 63 | style="width:.5%; text-align:left; border-style: none none none none;" | |
|-
|-
| style="border-style: none;" |
| class="wikitable" style="font-size:75%"
|+ z/Architecture long PSW{{sfn|z|loc=[https://publibfp.boulder.ibm.com/epubs/pdf/a227832c.pdf#page=199 Program-Status-Word Format]|pp=4-5 – 4-8}} |
| colspan=34 style="border-style: none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| 0 | R | style="border-style: solid none solid solid" | 0 | style="border-style: solid none solid | 0 | style="border-style: solid solid solid none" | 0 | T | I | E | colspan=4 | Key | 0 | M | W | P | colspan=2 | AS | colspan=2 | CC | colspan=4 | Program | R | style="border-style: solid none solid solid" | 0 | style="border-style: solid none solid | 0 | style="border-style: solid none solid | 0 | style="border-style: solid none solid | 0 | style="border-style: solid none solid | 0 | style="border-style: solid solid solid none" | 0 | E | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 0 | style="width:1%; text-align:left; border-style: none none none none;" | 1 | style="width:1%; text-align:left; border-style: none none none none;" | 2 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 4 | style="width:1%; text-align:keft; border-style: none none none none;" | 5 | style="width:1%; text-align:left; border-style: none none none none;" | 6 | style="width:1%; text-align:left; border-style: none none none none;" | 7 | style="width:1%; text-align:left; border-style: none none none none;" | 8 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 11 | style="width:1%; text-align:left; border-style: none none none none;" | 12 | style="width:1%; text-align:left; border-style: none none none none;" | 13 | style="width:1%; text-align:left; border-style: none none none none;" | 14 | style="width:1%; text-align:left; border-style: none none none none;" | 15 | style="width:1%; text-align:left; border-style: none none none none;" | 16 | style="width:1%; text-align:right; border-style: none none none none;" | 17 | style="width:1%; text-align:left; border-style: none none none none;" | 18 | style="width:1%; text-align:right; border-style: none none none none;" | 19 | style="width:1%; text-align:left; border-style: none none none none;" | 20 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 23 | style="width:1%; text-align:left; border-style: none none none none;" | 24 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 30 | style="width:1%; text-align:left; border-style: none none none none;" | 31 | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="border-style:none" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| B | colspan=31 | 0 | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 32 | style="width:1%; text-align:left; border-style: none none none none;" | 33 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 63 | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="border-style:none" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| colspan=32 | Instruction Address | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 64 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 95 | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="border-style:none" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| colspan=32 | Instruction Address (Continued) | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 96 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;' | 127 | style="width:.5%; text-align:left; border-style: none none none none;" | |
| colspan="34" style="border-style: none;"|
{| class="wikitable mw-collapsible autocollapse" |+ {{nowrap|Long PSW abbreviations}} |
| style="width:10%; text-align:left;"| Bits
! style="width:10%; text-align:left;"| Field ! style="width:80%; text-align:left;"| Meaning |
|---|
| 1
| R | PER Mask |
| 5
| T | DAT mode |
| 6
| IO | I/O mask |
| 7
| EX | External Mask |
| 8–11
| Key | PSW key |
| 12
| E=0 | Must be zero for LPSWE |
| 13
| M | Machine-check mask |
| 14
| W | Wait state |
| 15
| P | Problem state |
| 16–17
| AS | Address-Space Control |
| 18–19
| CC | Condition Code |
| 20–23
| PM | {| class="wikitable mw-collapsible autocollapse" |+ style="text-align: left;" | {{nowrap|Program Mask}} ! Bit ! Meaning |
| 20
| Fixed-point overflow |
| 21
| Decimal overflow |
| 22
| HFP Exponent underflow |
| 23
| HFP Significance |
|-
| 24
| RI
| Reserved for IBM
|-
| 31
| EA
| Extended Addressing mode
0=defined by BA below; 1=64-bit, BA must be zero
|-
| 32
| BA
| Basic Addressing mode
0=24 or 64; 1=31
|-
| 64–127
| IA
| Instruction Address
|}
|}
|-
| style="border-style: none;" |
|-
| style="border-style: none;" |
| class="wikitable" style="font-size:75%"
|+ z/Architecture short PSW{{sfn|z|loc=[https://publibfp.boulder.ibm.com/epubs/pdf/a227832c.pdf#p=202 Short PSW Format]|p=4-8}} |
| colspan=34 style="border-style: none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| 0 | R | style="border-style: solid none solid solid" | 0 | style="border-style: solid none solid | 0 | style="border-style: solid solid solid none" | 0 | T | I | E | colspan=4 | Key | 1 | M | W | P | colspan=2 | AS | colspan=2 | CC | colspan=4 | Program | R | style="border-style: solid none solid solid;" | 0 | style="border-style: solid none solid;" | 0 | style="border-style: solid none solid;" | 0 | style="border-style: solid none solid;" | 0 | style="border-style: solid none solid;" | 0 | style="border-style: solid solid solid none;" | 0 | E | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 0 | style="width:1%; text-align:left; border-style: none none none none;" | 1 | style="width:1%; text-align:left; border-style: none none none none;" | 2 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 4 | style="width:1%; text-align:left; border-style: none none none none;" | 5 | style="width:1%; text-align:left; border-style: none none none none;" | 6 | style="width:1%; text-align:left; border-style: none none none none;" | 7 | style="width:1%; text-align:left; border-style: none none none none;" | 8 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 11 | style="width:1%; text-align:left; border-style: none none none none;" | 12 | style="width:1%; text-align:left; border-style: none none none none;" | 13 | style="width:1%; text-align:left; border-style: none none none none;" | 14 | style="width:1%; text-align:left; border-style: none none none none;" | 15 | style="width:1%; text-align:left; border-style: none none none none;" | 16 | style="width:1%; text-align:right; border-style: none none none none;" | 17 | style="width:1%; text-align:left; border-style: none none none none;" | 18 | style="width:1%; text-align:right; border-style: none none none none;" | 19 | style="width:1%; text-align:left; border-style: none none none none;" | 20 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 23 | style="width:1%; text-align:left; border-style: none none none none;" | 24 | style="width:1%; text-align:left; border-style: none none none none;" | 25 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:right; border-style: none none none none;" | 30 | style="width:1%; text-align:left; border-style: none none none none;" | 31 | style="width:.5%; text-align:left; border-style: none none none none;" | |
| style="border-style:none;" | |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| B | colspan=31 | Instruction Address |
| style="width:.5%; text-align:left; border-style: none none none none;" |
| style="width:1%; text-align:left; border-style: none none none none;" | 32 | style="width:1%; text-align:left; border-style: none none none none;" | 33 | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | | style="width:1%; text-align:left; border-style: none none none none;" | 63 | style="width:.5%; text-align:left; border-style: none none none none;" | |
| colspan="34" style="border-style: none;"|
{| class="wikitable mw-collapsible autocollapse" |+ {{nowrap|Short PSW abbreviations}} |
| style="width:10%; text-align:left;"| Bits
! style="width:10%; text-align:left;"| Field ! style="width:80%; text-align:left;"| Meaning |
|---|
| 1
| R | PER Mask |
| 5
| T | DAT mode |
| 6
| IO | I/O mask |
| 7
| EX | External Mask |
| 8–11
| Key | PSW key |
| 12
| E=1 | Must be one for LPSW |
| 13
| M | Machine-check mask |
| 14
| W | Wait state |
| 15
| P | Problem state |
| 16–17
| AS | Address-Space Control |
| 18–19
| CC | Condition Code |
| 20–23
| PM | {| class="wikitable mw-collapsible autocollapse" |+ style="text-align: left;" | {{nowrap|Program Mask}} ! Bit ! Meaning |
| 20
| Fixed-point overflow |
| 21
| Decimal overflow |
| 22
| HFP Exponent underflow |
| 23
| HFP Significance |
|-
| 24
| RI
| Reserved for IBM
|-
| 31
| EA
| Extended Addressing mode
0=defined by BA below; 1=64-bit, BA must be zero
|-
| 32
| BA
| Basic Addressing mode
0=24 or 64; 1=31
|-
| 33–63
| IA
| Instruction Address
|}
|}
|}
Each processor has these registers
=Access registers=
Each CPU has 16 32-bit access registers.{{sfn|z|loc=[https://www.vm.ibm.com/library/other/22783213.pdf#page=354 Access-Register-Specified Address Spaces]|p=5-50}}{{sfn|z|loc=[https://www.vm.ibm.com/library/other/22783213.pdf#page=104 Access Registers]|pp=6-15 – 6-16}} When a program running in AR mode specifies register 1–15 as a base register or as a register operand containing an address, the CPU uses the associated access register during address translation.
=Breaking-event-address register (BEAR)=
The 64-bit BEAR{{sfn|z|loc=Breaking-Event-Address Register|p=[https://www.vm.ibm.com/library/other/22783213.pdf#page=246 4-46]}}{{sfn|z|loc=Breaking-Event-Address Register|p=4-46[https://www.vm.ibm.com/library/other/22783213.pdf#page=246 4-46]}} contains the address of the last instruction that broke the sequential execution of instructions; an interrupt stores the BEAR in the doubleword at real address 272 ({{hexadecimal|272}}). After an Execute of a branch, the BEAR contains the address of the execute, not that of the branch.
=Control registers=
The 16 64-bit control registers provide controls over and the status of a CPU, except for information included in the PSW. They are an evolutionary enhancement to the control registers on the earlier ESA/390 on the IBM S/390 processors. For details on which fields are dependent on specific features, consult the Principles of Operation.{{sfn
| z
| pp = [https://www.vm.ibm.com/library/other/22783213.pdf#page=209 4-9–4-12]
| loc = Control Registers
}}
Because z/Architecture expands the control registers from 32 bits to 64, the bit numbering differs from that in ESA/390.
| class="wikitable"
|+ z/Architecture mode control registers ! CR !! bits !! Field |
| id="z/Architecture CR0"
| 0 | 8 | Transactional-execution control |
| 0
| 9 | Transactional-execution program-interruption filtering override |
| 0
| 10 | Clock-comparator sign control |
| 0
| 13 | Cryptography counter control |
| 0
| 14 | Processor-activity-instrumentation-extension control |
| 0
| 15 | Measurement-counter-extraction-authorization control |
| 0
| 30 | Warning-track subclass mask |
| 0
| 32 | TRACE TOD-clock control |
| 0
| 33 | SSM-suppression |
| 0
| 34 | TOD-clock-sync control |
| 0
| 35 | Low-address-protection control |
| 0
| 36 | Extraction-authority control |
| 0
| 37 | Secondary-space control |
| 0
| 38 | Fetch-protection-override control |
| 0
| 39 | Storage-protection-override control |
| 0
| 40 | Enhanced-DAT-enablement control |
| 0
| 43 | Instruction-execution-protection-enablement control |
| 0
| 44 | ASN-and-LX-reuse control |
| 0
| 45 | AFP-register control |
| 0
| 46 | Vector enablement control |
| 0
| 48 | Malfunction-alert subclass mask |
| 0
| 48 | Malfunction-alert subclass mask |
| 0
| 49 | Emergency-signal subclass mask |
| 0
| 50 | External-call subclass mask |
| 0
| 52 | Clock-comparator subclass mask |
| | 0
| 53 | CPU-timer subclass mask |
| 0
| 54 | Service-signal subclass mask |
| 0
| 56 | Initialized to 1 |
| 0
| 57 | Interrupt-key subclass mask |
| 0
| 58 | Measurement-alert subclass mask |
| 0
| 59 | Timing-alert subclass mask |
| 0
| 61 | Crypto control |
| id="z/Architecture CR1"
| 1 | 0–51 | Primary Address-Space Control Element (ASCE) |
| 1
| 54 | Primary subspace-group control |
| 1
| 55 | Primary private-space control |
| 1
| 56 | Primary storage-alteration-event |
| 1
| 57 | Primary space-switch-event control |
| 1
| 58 | Primary real-space control |
| 1
| 60–61 | Primary designation-type control |
| 1
| 62–63 | Primary table length |
| id="z/Architecture CR2"
| 2 | 33–57 | Dispatchable-unit-control-table origin |
| 2
| 59 | Guarded-storage-facility enablement control |
| 2
| 61 | Transaction diagnostic scope |
| 2
| 62–63 | Transaction diagnostic control |
| id="z/Architecture CR3"
| 3 | 0–31 | Secondary ASN-second-table-entry instance number |
| 3
| 32–47 | PSW-key mask |
| 3
| 48–63 | Secondary ASN |
| id="z/Architecture CR4"
| 4 | 0–31 | Primary ASN-second-table-entry instance number |
| 4
| 32–47 | Authorization index |
| id="z/Architecture CR4"
| 4 | 48–63 | Primary ASN |
| id="z/Architecture CR5"
| 5 | 33–57 | Primary-ASN-second-table-entry origin |
| id="z/Architecture CR6"
| 6 | 32–39 | I/O-interruption subclass mask |
| id="z/Architecture CR7"
| 7 | 0–51 | Secondary Address-Space Control Element (ASCE) |
| 7
| 54 | Secondary subspace-group control |
| 7
| 55 | Secondary private-space control |
| 7
| 56 | Secondary storage-alteration-event control |
| 7
| 58 | Secondary real-space control |
| 7
| 60–61 | Secondary designation-type control |
| 7
| 62–63 | Secondary table length |
| id="z/Architecture CR8"
| 8 | 16–31 | Enhanced-monitor masks |
| 8
| 32–47 | Extended authorization index |
| 8
| 48–63 | Monitor masks |
| id="z/Architecture CR9"
| 9 | 32 | Successful-branching-event mask |
| 9
| 33 | Instruction-fetching-event mask |
| 9
| 34 | Storage-alteration-event mask |
| 9
| 35 | Storage-key-alteration-event mask |
| 9
| 36 | Store-using-real-address-event mask |
| 9
| 37 | Zero-address-detection-event mask |
| 9
| 38 | Transaction-end event mask |
| 9
| 39 | Instruction-fetching-nullification-event mask |
| 9
| 40 | Branch-address control |
| 9
| 41 | PER-event-suppression control |
| 9
| 43 | Storage-alteration-space control |
| id="z/Architecture CR10"
| 10 | 0–63 | PER starting address |
| id="z/Architecture CR11"
| 11 | 0–63 | PER ending address |
| id="z/Architecture CR12"
| 12 | 0 | Branch-trace control |
| 12
| 1 | Mode-trace control |
| 12
| 2–61 | Trace-entry address |
| 12
| 62 | ASN-trace control |
| 12
| 63 | Explicit-trace control |
| id="z/Architecture CR13"
| 13 | 0–51 | Home Address-Space Control Element (ASCE) |
| 13
| 55 | Home private-space control |
| 13
| 56 | Home storage-alteration-eventl |
| 13
| 57 | Home space-switch-event control |
| 13
| 58 | Secondary real-space control |
| 13
| 60–61 | Home designation-type control |
| 13
| 62–63 | Home table length |
| id="z/Architecture CR14"
| 14 | 32 | Set to 1 |
| 14
| 33 | Set to 1 |
| 14
| 34 | Extended save-area control (ESA/390-compatibility mode only) |
| 14
| 35 |Channel-report-pending subclass mask |
| 14
| 36 | Recovery subclass mask |
| 14
| 37 | Degradation subclass mask |
| 14
| 38 | External-damage subclass mask |
| 14
| 39 | Warning subclass mask |
| 14
| 42 | TOD-clock-control-override control |
| 14
| 44 | ASN-translation control |
| 14
| 45–63 | ASN-first-table origin |
| id="z/Architecture CR15"
| 15 | 0–60 | Linkage-stack-entry address |
=Floating-point Control (FPC) register=
The FPC register contains Interrupt Masks (IM), Status Flags (SF), Data Exception Code (DXC), Decimal Rounding Mode (DRM) and Binary Rounding Mode (BRM). An interruption only stores the DXC if the FPC register if the AFP-register (additional floating-point register) control bit, bit 13 of control register 0, is one. Also, while individual bits of the DXC usually have significance, programs should normally treat it as an 8-bit integer rather than querying individual bits.
| class=wikitable
|+ FPC fields |
| Byte name
! Bits ! Field name ! Use |
|---|
| masks
| 0 | IMi | IEEE-invalid-operation mask |
| masks
| 1 | IMz | IEEE-division-by-zero mask |
| masks
| 2 | IMo | IEEE-overflow mask |
| masks
| 3 | IMu | IEEE-underflow mask |
| masks
| 4 | IMx | IEEE-inexact mask |
| masks
| 5 | IMq | Quantum-exception mask |
| flags
| 8 | SFi | IEEE-invalid-operation flag |
| flags
| 9 | SFz | IEEE-division-by-zero |
| flags
| 10 | SFo | IEEE-overflow flag |
| flags
| 11 | SFu | IEEE-underflow flag |
| flags
| 12 | SFx | IEEE-inexact flag |
| flags
| 13 | SFq | Quantum-exception flag |
| DXC
| 16–23 | DXC | Data-exception code |
| DXC
| 16 | i | IEEE-invalid-operation |
| DXC
| 17 | z | IEEE-division-by-zero |
| DXC
| 18 | o | IEEE-overflow |
| DXC
| 19 | u | IEEE-underflow mask |
| DXC
| 20 | x | IEEE-inexact mask |
| DXC
| 21 | y/q | Quantum-exception mask |
| | 25–27
| DRM | DFP rounding mode |
| | 29–31
| BRM | BFP rounding mode |
=Floating-point registers=
Each CPU had 16 64-bit floating-point registers; FP0–15 occupy bits 0–63 of VR0–15.
=General registers=
Each CPU has 16 64-bit general registers, which serve as accumulators, base registers{{efn|Except for general register 0.|name=notzero}} and index registers.{{efn|name=notzero}} Instructions designated as Grandé operate on all 64 bits; some instructions added by the Extended-Immediate Facility operate on any halfword or word in the register; most other instructions do not change or use bits 0–31.
=Prefix register=
The prefix register is used in translating a real address to an absolute address. In z/Architecture mode, the PSA is 2 pages (8 KiB). Bits 0–32 and 51–63 are always zero. If bits 0–50 of a real address are zero then they are replaced by bits 0–50 of the prefix register; if bits 0–50 of the real address are equal to bits 0–50 of the prefix register then they are replaced with zeros.
=Program status word (PSW)=
The PSW holds the instruction address and other fields reflecting the status of the program currently running on a CPU. The status of the program is also affected by the contents of the Control registers.
=Vector registers=
Each CPU has 32 128-bit vector registers;{{sfn|z|loc=[https://www.vm.ibm.com/library/other/22783213.pdf#page=103 Vector Registers]|pp=2-5 – 2-6}} bits 0–63 of VR0–15 are also FPR0–15. A vector register may contain 16 8-bit fields, 8 16-bit fields, 4 32-bit fields, 2 64-bit fields or 1 128-bit field.
Memory
IBM classifies memory in z/Architecture into Main Storage and Expanded Storage.
Main storage is addressed in 8-bit bytes (octets), with larger aligned{{efn|Some instructions allow references to unaligned data.}} groupings:
;Halfword
:Two bytes
:16 bits
;Word
:Four bytes
:32 bits
;Doubleword
:8 bytes
:64 bits
;Quadword
:16 bytes
:128 bits
;Page
:4096 bytes
Although z/Architecture allows real and virtual addresses from 0 to 264-1, engineering constraints limit current and planned models to far less.
Expanded storage is address in 4 KiB blocks, with block numbers ranging fom 0 to 232.
Addressing
{{stub-section|date=June 2024}}
=Types of main storage addresses=
There are three types of main storage addresses in z/Architecture
;Virtual address
:The address as seen by application programs. It is an offset into an address space and is subject to address translation via page and segment tables.
;Real address
:The address after address translation, or the address seen by an OS component running with translation off. It is subject to prefixing.
;Absolute address
:The address after prefixing references to the first two pages{{efn|References to the first page in ESA mode, but that is not available on current models.}} via the prefix register.
=Address encoding=
z/Architecture uses the same truncated addressing as ESA, with some additional instruction formats. As with ESA, in AR mode each nonzero base register is associated with a base register specifying the address space. Depending on the instruction, an address may be provided in several different formats.
;R
:The address is contained in a general register
;Relative
:A signed 16-bit halfword offset from the current instruction.
;Relative long
:A signed 32-bit halfword offset from the current instruction.
;RS
:A base register and a 12-bit displacement
;RX
:A base register, an index register, and a 12-bit displacement
;Y
:A base register, an index register, and a 20-bit displacement; colloquially known as "Yonder".
=Addressing modes=
In addition to the two addressing modes supported by S/370-XA and ESA, a/Architecture has an extended addressing mode with 64-bit virtual addresses. The addressing mode is controlled by the EA (bit 31) and BA (bit 32) bits in the PSW. The valid combinations are
- 00 24-bit addressing
- 01 31-bit addressing
- 11 64-bit addressing
=Translation modes=
z/Architecture supports four virtual translation modes, controlled by{{sfn|z|loc=Figure 3-15. Translation Modes|pp=[https://www.vm.ibm.com/library/other/22783213.pdf#page=147 3-41, 3-42]}} bit 5, the DAT-mode bit, and bits 16–17, the Address-Space Control (AS) bits, of the PSW.
;Primary-space mode
:All storage references use the translation tables for the primary address space
;Access-register mode
:All storage references use the translation tables designated by the access register associated with the base register.
;Secondary-space mode
:All storage references use the translation tables for the secondary address space
;Home-space mode
:All storage references use the translation tables for the home address space
Operating system support
IBM's operating systems z/OS, z/VSE, z/TPF, and z/VM are versions of MVS, VSE, Transaction Processing Facility (TPF), and VM that support z/Architecture. Older versions of z/OS, z/VSE, and z/VM continued to support 32-bit systems; z/OS version 1.6 and later, z/VSE Version 4 and later, and z/VM Version 5 and later require z/Architecture.
Linux also supports z/Architecture with Linux on IBM Z.
z/Architecture supports running multiple concurrent operating systems and applications even if they use different address sizes. This allows software developers to choose the address size that is most advantageous for their applications and data structures.
On July 7, 2009, IBM on occasion of announcing a new version of one of its operating systems implicitly stated that Architecture Level Set 4 (ALS 4) exists, and is implemented on the System z10 and subsequent machines.[https://www.ibm.com/common/ssi/rep_ca/7/897/ENUS209-207/ENUS209-207.PDF Preview: IBM z/VM V6.1 – Foundation for future virtualization growth] {{Webarchive|url=https://web.archive.org/web/20211028213436/https://www.ibm.com/common/ssi/rep_ca/7/897/ENUS209-207/ENUS209-207.PDF |date=2021-10-28 }}, IBM United States Software Announcement
209-207, dated July 7, 2009ALS 1 was 9672 G2; ALS 2 was 9672 G5; ALS 3 was the original z/Architecture:{{cite web|title=IBM CMOS Processor Table|date=November 18, 2008|url=https://www.vm.ibm.com/devpages/jelliott/cmosproc.html|access-date=18 October 2012|archive-date=10 December 2013|archive-url=https://web.archive.org/web/20131210190707/http://www.vm.ibm.com/devpages/jelliott/cmosproc.html|url-status=live}} The ALS 4 is also specified in LOADxx as ARCHLVL 3, whereas the earlier z900, z800, z990, z890, System z9 specified ARCHLVL 2. Earlier announcements of System z10 simply specified that it implements z/Architecture with some additions: 50+ new machine instructions, 1 MB page frames, and hardware decimal floating-point unit (HDFU).{{cite web|title=IBM System z10 Business Class (z10 BC) Reference Guide|website=IBM |year=2008|url=https://www.ibm.com/systems/in/resources/systems_ap_z_hardware_z10bc_index_content_zs003021usen.pdf|access-date=2012-10-18|archive-date=2011-03-04|archive-url=https://web.archive.org/web/20110304060145/http://www-03.ibm.com/systems/in/resources/systems_ap_z_hardware_z10bc_index_content_zs003021usen.pdf|url-status=live}}{{Cite web |url=https://publibfp.boulder.ibm.com/epubs/pdf/dz9zr010.pdf |title=z/Architecture Principles of Operation |access-date=2016-01-15 |archive-date=2020-11-30 |archive-url=https://web.archive.org/web/20201130225514/http://publibfp.boulder.ibm.com/epubs/pdf/dz9zr010.pdf |url-status=live }}
Most{{citation needed|date=September 2017}} operating systems for the z/Architecture, including z/OS, generally restrict code execution to the first 2 GB (31 address bits, or 231 addressable bytes) of each virtual address space for reasons of efficiency and compatibility rather than because of architectural limits. Linux on IBM Z allows code to execute within 64-bit address ranges.
=z/OS=
Each z/OS address space, called a 64-bit address space, is 16 exabytes in size.
==Code (or mixed) spaces==
The z/OS implementation of the Java programming language is an exception. The z/OS virtual memory implementation supports multiple 2 GB address spaces, permitting more than 2 GB of concurrently resident program code.
==Data-only spaces==
Data-only spaces are memory regions that can be read from and written to, but not used as executable code. (Similar to the NX bit on other modern processors.)
By default, the z/Architecture memory space is indexed by 64-bit pointers, allowing up to 16 exabytes of memory to be visible to an executing program.
==={{anchor}}Dataspaces and hiperspaces===
Applications that need more than a 16 exabyte data address space can employ extended addressability techniques, using additional address spaces or data-only spaces. The data-only spaces that are available for user programs are called:
- dataspaces (sometimes referred to as "data spaces"){{cite book
|last1 = Hoskins
|first1 = Jim
|last2 = Frank
|first2 = Bob
|title = Exploring IBM Eserver Zseries and S/390 Servers
|year = 2002
|publisher = Maximum Press
|isbn = 1885068913
|url = https://books.google.com/books?id=NtHhpIjIFMEC&pg=PA26
|page = 26
|quote = VM Data Spaces architecture is standard on all System/390 processors.
|access-date = 2017-10-19
|archive-date = 2021-04-27
|archive-url = https://web.archive.org/web/20210427054109/https://books.google.com/books?id=NtHhpIjIFMEC&pg=PA26
|url-status = live
- hiperspaces (High performance space).{{cite web|url=https://www.ibm.com/docs/en/zp-and-ca/3.1.0?topic=resources-analyzing-data-in-memory|title=Analyzing data in memory|publisher=IBM}}{{cite newsgroup
|url = https://ibmmainframes.com/about25176.html#ixzz4WnbYLLq4
|title = What is hiperspace? Which was the first OS to support hiperspace?
|author = Hemanth Nandas
|newsgroup = ibmmainframes.com
|date = October 15, 2007
|access-date = January 25, 2017
|archive-date = February 2, 2017
|archive-url = https://web.archive.org/web/20170202024636/http://ibmmainframes.com/about25176.html#ixzz4WnbYLLq4
|url-status = live
}} HIGH PERFORMANCE SPACE or "High Performance Dataspace" (author Anuj Dhawan, same date)
These spaces are similar in that both are areas of virtual storage that a program can create, and can be up to 2 gigabytes. Unlike an address space, a dataspace or hiperspace contains only user data; it does not contain system control blocks or common areas. Program code cannot run in a dataspace or a hiperspace.{{Cite web |url=http://zseries.marist.edu/pdfs/ztidbitz/54%20zTidBits%20%28zOS%20ExtendedAddressability%29.pdf |title=CheatSheet #54 zTidBits z/OS Extended Addressing |access-date=2022-07-17}}
A dataspace differs from a hiperspace in that dataspaces are byte-addressable, whereas hiperspaces are page-addressable.
=IBM mainframe expanded storage=
Traditionally IBM Mainframe memory has been byte-addressable. This kind of memory is termed "Central Storage". IBM Mainframe processors through much of the 1980s and 1990s supported another kind of memory: Expanded Storage. It was first introduced with the IBM 3090 high-end mainframe series in 1985.{{Cite journal |last1=Sakaki |first1=M. |last2=Samukawa |first2=H. |last3=Honjou |first3=N. |date=1988 |title=Effective utilization of IBM 3090 large virtual storage in the numerically intensive computations of ab initio molecular orbitals |url=https://ieeexplore.ieee.org/document/5387596 |journal=IBM Systems Journal |volume=27 |issue=4 |pages=528–540 |doi=10.1147/sj.274.0528 |issn=0018-8670|url-access=subscription }}
Expanded Storage is 4KB-page addressable. When an application wants to access data in Expanded Storage it must first be moved into Central Storage. Similarly, data movement from Central Storage to Expanded Storage is done in multiples of 4 KB pages. Initially page movement was performed using relatively expensive instructions, by paging subsystem code.
The overhead of moving single and groups of pages between Central and Expanded Storage was reduced with the introduction
of the MVPG (Move Page) instruction and the ADMF (Asynchronous Data Mover Facility) capability.
The MVPG instruction and ADMF are explicitly invoked—generally by middleware in z/OS or z/VM (and ACP?)—to access data in expanded storage. Some uses are namely:
- MVPG is used by VSAM Local Shared Resources (LSR) buffer pool management to access buffers in a hiperspace in Expanded Storage.
- Both MVPG and ADMF are used by IBM Db2 to access hiperpools. Hiperpools are portions of a buffer pool located in a hiperspace.
- VM Minidisk Caching.
Until the mid-1990s Central and Expanded Storage were physically different areas of memory on the processor. Since the mid-1990s Central and Expanded Storage were merely assignment choices for the underlying processor memory.
These choices were made based on specific expected uses:
For example, Expanded Storage is required for the Hiperbatch function (which uses the MVPG instruction to access its hiperspaces).
In addition to the hiperspace and paging cases mentioned above there are other uses of expanded storage, including:
- Virtual I/O (VIO) to Expanded Storage which stored temporary data sets in simulated devices in Expanded Storage. (This function has been replaced by VIO in Central Storage.)
- VM Minidisk Caching.
z/OS removed the support for Expanded Storage. All memory in z/OS is now Central Storage. z/VM 6.4 fulfills Statement of Direction to drop support for all use of Expanded Storage.
=MVPG and ADMF=
==MVPG==
IBM described MVPG as "moves a single page and the central processor cannot execute any other instructions until the page move is completed."{{patent|US|5442802|Asynchronous co-processor data mover method and means}}
The MVPG mainframe instruction{{cite web|url=https://www.bixoft.nl/english/opcd/mvpg.htm|title=HLASM – MVPG = MoVe PaGe|access-date=2017-01-24|archive-date=2013-10-06|archive-url=https://web.archive.org/web/20131006113734/http://www.bixoft.nl/english/opcd/mvpg.htm|url-status=live}} (MoVe PaGe, opcode X'B254') has been compared to the MVCL (MoVe Character Long) instruction, both of which can move more than 256 bytes within main memory using a single instruction. These instructions do not comply with definitions for atomicity, although they can be used as a single instruction within documented timing and non-overlap restrictions.MOVE LONG, note 8.{{cite web
|url=http://bitsavers.informatik.uni-stuttgart.de/pdf/ibm/370/princOps/GA22-7000-10_370_Principles_of_Operation_Sep87.pdf
|title=GA22-7000-10, IBM System/370, Principles of Operation
|access-date=2021-10-11
|archive-date=2021-04-11
|archive-url=https://web.archive.org/web/20210411000251/http://bitsavers.informatik.uni-stuttgart.de/pdf/ibm/370/princOps/GA22-7000-10_370_Principles_of_Operation_Sep87.pdf
|url-status=live
The need to move more than 256 bytes within main memory had historically been addressed with software{{cite web|url=https://www.ibm.com/support/knowledgecenter/en/SSLTBW_2.1.0/com.ibm.zos.v2r1.hasc200/hasc2__MVCL_____Move_more_than_256_bytes_of_storage.htm|title=$MVCL – Move more than 256 bytes of storage| website=IBM |date=20 September 2014|access-date=24 January 2017|archive-date=2 February 2017|archive-url=https://web.archive.org/web/20170202033701/https://www.ibm.com/support/knowledgecenter/en/SSLTBW_2.1.0/com.ibm.zos.v2r1.hasc200/hasc2__MVCL_____Move_more_than_256_bytes_of_storage.htm|url-status=live}} (MVC loops), MVCL,{{cite web|url=http://csc.columbusstate.edu/woolbright/Instructions/MVCL.HTM|title=Move Long|access-date=2017-01-24|archive-date=2017-04-27|archive-url=https://web.archive.org/web/20170427234006/http://csc.columbusstate.edu/woolbright/Instructions/MVCL.HTM|url-status=live}} which was introduced with the 1970 announcement of the System/370, and MVPG, patented{{patent|US|5237668|Process using virtual addressing in a non-privileged instruction to control the copying of a page of data in or between multiple media}} and announced by IBM in 1989, each have advantages.{{cite mailing list|url=https://groups.google.com/forum/#!topic/bit.listserv.ibm-main/Y-P4xYn3n-0|title=MVPG faster than MVCL for aligned pages?|mailing-list=IBM-MAIN|access-date=2017-01-24|archive-date=2011-01-22|archive-url=https://arquivo.pt/wayback/20110122130054/https://groups.google.com/forum/#!topic/bit.listserv.ibm-main/Y-P4xYn3n-0|url-status=live}}
==ADMF==
ADMF (Asynchronous Data Mover Facility), which was introduced in 1992, goes beyond the capabilities of the MVPG (Move Page) instruction, which is limited to a single page,IBM's patent EP0549924A1 describes MVPG as "moves a single page." and can move groups of pages between Central and Expanded Storage.
A macro instruction named IOSADMF, which has been described as an API that avoids "direct, low-level use of ADMF",{{cite mailing list|url=https://groups.google.com/forum/#!topic/bit.listserv.ibm-main/oavv1AfA6oA|title=admf|mailing-list=IBM-MAIN |first1=Art |last1=Celestini |date=August 20, 1997 |via=Google Groups |access-date=2017-01-24|archive-date=2011-01-22|archive-url=https://arquivo.pt/wayback/20110122130054/https://groups.google.com/forum/#!topic/bit.listserv.ibm-main/oavv1AfA6oA|url-status=live}} can be used to read{{efn|AREAD – transfer data from a hiperspace to the program's primary address space.}} or write data to or from a hiperspace.z/OS MVS Programming: Extended Addressability Guide – SA23-1394-00 Hiperspaces are created using DSPSERV CREATE.
To provide reentrancy, IOSADMF is used together with a "List form" and "Execute form."{{cite web|url=https://www.ibm.com/support/knowledgecenter/SSLTBW_2.1.0/com.ibm.zos.v2r1.ieaa200/iosadmf.htm|title=IOSADMF — Transfer hiperspace data| website=IBM |date=February 7, 2015|access-date=January 24, 2017|archive-date=2 February 2017|archive-url=https://web.archive.org/web/20170202032953/http://www.ibm.com/support/knowledgecenter/SSLTBW_2.1.0/com.ibm.zos.v2r1.ieaa200/iosadmf.htm|url-status=live}}
Non-IBM implementations
Platform Solutions Inc. (PSI) previously marketed Itanium-based servers which were compatible with z/Architecture. IBM bought PSI in July 2008, and the PSI systems are no longer available.{{cite press release |title=IBM Acquires Platform Solutions |publisher=IBM |date=2008-07-02 |url=https://www-03.ibm.com/press/us/en/pressrelease/24560.wss |access-date=2008-09-06 |archive-date=2008-09-05 |archive-url=https://web.archive.org/web/20080905095542/http://www-03.ibm.com/press/us/en/pressrelease/24560.wss |url-status=dead }} FLEX-ES, zPDT and the Hercules emulator also implement z/Architecture. Hitachi mainframes running newer releases of the VOS3 operating system implement ESA/390 plus Hitachi-unique CPU instructions, including a few 64-bit instructions. While Hitachi formally collaborated with IBM on the z900-G2/z800 CPUs introduced in 2002, Hitachi's machines are not z/Architecture-compatible.
Notes
{{Notelist}}
References
;z
:{{cite book
| title = z/Architecture Principles of Operation
| id = SA22-7832-13
| date = May 2022
| edition = Fourteenth
| ref = {{sfnref|z}}
| url = https://www.vm.ibm.com/library/other/22783213.pdf
| publisher = IBM
| access-date = June 28, 2024
}}
{{Reflist}}
Further reading
- [https://preshing.com/20130618/atomic-vs-non-atomic-operations Preshing on Programming – Atomic vs. Non-Atomic Operations]
- [https://ocw.mit.edu/courses/res-6-004-principles-of-computer-system-design-an-introduction-spring-2009/de2b7c59e413f58e51eac60acd52efef_atomicity_open_5_0.pdf Principles of Computer Design – Atomicity]
{{CPU technologies}}
{{DEFAULTSORT:Z Architecture}}
Category:IBM mainframe technology
Category:Instruction set architectures