Espresso (processor)

{{Infobox CPU

| name = Espresso

| image = Nintendo-Wii-U-MCM.jpg

| image_size = 250px

| caption = An illustration of the Wii U MCM without heat spreader. The smaller chip, lower right, is the "Espresso" CPU made by IBM. The other chips are the "Latte" GPU (large chip, center) from AMD and an EEPROM chip (tiny chip, upper right) from Renesas.

| produced-start = 2012

| produced-end = January 31, 2017

| slowest = 1.243

| slow-unit = GHz

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| size-from = 45 nm

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| soldby = Nintendo

| designfirm = IBM, Nintendo IRD, NTD

| manuf1 = IBM Microelectronics, Renesas

| core1 =

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| arch = PowerPC 1.1

| microarch = Not verified by Nintendo

| instructions = 4

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| numcores = 3

| l1cache =

| l2cache = 1× 2 MB, 2× 512 KB (on-die)

| l3cache =

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| llcache = 3

| gpu = AMD Radeon-based "Latte"

| application = Embedded (Wii U)

| predecessor = Broadway

| successor = Erista

| variant =

}}

Espresso is the codename of the 32-bit central processing unit (CPU) used in Nintendo's Wii U video game console. It was designed by IBM, and was produced using a 45 nm silicon-on-insulator process. The Espresso chip resides together with a GPU from AMD on an MCM manufactured by Renesas. It was revealed at E3 2011 in June 2011 and released in November 2012.

Design

File:Nintendo-Wii-U-processor-heatspreader.jpg

File:Wii U CPU GPU.jpg

IBM and Nintendo have revealed that the Espresso processor is a PowerPC-based microprocessor with three cores on a single chip to reduce power consumption and increase speed. The CPU and the graphics processor are placed on a single substrate as a multi-chip module (MCM) to reduce complexity, increase the communication speed between the chips, further reduce power consumption, and reduce cost and space required. The two chips were assembled to the complete MCM by Renesas in Japan.{{Cite web |url=https://iwataasks.nintendo.com/interviews/#/wiiu/console/0/0 |title=Wii U : The Console : Changes in Television |website=Iwata Asks |publisher=Nintendo |archive-url=https://web.archive.org/web/20220609231841/https://iwataasks.nintendo.com/interviews/#/wiiu/console/0/0 |archive-date=2022-06-09 |url-status=dead}} Espresso itself was manufactured by IBM in its 300 mm plant in East Fishkill, New York, using 45 nm SOI-technology{{cite web |url=http://www.advancedsubstratenews.com/2011/07/new-wii-u™-on-soi/ |title=NEW WII U™ ON SOI |archive-url=https://web.archive.org/web/20160325055520/http://www.advancedsubstratenews.com/2011/07/new-wii-u%E2%84%A2-on-soi/ |archive-date=2016-03-25 |url-status=dead}} and embedded DRAM (eDRAM) for caches.

While unverified by Nintendo, hackers, teardowns, and unofficial informants have since revealed more information about the Espresso, such as its name,{{cite web |url=http://www.vgleaks.com/world-exclusive-wii-u-final-specs/ |title=World Exclusive: Wii U Final Specs|date=11 September 2012 }} size{{cite web |url=http://www.anandtech.com/show/6465/nintendo-wii-u-teardown |title=Nintendo Wii U Teardown |website=AnandTech}}{{cite web |url=http://www.ifixit.com/Teardown/Nintendo+Wii+U+Teardown/11796 |title=Nintendo Wii U Teardown |website=iFixit|date=19 November 2012 }} and speed.{{cite news |url=http://www.eurogamer.net/articles/digitalfoundry-wii-hacker-reveals-wii-u-cpu-secrets |title=Wii U has 1.24GHz CPU, 550MHz graphics core|newspaper=Eurogamer.net |date=29 November 2012 }}{{cite web |url=http://www.ign.com/articles/2012/11/29/wii-u-cpu-gpu-details-uncovered |title=Wii U CPU, GPU Details Uncovered|date=29 November 2012 }} The microarchitecture seems to be quite similar to its predecessors the Broadway and Gekko, i.e. PowerPC 750 based, but enhanced with larger and faster caches and multiprocessor support.

Rumors that the Wii U CPU was derived from IBM's high-end POWER7 server processor proved false, as it would potentially increase the manufacturing and retail cost of the system, and require a larger form factor. Espresso shares some technology with POWER7, such as eDRAM and general instruction set similarities, but those are superficial similarities.{{cite web |url=https://www.engadget.com/2011/06/07/ibm-puts-watsons-brains-in-nintendo-wii-u/ |title=IBM puts Watson's brains in Nintendo Wii U}}{{cite news |url=http://www.eurogamer.net/articles/digitalfoundry-ibm-teases-on-wii-u-cpu |title=IBM teases on Wii U CPU specs|newspaper=Eurogamer.net |date=8 June 2011 }}{{cite web |url=https://www.pcmag.com/article2/0,2817,2397198,00.asp |title=Rumored Wii U Specs Raising Eyebrows... for the Wrong Reasons}}{{cite web |url=http://www.gonintendo.com/?mode=viewstory&id=184227 |title=IBM reconfirms the Wii U/Watson connection|date=27 August 2012 }}{{cite web |url=http://hothardware.com/News/IBM-Confirms-WII-U-Utilizes-PowerBased-CPU-Not-Power-7 |title=IBM Confirms WII U Utilizes Power-Based CPU, Not Power 7|date=25 September 2012 }}

Specifications

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Out-of-order execution PowerPC based cores
45 nanometer process technology
IBM silicon on insulator (SOI) technology
Backward compatible with the Broadway and Gekko processors

The following specifications have not been officially confirmed by either Nintendo or IBM. They have been obtained by reverse engineering by hacker Hector Martin, alias marcan.{{cite web|url=http://hothardware.com/News/Hackers-Discover-Wii-Us-Clock-Speed-Processor-Design/|title=Hackers Discover Wii U's Processor Design and Clock Speed|author=Joel Hruska|publisher=HotHardware|date=November 29, 2012|access-date=January 21, 2014}}

Broadway-based core architecture{{cite tweet |user=marcan42 |first=Héctor |last=Martín |number=277823057844903938 |title=@DFaker no, it's just a 750. PPC750 can issue 3/cycle and retire 2/cycle. @dampflokfreund yes, three Broadways and more cache. |date=2012-12-09 |archive-url=https://web.archive.org/web/20131005034521/https://twitter.com/marcan42/status/277823057844903938 |archive-date=2013-10-05 |url-status=dead}}
Three cores at 1.243125 GHz
Symmetric multiprocessing with MESI/MERSI support{{cite tweet |user=marcan42 |first=Héctor |last=Martín |number=404310017882726400 |title=Hah! My Twitter arguing must be so sad that I just got this screenshot in my inbox (anon sender): https://marcansoft.com/transf/espresso_intro.png … @EyeOfCore|date=2013-11-23 |archive-url=https://web.archive.org/web/20131203061611/https://twitter.com/marcan42/status/404310017882726400 |archive-date=2013-12-03 |url-status=dead}} (links to PNG of a page from the IBM Espresso RISC Processor Developer's User Manual)
Each core can output up to 4 instructions per clock using superscalar parallelism.
32-bit integer unit
64-bit floating-point (or 2× 32-bit SIMD, often found under the denomination "paired singles")
A total of 3 MB of Level 2 cache in an unusual configuration.{{cite tweet |user=marcan42 |first=Héctor |last=Martín |number=296605342568153089 |title=@theevilmuppet L1 is the same, L2 is different (this is the claimed eDRAM). 512K/2M/512K L2 cache per core (core 1 has more cache). |date=2013-01-30 |archive-url=https://web.archive.org/web/20131008041027/https://twitter.com/marcan42/status/296605342568153089 |archive-date=2013-10-08 |url-status=dead}}
Core 0: 512 KB, core 1: 2 MB, core 2: 512 KB
4 stage pipeline {{cite web |url=https://fail0verflow.com/media/files/ppc_750cl.pdf |title=IBM PowerPC 750CL Microprocessor Revision Level DD2.x Datasheet}}
7 stage pipeline - FP
6 Execution Units per core (18 EUs total)
Die size: 4.74 mm × 5.85 mm = 27.73 mm²

Espresso (processor)

Design

Specifications

References

Further reading