Opcode

{{short description|Part of a machine instruction}}

{{Use dmy dates|date=March 2020|cs1-dates=y}}

{{Machine code}}

In computing, an opcode (abbreviated from operation code) is an enumerated value that specifies the operation to be performed. Opcodes are employed in hardware devices such as arithmetic logic units (ALUs), central processing units (CPUs), and software instruction sets. In ALUs, the opcode is directly applied to circuitry via an input signal bus. In contrast, in CPUs, the opcode is the portion of a machine language instruction that specifies the operation to be performed.

CPUs

Opcodes are found in the machine language instructions of CPUs as well as in some abstract computing machines. In CPUs, an opcode may be referred to as an instruction machine code, instruction code, instruction syllable, instruction parcel, or opstring. For any particular processor (which may be a general CPU or a more specialized processing unit), the opcodes are defined by the processor's instruction set architecture (ISA). They can be described using an opcode table. The types of operations may include arithmetic, data copying, logical operations, program control, and special instructions (e.g., CPUID).

In addition to the opcode, many instructions specify the data (known as operands) the operation will act upon, although some instructions may have implicit operands or none. Some instruction sets have nearly uniform fields for opcode and operand specifiers, whereas others (e.g., x86 architecture) have a less uniform, variable-length structure. Instruction sets can be extended through opcode prefixes, which add a subset of new instructions made up of existing opcodes following reserved byte sequences.{{Citation needed|date=February 2023}}

=Sample opcode table=

This table shows opcodes of a simple 8-bit microprocessor, the Intel 8008 from 1972.

Each opcode is 8 bits long. Each is shown as a binary pattern of ones and zeros in the Opcode column. Up to two additional fields may be embedded into the opcode. Some 3-bit fields are labeled DDD, SSS, CC, and ALU. The SSS (source) and DDD (destination) fields specify one of the eight possible 8008 registers or memory: A, B, C, D, E, H, L, or M. CC specifies a condition that will activate certain JMP, CAL, and RET instructions. ALU specifies one of a possible eight arithmetic logic unit functions to be performed during an instruction, specifically, add, add with carry, subtract, subtract with borrow, logical AND, logical XOR, logical OR, and compare. The X in some fields means that either a 1 or 0 can be inserted with no effect.

The fixed ones and zeros are combined with the parameter fields to build the 8-bit opcode. Additionally, the full instruction might require one or two additional bytes of operands. These are shown in the second major column of the table, labeled "Operands". If no operands are required, the column is filled with a dash (—).

Since the ones and zeros are difficult to remember, the Mnemonic column shows a short, easy to remember letter code that an assembly language programmer may use to invoke the required opcode.

The Description column shows the function performed by the microprocessor when it encounters a specific opcode.

class="wikitable" style="text-align:center"

!colspan=8| Opcode

colspan=2| Operandsrowspan=2| Mnemonicrowspan=2| Description
7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3
0000000Xalign=left| HLTalign=left| Halt
00colspan=3|DDD000align=left| INralign=left| DDD ← DDD + 1 (except A and M)
00colspan=3|DDD001align=left| DCralign=left| DDD ← DDD - 1 (except A and M)
00000010align=left| RLCalign=left| A1-7 ← A0-6; A0 ← Cy ← A7
00colspan=3|CC011align=left| Rcc (RET conditional)align=left| If cc true, P ← (stack)
00colspan=3|ALU100dataalign=left| ADI ACI SUI SBI NDI XRI ORI CPI dataalign=left| A ← A [ALU operation] data
00colspan=3|N101align=left| RST nalign=left| (stack) ← P, P ← N x 8
00colspan=3|DDD110dataalign=left| LrI data (Load r with immediate data)align=left| DDD ← data
00XXX111align=left| RETalign=left| P ← (stack)
00001010align=left| RRCalign=left| A0-6 ← A1-7; A7 ← Cy ← A0
00010010align=left| RALalign=left| A1-7 ← A0-6; Cy ← A7; A0 ← Cy
00011010align=left| RARalign=left| A0-6 ← A1-7; Cy ← A0; A7 ← Cy
01colspan=3|CC000addloaddhialign=left| Jcc add (JMP conditional)align=left| If cc true, P ← add
0100colspan=3|port1align=left| INP portalign=left| A ← Port (ports 0-7 only)
01colspan=5|port1align=left| OUT portalign=left| Port ← A (ports 8-31 only)
01colspan=3|CC010addloaddhialign=left| Ccc add (CAL conditional)align=left| If cc true, (stack) ← P, P ← add
01XXX100addloaddhialign=left| JMP addalign=left| P ← add
01XXX110addloaddhialign=left| CAL addalign=left| (stack) ← P, P ← add
10colspan=3|ALUcolspan=3|SSSalign=left| ADr ACr SUr SBr NDr XRr ORr CPralign=left| A ← A [ALU operation] SSS
11colspan=3|DDDcolspan=3|SSSalign=left| Lds (Load d with s)align=left| DDD ← SSS
11111111align=left| HLTalign=left| Halt
7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3 || Mnemonic || Description
colspan=13|
colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU
colspan=5| A000colspan=2|FC, C falsealign=left|ADr ADI (A ← A + arg)
colspan=5| B001colspan=2|FZ, Z falsealign=left|ACr ACI (A ← A + arg + Cy)
colspan=5| C010colspan=2|FS, S falsealign=left|SUr SUI (A ← A - arg)
colspan=5| D011colspan=2|FP, P oddalign=left|SBr SBI (A ← A - arg - Cy)
colspan=5| E100colspan=2|TC, C truealign=left|NDr NDI (A ← A ∧ arg)
colspan=5| H101colspan=2|TZ, Z truealign=left|XRr XRI (A ← A ⊻ arg)
colspan=5| L110colspan=2|TS, S truealign=left|ORr ORI (A ← A ∨ arg)
colspan=5| M111colspan=2|TP, P evenalign=left|CPr CPI (A - arg)
colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU

{{Anchor|SIS}}Software instruction sets

Opcodes can be found in bytecodes and other representations intended for execution by software interpreters. These often employ slightly higher-level data types and operations than those found in hardware opcodes but are nevertheless constructed along similar lines. Examples include the byte code found in Java class files, which are interpreted by Java virtual machines, the byte code used in GNU Emacs for compiled Lisp code, and NET Common Intermediate Language.

See also

References

{{Reflist|40em|refs=

{{cite book |author-first=David William |author-last=Barron |author-link=David W. Barron |editor-first=J. John |editor-last=Floretin |title=Assemblers and Loaders |date=1978 |orig-year=1971, 1969 |edition=3 |publisher=Elsevier North-Holland Inc. |series=Computer Monographs |publication-place=New York, USA |location=University of Southampton, Southampton, UK |isbn=0-444-19462-2 |lccn=78-19961 |chapter=2.1. Symbolic instructions |page=7}} (xii+100 pages)

{{cite web |title=A Minimal CISC |work=Computer Architecture On-Line Collection |author-first=Douglas W. |author-last=Jones |publisher=The University of Iowa, Department of Computer Science |date=2016 |orig-year=2012 |location=Iowa City, USA |url=http://homepage.cs.uiowa.edu/~jones/arch/cisc/ |access-date=2016-05-28 |url-status=live |archive-url=https://web.archive.org/web/20200302190911/http://homepage.cs.uiowa.edu/~jones/arch/cisc/ |archive-date=2020-03-02}}

{{cite journal |title=A Minimal CISC |author-first=Douglas W. |author-last=Jones |journal=ACM SIGARCH Computer Architecture News |publisher=Association for Computing Machinery (ACM) |location=New York, USA |date=June 1988 |volume=16 |issue=3 |pages=56–63 |doi=10.1145/48675.48684 |s2cid=17280173 |doi-access=free }}

{{cite book |title=Application of CLP to instruction modulo scheduling for VLIW processors |chapter=7.1.4. Benchmark suite |author-first=Łukasz |author-last=Domagała |publisher=Jacek Skalmierski Computer Studio |date=2012 |isbn=978-83-62652-42-6 |pages=80–83 [83] |location=Gliwice, Poland |url=https://books.google.com/books?id=e6apNOED26kC |chapter-url=https://books.google.com/books?id=e6apNOED26kC |access-date=2016-05-28 |url-status=live |archive-url=https://web.archive.org/web/20200302192452/https://books.google.de/books?hl=de&id=e6apNOED26kC&jtp=83 |archive-date=2020-03-02}}

{{cite web |title=Multiple Instruction Issue |author-first=Mark |author-last=Smotherman |publisher=School of Computing, Clemson University |date=2016 |orig-year=2013 |url=https://people.cs.clemson.edu/~mark/330/ilp.txt |access-date=2016-05-28 |url-status=live |archive-url=https://web.archive.org/web/20160528142545/https://people.cs.clemson.edu/~mark/330/ilp.txt |archive-date=2016-05-28}}

{{cite magazine |title=Finding Binary Clones with Opstrings & Function Digests |author-first=Andrew |author-last=Schulman |magazine=Dr. Dobb's Journal |volume=30 |issue=7 |id=#374 |issn=1044-789X |publisher=CMP Media LLC |date=2005-07-01 |series=Part I |pages=69–73 |url=http://www.drdobbs.com/finding-binary-clones-with-opstrings-fu/184406152 |access-date=2020-03-02 |url-status=live |archive-url=https://web.archive.org/web/20200302175401/https://www.drdobbs.com/finding-binary-clones-with-opstrings-fu/184406152 |archive-date=2020-03-02 |postscript=none}}; {{cite magazine |title=Finding Binary Clones with Opstrings & Function Digests |author-first=Andrew |author-last=Schulman |magazine=Dr. Dobb's Journal |volume=30 |issue=8 |id=#375 |issn=1044-789X |publisher=CMP Media LLC |date=2005-08-01 |series=Part II |pages=56–61 |url=http://www.drdobbs.com/finding-binary-clones-with-opstrings-fu/184406203 |access-date=2016-05-28 |url-status=live |archive-url=https://web.archive.org/web/20200302185255/https://www.drdobbs.com/finding-binary-clones-with-opstrings-fu/184406203 |archive-date=2020-03-02 |postscript=none}}; {{cite magazine |title=Finding Binary Clones with Opstrings & Function Digests |author-first=Andrew |author-last=Schulman |magazine=CMP Media LLC |volume=30 |issue=9 |id=#376 |issn=1044-789X |publisher=United Business Media |date=2005-09-01 |series=Part III |pages=64–70 |url=http://www.drdobbs.com/tools/finding-binary-clones-with-opstrings-fu/184406247 |access-date=2016-05-28 |url-status=live |archive-url=https://web.archive.org/web/20200302185646/https://www.drdobbs.com/tools/finding-binary-clones-with-opstrings-fu/184406247?pgno=3 |archive-date=2020-03-02}}

{{cite web |title=Javassist, a Java-bytecode translator toolkit |author-first=Shigeru |author-last=Chiba |date=2007 |orig-year=1999 |url=http://www.docjar.org/html/api/javassist/bytecode/InstructionPrinter.java.html |access-date=2016-05-27 |url-status=live |archive-url=https://web.archive.org/web/20200302185725/http://www.docjar.org/html/api/javassist/bytecode/InstructionPrinter.java.html |archive-date=2020-03-02}}

{{cite book |title=Computer architecture: A quantitative approach |author-last1=Hennessy |author-first1=John L. |author-last2=Patterson |author-first2=David A. |author-last3=Asanović |author-first3=Krste |author-link3=Krste Asanović |author-last4=Bakos |author-first4=Jason D. |author-last5=Colwell |author-first5=Robert P. |author-last6=Bhattacharjee |author-first6=Abhishek |author-last7=Conte |author-first7=Thomas M. |author-last8=Duato |author-first8=José |author-last9=Franklin |author-first9=Diana |author-last10=Goldberg |author-first10=David |author-last11=Jouppi |author-first11=Norman P. |author-last12=Li |author-first12=Sheng |author-last13=Muralimanohar |author-first13=Naveen |author-last14=Peterson |author-first14=Gregory D. |author-last15=Pinkston |author-first15=Timothy M. |author-last16=Ranganathan |author-first16=Parthasarathy |author-last17=Wood |author-first17=David A. |author-last18=Young |author-first18=Cliff |author-last19=Zaky |author-first19=Amr |date=2017-11-23 |edition=6 |publisher=Morgan Kaufmann Publishers |location=Cambridge, Massachusetts, USA |isbn=978-0-12811905-1 |oclc=983459758 }}

{{cite book |title=Machine Language For Beginners |chapter=Introduction: Why Machine Language? |author-first=Richard |author-last=Mansfield |date=1983 |series=Compute! Books |publisher=COMPUTE! Publications, Inc., American Broadcasting Companies, Inc.; Small System Services, Inc. |location=Greensboro, North Carolina, USA |isbn=0-942386-11-6 |edition=1 |url=https://www.atariarchives.org/mlb/index.php |chapter-url=http://www.atariarchives.org/mlb/introduction.php |access-date=2016-05-28 |url-status=live |archive-url=https://web.archive.org/web/20080213090055/http://www.atariarchives.org/mlb/introduction.php |archive-date=2008-02-13}}

{{cite magazine |title=bytecode Definition |series=PC Magazine Encyclopedia |magazine=PC Magazine |url=https://www.pcmag.com/encyclopedia_term/0,2542,t=bytecode&i=39108,00.asp |access-date=2015-10-10 |url-status=dead |archive-url=https://web.archive.org/web/20121006015213/http://www.pcmag.com/encyclopedia_term/0%2C2542%2Ct%3Dbytecode%26i%3D39108%2C00.asp |archive-date=6 October 2012 }}

{{cite book |title=MCS-4 Assembly Language Programming Manual - The INTELLEC 4 Microcomputer System Programming Manual |chapter=Appendix B - Instruction Machine Codes |edition=Preliminary |publisher=Intel Corporation |date=December 1973 |location=Santa Clara, California, USA |id=MCS-030-1273-1 |pages=B-1 – B-8 |chapter-url=http://bitsavers.trailing-edge.com/components/intel/MCS4/MCS-4_Assembly_Language_Programming_Manual_Dec73.pdf |access-date=2020-03-02 |url-status=live |archive-url=https://web.archive.org/web/20200301235541/http://bitsavers.trailing-edge.com/components/intel/MCS4/MCS-4_Assembly_Language_Programming_Manual_Dec73.pdf |archive-date=2020-03-01}}

{{cite book |title=MCS-40 User's Manual For Logic Designers |chapter=The Functions Of A Computer: Instruction Register And Decoder |publisher=Intel Corporation |editor-first=Howard A. |editor-last=Raphael |date=November 1974 |location=Santa Clara, California, USA |page=viii |chapter-url=http://bitsavers.trailing-edge.com/components/intel/MCS40/MCS-40_Users_Manual_Nov74.pdf |access-date=2020-03-03 |url-status=live |archive-url=https://web.archive.org/web/20200303024244/http://bitsavers.trailing-edge.com/components/intel/MCS40/MCS-40_Users_Manual_Nov74.pdf |archive-date=2020-03-03 |quote=[…] Each operation that the processor can perform is identified by a unique binary number known as an instruction code. […]}}

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{{X86 assembly topics}}

Category:Machine code