soft microprocessor

| Conor Santifort

| {{yes|LGPLv2.1}}

| Wishbone

| ARMv2a 3-stage or 5-stage pipeline

| [https://opencores.org/project/amber Project page at Opencores]

| Verilog

| ARM

| {{no}}

| [http://www.arm.com/products/system-ip/interconnect/index.php]

| 70–200{{nbsp}}MHz, 32-bit RISC

| [http://www.arm.com/products/CPUs/ARM_Cortex-M1.html]

| Verilog

| Sébastien Bourdeauducq

| {{yes}}

| Direct SRAM

| Atmel AVR-compatible 8-bit RISC

| [http://opencores.org/project,navre Project page at Opencores]

| Verilog

| Doru Cuturela

| {{yes}}

|

| Atmel AVR-compatible 8-bit RISC

| [http://opencores.org/project,pavr Project page at Opencores]

| VHDL

| Andras Pal

| {{yes}}

| Standard AVR buses (core-coupled I/O, synchronous SRAM, synchronous program ROM)

| Atmel AVR-compatible 8-bit RISC (up to AVR5), peripherals and SoC features included

| [http://opencores.org/project/softavrcore Project page at Opencores]

| Verilog

| Shawn Tan

| {{yes}}

| Wishbone

| MicroBlaze EDK 3.2 compatible

| [http://www.aeste.my/aemb AEMB]

| Verilog

| Xilinx

| {{no}}

| PLB, OPB, FSL, LMB, AXI4

|

| [https://web.archive.org/web/20030430214925/http://www.xilinx.com/microblaze/ Xilinx MicroBlaze]

|

| Virginia Tech CCM Lab

| {{yes}}

| OPB, FSL

| Binary compatible with the MicroBlaze

| [https://web.archive.org/web/20090724052731/http://www.ccm.ece.vt.edu/~scraven/openfire.html]{{Cite web|url=http://opencores.org/project,openfire_core,overview|title=Overview :: OpenFire Processor Core :: OpenCores}}

| Verilog

| LIRMM, University of Montpellier / CNRS

| {{yes}}

| Wishbone

| MicroBlaze ISA, VHDL

| [http://www.lirmm.fr/ADAC/?page_id=462 SecretBlaze]

| VHDL

| MicroCore Labs

| {{yes}}

| Ultra-small-footprint microsequencer-based 8051 core

| 312 Artix-7 LUTs. Quad-core 8051 version is 1227 LUTs.

| [http://www.microcorelabs.com MCL51 Core]

|

| Altium

| {{no|Royalty-free}}

| Wishbone / Intel 8051

| 8-bit Intel 8051 instruction set compatible, lower clock cycle alternative

| [https://web.archive.org/web/20160306202550/http://wiki.altium.com/display/adoh/processor-based+fpga+design Embedded Design on Altium Wiki]

|

| University of Cambridge

| {{yes|BSD}}

|

| MIPS

| [http://www.cl.cam.ac.uk/research/security/ctsrd/beri/ Project page]

| Bluespec

| René Doss

| {{yes|CC BY-NC 3.0, except commercial applicants have to pay a licence fee.}}

| Pipelined bus

| MIPS I instruction set pipeline stages

| [http://www.dossmatik.de/mais-cpu.html Dossmatik]

| VHDL

| Altium

| {{no|Royalty-free}}

| Wishbone

| 32-bit R3000-style RISC modified Harvard-architecture CPU

| [https://web.archive.org/web/20160306202550/http://wiki.altium.com/display/adoh/processor-based+fpga+design Embedded Design on Altium Wiki]

|

| Pablo Bleyer

| {{yes}}

|

| Compatible with the PicoBlaze processors

| [http://bleyer.org/pacoblaze PacoBlaze]

| Verilog

| Xilinx

| {{no}}

|

|

| [https://web.archive.org/web/20030501203653/http://www.xilinx.com/picoblaze/ Xilinx PicoBlaze]

| VHDL, Verilog

| University of Zagreb

| {{yes|BSD}}

| AXI, SDRAM, SRAM

| 32-bit, RISC-V / MIPS ISA subsets (retargetable), GCC toolchain

| [https://github.com/f32c/f32c f32c]

| VHDL

| Stephan Nolting

| {{yes|BSD}}

| Wishbone b4, AXI4

| rv32[i/e] [m] [a] [c] [b] [u] [Zfinx] [Zicsr] [Zifencei], RISC-V-compliant, CPU & SoC available, highly customizable, GCC toolchain

| [https://github.com/stnolting/neorv32 GitHub] [https://opencores.org/projects/neorv32 OpenCores]

| VHDL

| SpinalHDL|SpinalHDL

| {{Yes}}

| AXI4 / Avalon

| 32-bit, RISC-V, up to 340{{nbsp}}MHz on Artix 7. Up to 1.44{{nbsp}}DMIPS/MHz.

| https://github.com/SpinalHDL/VexRiscv

| VHDLVerilog (SpinalHDL)

| ESA

| {{yes}}

| AMBA2

| SPARC V8

| [http://www.esa.int/TEC/Microelectronics/SEMUD70CYTE_0.html ESA]

| VHDL

| Aeroflex Gaisler

| {{yes}}

| AMBA2

| SPARC V8

| [http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=156&Itemid=104 Aeroflex Gaisler]

| VHDL

| Princeton Parallel Group

| {{Yes}}

|

| Manycore SPARC V9

| [http://parallel.princeton.edu/openpiton/specs.html OpenPiton]

| Verilog

| Sun

| {{yes}}

|

| 64-bit

| [http://www.opensparc.net/opensparc-t1/index.html OpenSPARC.net]

| Verilog

| TemLib

| {{yes}}

| Pipelined bus

| SPARC V8

| [http://temlib.org TEMLIB]

| VHDL

| HT-Lab

| {{yes}}

|

| 8088-compatible CPU in VHDL

| [http://www.ht-lab.com/cpu86.htm cpu86]

| VHDL

| MicroCore Labs

| {{yes}}

| 8088 BIU provided. Others easy to create.

| Cycle accurate 8088/8086 implemented with a microsequencer. Less than 2% utilization of Kintex-7.

| [http://www.microcorelabs.com MCL86 Core]

|

| Jamie Iles

| {{yes|GPLv3}}

| Custom

| 80186-compatible GPLv3 core

| [https://www.jamieiles.com/80186/ s80x86]

| SystemVerilog

| Zeus Gómez Marmolejo

| {{yes}}

| Wishbone

| x86 PC clone

| [https://archive.today/20130112150552/http://zet.aluzina.org/ Zet]

| Verilog

| Aleksander Osman

| {{yes|3-Clause BSD}}

| Avalon

| i486 SX compatible core

| [https://github.com/alfikpl/ao486 ao486]

| Verilog

| IBM

| {{No}}

| CoreConnect

| 32-bit PowerPC v.2.03 Book E

| IBM

| Verilog

| IBM

| {{No}}

| CoreConnect

| 32-bit PowerPC v.2.03 Book E

| IBM

| Verilog

| IBM

| {{No}}

| CoreConnect

| 32-bit PowerPC v.2.05 Book E

| IBM

| Verilog

| IBM/OpenPOWER

| {{yes|CC-BY 4.0}}

| Wishbone

| 64-bit PowerISA 3.0 proof of concept

| [https://github.com/antonblanchard/microwatt Microwatt @ Github]

| VHDL

| IBM/OpenPOWER

| {{yes|CC-BY 4.0}}

| Wishbone

| 64-bit PowerISA 3.0

| [https://github.com/antonblanchard/chiselwatt Chiselwatt @ Github]

| Chisel

| [https://libre-soc.org Libre-SoC.org]

| {{yes|BSD/LGPLv2+}}

| Wishbone

| 64-bit PowerISA 3.0. CPU/GPU/VPU implementation and custom vector instructions

| [https://libre-soc.org Libre-SoC.org]

| python/nMigen

| IBM/OpenPOWER

| {{yes|CC-BY 4.0}}

| Custom PBus

| 64-bit PowerPC 2.6 Book E. In order core

| [https://github.com/openpower-cores/a2i A2I @ Github]

| VHDL

| IBM/OpenPOWER

| {{yes|CC-BY 4.0}}

| Custom PBus

| 64-bit PowerPC 2.7 Book E. Out of order core

| [https://github.com/openpower-cores/a2o A2O @ Github]

| Verilog

| ARC International, Synopsys

| {{no}}

|

| 16/32/64-bit ISA RISC

| [https://www.synopsys.com/designware-ip/processor-solutions.html DesignWare ARC]

| Verilog

| Entner Electronics

| {{no}}

|

| 9-bit RISC, very small size, C-programmable

| [http://www.entner-electronics.com/tl/index.php/eric5.html ERIC5] {{Webarchive|url=https://web.archive.org/web/20160305131214/http://www.entner-electronics.com/tl/index.php/eric5.html |date=2016-03-05 }}

| VHDL

| Richard James Howe

| {{yes | MIT}}

| Custom

| 16-bit Stack Machine, designed to execute Forth directly, small

| [https://github.com/howerj/forth-cpu H2 CPU]

| VHDL

| [http://www.fpga-cores.com/ FPGA Cores]

| {{no}}

| Custom

| 32-bit RISC-V M Extension, SoC defined by C++

| [http://www.fpga-cores.com/instant-soc/ Instant SoC]

| VHDL

| Martin Schoeberl

| {{yes}}

| SimpCon / Wishbone (extension)

| Stack-oriented, hard real-time support, executing Java bytecode directly

| [https://web.archive.org/web/20190417225405/http://www.jopdesign.com/ Jop]

| VHDL

| Lattice

| {{yes}}

| Wishbone

|

| [http://www.latticesemi.com/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/Mico8.aspx LatticeMico8]

| Verilog

| Lattice

| {{yes}}

| Wishbone

|

| [http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm LatticeMico32]

| Verilog

| Alex Kuznetsov

| {{yes|MIT}}

| Wishbone

| 32-bit, 3-stage pipeline, register file based on block RAM

| [https://lxp32.github.io/ lxp32]

| VHDL

| MicroCore Labs

| {{yes}}

| Ultra-small-footprint microsequencer-based 6502 core

| 252 Spartan-7 LUTs. Clock cycle-exact.

| [https://github.com/MicroCoreLabs/Projects MCL65 Core]

|

| Marcus Geelnard

| {{yes}}

| Wishbone, B4/pipelined

| 32-bit RISC/Vector CPU implementing the MRISC32 ISA

| [https://mrisc32.bitsnbites.eu/ MRISC32]

| VHDL

| Stephan Nolting

| {{yes}}

| Wishbone (Avalon, AXI4-Lite)

| 16-bit MSP430 ISA-compatible, very small size, many peripherals, highly customizable

| [https://github.com/stnolting/neo430 NEO430]

| VHDL

| Altera

| {{no}}

| Avalon

|

| [https://web.archive.org/web/20101225092752/http://www.altera.com/products/ip/processors/nios2/ni2-index.html Altera Nios II]

| Verilog

| OpenCores

| {{yes}}

| Wishbone

| 32-bit; done in ASIC, Actel, Altera, Xilinx FPGA.

| [https://openrisc.io/]

| Verilog

| TU Darmstadt / TU Dresden

| {{Yes}}

| Custom (AXI support in development)

| 18-bit ISA (GNU Binutils / GCC support in development)

| [http://www.spartanmc.de SpartanMC]

| Verilog

| Miguel Angel Ajo Pelayo

| {{yes|MIT}}

|

| PIC12F compatible, program synthesised in gates

| [http://projects.nbee.es/display/IPCORES/SYNPIC12+8bit+RISC+CPU+core nbee.es]

| VHDL

| Jan Gray

| {{no}}

| XSOC abstract bus

| 16-bit RISC CPU and SoC featured in Circuit Cellar Magazine #116-118

| [http://www.fpgacpu.org/xsoc/index.html XSOC/xr16]

| Schematic

| Yann Guidon

| {{yes|AGPLv3}}

| Direct SRAM

| 16 or 32 bits, RTL in [https://web.archive.org/web/20121207045204/http://yasep.org/VHDL/ VHDL] & [http://yasep.org/#!ASM/impASM#examples/keywords.yas asm] in JS, microcontroller subset : ready

| [http://yasep.org yasep.org] ([http://www.mozilla.com/ Firefox] required)

| VHDL

| [http://zipcpu.com/about/gisselquist-technology.html Gisselquist Technology]

| {{yes|GPLv3}}

| Wishbone, B4/pipelined

| 32-bit CPU targeted for minimal FPGA resource usage

| [http://zipcpu.com/about/zipcpu.html zipcpu.com]

| Verilog

| Zylin AS

| {{yes}}

| Wishbone

| Stack based CPU, configurable 16/32 bit datapath, eCos support

| [http://opensource.zylin.com/zpu.htm Zylin CPU]

| VHDL

|Niklaus Wirth| Niklaus Wirth

| {{yes}}

|Custom

|Running a complete graphical Oberon System including an editor and compiler. Software can be developed and ran on the same FPGA board.

|[http://www.projectoberon.com/ www.projectoberon.com/]

|Verilog