AArch64#ARMv9-A

• 64-bit:
• Execution state: AArch64.
• Instruction sets: A64.
• 32-bit:
• Execution state: AArch32.
• Instruction sets: A32 + T32.
• Example: ARMv8-R, Cortex-A32.{{cite web|url=https://www.arm.com/products/processors/cortex-a/cortex-a32-processor.php|title=Cortex-A32 Processor – ARM|access-date=18 December 2016}}

• New instruction set, A64:
• Has 31 general-purpose 64-bit registers.
• Has dedicated zero or stack pointer (SP) register (depending on instruction).
• The program counter (PC) is no longer directly accessible as a register.
• Instructions are still 32 bits long and mostly the same as A32 (with LDM/STM instructions and most conditional execution dropped).
• Has paired loads/stores (in place of LDM/STM).
• No predication for most instructions (except branches).
• Most instructions can take 32-bit or 64-bit arguments.
• Addresses assumed to be 64-bit.
• Advanced SIMD{{anchor|SIMD}} (Neon) enhanced:
• Has 32 × 128-bit registers (up from 16), also accessible via VFPv4.
• Supports double-precision floating-point format.
• Fully IEEE 754 compliant.
• AES encrypt/decrypt and SHA-1/SHA-2 hashing instructions also use these registers.
• A new exception system:
• Fewer banked registers and modes.
• Memory translation from 48-bit virtual addresses based on the existing Large Physical Address Extension (LPAE), which was designed to be easily extended to 64-bit.

Extension: Data gathering hint (ARMv8.0-DGH).

AArch64 was introduced in ARMv8-A and is included in subsequent versions of ARMv8-A, and in all versions of ARMv9-A. It was also introduced in ARMv8-R as an option, after its introduction in ARMv8-A; it is not included in ARMv8-M.

The main opcode for selecting which group an A64 instruction belongs to is at bits 25–28.

{{See also|Comparison of ARMv8-A processors}}

File:ARMCortexA57A53.jpg/A53 MPCore big.LITTLE CPU chip]]

Announced in October 2011,{{cite press release|url=https://www.arm.com/about/newsroom/arm-discloses-technical-details-of-the-next-version-of-the-arm-architecture.php|title=ARM Discloses Technical Details Of The Next Version Of The ARM Architecture|date=27 October 2011|publisher=Arm Holdings|access-date=20 September 2013|archive-url=https://web.archive.org/web/20190101024118/https://www.arm.com/about/newsroom/arm-discloses-technical-details-of-the-next-version-of-the-arm-architecture.php|archive-date=1 January 2019}} ARMv8-A represents a fundamental change to the ARM architecture. It adds an optional 64-bit execution state, named "AArch64", and the associated new "A64" instruction set, in addition to a 32-bit execution state, "AArch32", supporting the 32-bit "A32" (original 32-bit Arm) and "T32" (Thumb/Thumb-2) instruction sets. The latter instruction sets provide user-space compatibility with the existing 32-bit ARMv7-A architecture. ARMv8-A allows 32-bit applications to be executed in a 64-bit OS, and a 32-bit OS to be under the control of a 64-bit hypervisor.{{cite web | url=https://www.arm.com/files/downloads/ARMv8_Architecture.pdf | title=ARMv8-A Technology Preview | year=2011 | access-date=31 October 2011 | first=Richard | last=Grisenthwaite | archive-date=11 November 2011 | archive-url=https://web.archive.org/web/20111111161327/https://www.arm.com/files/downloads/ARMv8_Architecture.pdf | url-status=dead }} ARM announced their Cortex-A53 and Cortex-A57 cores on 30 October 2012.{{cite press release | url=https://www.arm.com/about/newsroom/arm-launches-cortex-a50-series-the-worlds-most-energy-efficient-64-bit-processors.php | title=ARM Launches Cortex-A50 Series, the World's Most Energy-Efficient 64-bit Processors | publisher=Arm Holdings | access-date=31 October 2012}} Apple was the first to release an ARMv8-A compatible core (Cyclone) in a consumer product (iPhone 5S). AppliedMicro, using an FPGA, was the first to demo ARMv8-A.{{cite press release |url=https://www.businesswire.com/news/home/20111027006673/en/AppliedMicro-Showcases-World's-64-bit-ARM-v8-Core |title=AppliedMicro Showcases World's First 64-bit ARM v8 Core |publisher=AppliedMicro |date=28 October 2011 |access-date=11 February 2014}} The first ARMv8-A SoC from Samsung is the Exynos 5433 used in the Galaxy Note 4, which features two clusters of four Cortex-A57 and Cortex-A53 cores in a big.LITTLE configuration; but it will run only in AArch32 mode.{{cite web | title = Samsung's Exynos 5433 is an A57/A53 ARM SoC |publisher = AnandTech |url = https://www.anandtech.com/show/8537/samsungs-exynos-5433-is-an-a57a53-arm-soc | access-date = 17 September 2014}}

ARMv8-A includes the VFPv3/v4 and advanced SIMD (Neon) as standard features in both AArch32 and AArch64. It also adds cryptography instructions supporting AES, SHA-1/SHA-256 and finite field arithmetic.{{cite web|title=ARM Cortex-A53 MPCore Processor Technical Reference Manual: Cryptography Extension|url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0500e/CJHDEBAF.html|publisher=ARM|access-date=11 September 2016}}

An ARMv8-A processor can support one or both of AArch32 and AArch64; it may support AArch32 and AArch64 at lower Exception levels and only AArch64 at higher Exception levels.{{cite web|url=https://developer.arm.com/documentation/102412/0103/Execution-and-Security-states/Impact-of-implemented-Exception-levels|title=Impact of implemented Exception levels|work=Learn the architecture - AArch64 Exception Model|publisher=Arm}} For example, the ARM Cortex-A32 supports only AArch32,{{cite web|url=https://developer.arm.com/Processors/Cortex-A32|title=Cortex-A32|website=Arm Developer}} the ARM Cortex-A34 supports only AArch64,{{cite web|url=https://developer.arm.com/Processors/Cortex-A34|title=Cortex-A34|website=Arm Developer}} and the ARM Cortex-A72 supports both AArch64 and AArch32.{{cite web|url=https://developer.arm.com/Processors/Cortex-A72|title=Cortex-A72|website=Arm Developer}} An ARMv9-A processor must support AArch64 at all Exception levels, and may support AArch32 at EL0.

In December 2014, ARMv8.1-A,{{cite web |url=https://community.arm.com/groups/processors/blog/2014/12/02/the-armv8-a-architecture-and-its-ongoing-development |title=The ARMv8-A architecture and its ongoing development |first=David |last=Brash |date=2 December 2014 |access-date=23 January 2015}} an update with "incremental benefits over v8.0", was announced. The enhancements fell into two categories: changes to the instruction set, and changes to the exception model and memory translation.

Instruction set enhancements included the following:

• A set of AArch64 atomic read-write instructions.
• Additions to the Advanced SIMD instruction set for both AArch32 and AArch64 to enable opportunities for some library optimizations:
• Signed Saturating Rounding Doubling Multiply Accumulate, Returning High Half.
• Signed Saturating Rounding Doubling Multiply Subtract, Returning High Half.
• The instructions are added in vector and scalar forms.
• A set of AArch64 load and store instructions that can provide memory access order that is limited to configurable address regions.
• The optional CRC instructions in v8.0 become a requirement in ARMv8.1.

Enhancements for the exception model and memory translation system included the following:

• A new Privileged Access Never (PAN) state bit provides control that prevents privileged access to user data unless explicitly enabled.
• An increased VMID range for virtualization; supports a larger number of virtual machines.
• Optional support for hardware update of the page table access flag, and the standardization of an optional, hardware updated, dirty bit mechanism.
• The Virtualization Host Extensions (VHE). These enhancements improve the performance of Type 2 hypervisors by reducing the software overhead associated when transitioning between the Host and Guest operating systems. The extensions allow the Host OS to execute at EL2, as opposed to EL1, without substantial modification.
• A mechanism to free up some translation table bits for operating system use, where the hardware support is not needed by the OS.
• Top byte ignore for memory tagging.{{Cite web|url=https://en.wikichip.org/wiki/arm/tbi|title=Top-byte ignore (TBI)|website=WikiChip}}

ARMv8.2-A was announced in January 2016.{{cite web|url=https://community.arm.com/groups/processors/blog/2016/01/05/armv8-a-architecture-evolution|title=ARMv8-A architecture evolution|first=David|last=Brash|date=5 January 2016|access-date=7 June 2016}} Its enhancements fall into four categories:

• Optional half-precision floating-point data processing (half-precision was already supported, but not for processing, just as a storage format.)
• Memory model enhancements.
• Introduction of Reliability, Availability and Serviceability Extension (RAS Extension).
• Introduction of statistical profiling.

{{anchor|ARMv8-A SVE}}

The Scalable Vector Extension (SVE) is "an optional extension to the ARMv8.2-A architecture and newer" developed specifically for vectorization of high-performance computing scientific workloads.{{Cite news|url=https://community.arm.com/processors/b/blog/posts/technology-update-the-scalable-vector-extension-sve-for-the-armv8-a-architecture|title=The scalable vector extension sve for the ARMv8 a architecture|work=Arm Community|access-date=8 July 2018|language=en|date=22 August 2016}}{{Cite web|url=https://gcc.gnu.org/gcc-8/changes.html|title=GCC 8 Release Series – Changes, New Features, and Fixes – GNU Project – Free Software Foundation (FSF)|website=gcc.gnu.org|language=en|access-date=9 July 2018}} The specification allows for variable vector lengths to be implemented from 128 to 2048 bits. The extension is complementary to, and does not replace, the NEON extensions.

A 512-bit SVE variant has already been implemented on the Fugaku supercomputer using the Fujitsu A64FX ARM processor; this computer{{Cite press release|url=https://www.fujitsu.com/global/about/resources/news/press-releases/2018/0621-01.html|title=Fujitsu Completes Post-K Supercomputer CPU Prototype, Begins Functionality Trials – Fujitsu Global|website=www.fujitsu.com|language=en|access-date=8 July 2018}} was the fastest supercomputer in the world for two years, from June 2020{{Cite press release|title=Japan's Fugaku gains title as world's fastest supercomputer|url=https://www.riken.jp/en/news_pubs/news/2020/20200623_1/index.html |date=23 June 2020 |access-date=7 December 2020 |publisher=www.riken.jp |language=en}} to May 2022.{{cite web |title=ORNL's Frontier First to Break the Exaflop Ceiling |url=https://www.top500.org/news/ornls-frontier-first-to-break-the-exaflop-ceiling/ |website=Top500 |date=30 May 2022 |access-date=30 May 2022 }} A more flexible version, 2x256 SVE, was implemented by the AWS Graviton3 ARM processor.

SVE is supported by GCC, with GCC 8 supporting automatic vectorization and GCC 10 supporting C intrinsics. {{as of|July 2020}}, LLVM and clang support C and IR intrinsics. ARM's own fork of LLVM supports auto-vectorization.{{cite web |title=⚙ D71712 Downstream SVE/SVE2 implementation (LLVM) |url=https://reviews.llvm.org/D71712 |website=reviews.llvm.org}}

In October 2016, ARMv8.3-A was announced. Its enhancements fell into six categories:{{cite web|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-a-architecture-2016-additions|title=ARMv8-A architecture – 2016 additions|author=David Brash|date=26 October 2016}}

• Pointer authentication (PAC){{cite web |url=https://patches.linaro.org/patch/90145/ |title=[Ping~,AArch64] Add commandline support for -march=armv8.3-a |quote=pointer authentication extension is defined to be mandatory extension on ARMv8.3-A and is not optional}}{{cite web |url=https://learn.arm.com/learning-paths/servers-and-cloud-computing/pac/pac/ |title=Pointer Authentication on Arm |publisher=ARM |access-date=5 March 2025}} (AArch64 only); mandatory extension (based on a new block cipher, QARMA{{cite web|url=https://www.qualcomm.com/news/onq/2017/01/10/qualcomm-releases-whitepaper-detailing-pointer-authentication-armv83|title=Qualcomm releases whitepaper detailing pointer authentication on ARMv8.3|date=10 January 2017}}) to the architecture (compilers need to exploit the security feature, but as the instructions are in NOP space, they are backwards compatible albeit providing no extra security on older chips).
• Nested virtualization (AArch64 only).
• Advanced SIMD complex number support (AArch64 and AArch32); e.g. rotations by multiples of 90 degrees.
• New FJCVTZS (Floating-point JavaScript Convert to Signed fixed-point, rounding toward Zero) instruction.{{cite web|url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100069_0610_00_en/hko1477562192868.html |title=A64 Floating-point Instructions: FJCVTZS |website=arm.com |access-date=11 July 2019}}
• A change to the memory consistency model (AArch64 only); to support the (non-default) weaker RCpc (Release Consistent processor consistent) model of C++11/C11 (the default C++11/C11 consistency model was already supported in previous ARMv8).
• ID mechanism support for larger system-visible caches (AArch64 and AArch32).

ARMv8.3-A architecture is now supported by (at least) the GCC 7 compiler.{{cite web|url=https://gcc.gnu.org/gcc-7/changes.html |title=GCC 7 Release Series – Changes, New Features, and Fixes |quote=The ARMv8.3-A architecture is now supported. It can be used by specifying the -march=armv8.3-a option. [..] The option -msign-return-address= is supported to enable return address protection using ARMv8.3-A Pointer Authentication Extensions.}}

In November 2017, ARMv8.4-A was announced. Its enhancements fell into these categories:{{Cite web|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/introducing-2017s-extensions-to-the-arm-architecture|title=Introducing 2017's extensions to the Arm Architecture|website=community.arm.com|date=2 November 2017 |language=en|access-date=15 June 2019}}{{Cite web|url=https://community.arm.com/developer/tools-software/tools/b/tools-software-ides-blog/posts/exploring-the-arm-dot-product-instructions|title=Exploring dot product machine learning|website=community.arm.com|date=6 December 2017 |language=en|access-date=15 June 2019}}{{Cite web|url=https://www.phoronix.com/scan.php?page=news_item&px=GCC-ARMv8.4-A-Patches|title=ARM Preps ARMv8.4-A Support For GCC Compiler – Phoronix|website=www.phoronix.com|language=en|access-date=14 January 2018}}

• "SHA3 / SHA512 / SM3 / SM4 crypto extensions." I.e. optional instructions.

• Improved virtualization support.
• Memory Partitioning and Monitoring (MPAM) capabilities.
• A new Secure EL2 state and Activity Monitors.
• Signed and unsigned integer dot product (SDOT and UDOT) instructions.

{{anchor|ARMv8.5-A|ARMv9.0-A}}

In September 2018, ARMv8.5-A was announced. Its enhancements fell into these categories:{{Cite web | url=https://developer.arm.com/documentation/102378/0201/ARMv8-x-and-ARMv9-x-extensions-and-features | title=ARMv8.x and ARMv9.x extensions and features | work=Learn the architecture: Understanding the ARMv8.x and ARMv9.x extensions}}{{Cite web|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-a-profile-architecture-2018-developments-armv85a|title=Arm Architecture ARMv8.5-A Announcement – Processors blog – Processors – Arm Community|website=community.arm.com|language=en|access-date=26 April 2019}}{{Cite web|url=https://developer.arm.com/docs/ddi0487/ea|title=Arm Architecture Reference Manual ARMv8, for ARMv8-A architecture profile|website=ARM Developer|language=en|access-date=6 August 2019}}

• Memory Tagging Extension (MTE) (AArch64).{{Cite web|title=Arm MTE architecture: Enhancing memory safety|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/enhancing-memory-safety|access-date=27 July 2021|website=community.arm.com|date=5 August 2019 |language=en}}
• Branch Target Indicators (BTI) (AArch64) to reduce "the ability of an attacker to execute arbitrary code". Like pointer authentication, the relevant instructions are no-ops on earlier versions of ARMv8-A.
• Random Number Generator instructions – "providing Deterministic and True Random Numbers conforming to various National and International Standards".

On 2 August 2019, Google announced Android would adopt Memory Tagging Extension (MTE).{{Cite web|url=https://security.googleblog.com/2019/08/adopting-arm-memory-tagging-extension.html|title=Adopting the Arm Memory Tagging Extension in Android|website=Google Online Security Blog|language=en|access-date=6 August 2019}}

{{anchor|ARMv9-A}}

In March 2021, ARMv9-A was announced. ARMv9-A's baseline is all the features from ARMv8.5.{{Cite web|title=Arm's solution to the future needs of AI, security and specialized computing is v9|url=https://www.arm.com/company/news/2021/03/arms-answer-to-the-future-of-ai-armv9-architecture|access-date=27 July 2021|website=Arm {{!}} The Architecture for the Digital World|language=en}}{{Cite web|last=Schor|first=David|date=30 March 2021|title=Arm Launches ARMv9|url=https://fuse.wikichip.org/news/4646/arm-launches-armv9/|access-date=27 July 2021|website=WikiChip Fuse|language=en-US}}{{Cite web|last=Frumusanu|first=Andrei|title=Arm Announces ARMv9 Architecture: SVE2, Security, and the Next Decade|url=https://www.anandtech.com/show/16584/arm-announces-armv9-architecture|access-date=27 July 2021|website=www.anandtech.com}} ARMv9-A also adds:

• Scalable Vector Extension 2 (SVE2). SVE2 builds on SVE's scalable vectorization for increased fine-grain Data Level Parallelism (DLP), to allow more work done per instruction. SVE2 aims to bring these benefits to a wider range of software including DSP and multimedia SIMD code that currently use Neon. The LLVM/Clang 9.0 and GCC 10.0 development codes were updated to support SVE2.{{Cite web|title=Arm SVE2 Support Aligning For GCC 10, LLVM Clang 9.0 – Phoronix|url=https://www.phoronix.com/scan.php?page=news_item&px=Arm-SVE2-GCC10-Clang9|access-date=26 May 2019|website=www.phoronix.com}}
• Transactional Memory Extension (TME). Following the x86 extensions, TME brings support for Hardware Transactional Memory (HTM) and Transactional Lock Elision (TLE). TME aims to bring scalable concurrency to increase coarse-grained Thread Level Parallelism (TLP), to allow more work done per thread.{{Cite web|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/new-technologies-for-the-arm-a-profile-architecture|title=Arm releases SVE2 and TME for A-profile architecture – Processors blog – Processors – Arm Community|website=community.arm.com|date=18 April 2019 |language=en|access-date=25 May 2019}} The LLVM/Clang 9.0 and GCC 10.0 development codes were updated to support TME.
• Confidential Compute Architecture (CCA).{{Cite web|title=Unlocking the power of data with Arm CCA|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/unlocking-the-power-of-data-with-arm-cca|access-date=27 July 2021|website=community.arm.com|date=23 June 2021 |language=en}}{{Cite web|date=23 June 2021|title=Arm Introduces Its Confidential Compute Architecture|url=https://fuse.wikichip.org/news/5699/arm-introduces-its-confidential-compute-architecture/|access-date=27 July 2021|website=WikiChip Fuse|language=en-US}}

{{anchor|ARMv8.6-A|ARMv9.1-A}}

In September 2019, ARMv8.6-A was announced. Its enhancements fell into these categories:{{Cite web|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a|title=Arm A profile architecture update 2019|website=community.arm.com|date=25 September 2019 |language=en|access-date=26 September 2019}}

• General Matrix Multiply (GEMM).
• Bfloat16 format support.
• SIMD matrix manipulation instructions, BFDOT, BFMMLA, BFMLAL and BFCVT.
• Enhancements for virtualization, system management and security.
• And the following extensions (that LLVM 11 already added support for{{Cite web|url=https://releases.llvm.org/11.0.1/docs/ReleaseNotes.html|title=LLVM 11.0.0 Release Notes|access-date=11 March 2021|website=releases.llvm.org}}):
• Enhanced Counter Virtualization (ARMv8.6-ECV).
• Fine-Grained Traps (ARMv8.6-FGT).
• Activity Monitors virtualization (ARMv8.6-AMU).

For example, fine-grained traps, Wait-for-Event (WFE) instructions, EnhancedPAC2 and FPAC. The bfloat16 extensions for SVE and Neon are mainly for deep learning use.{{Cite web|url=https://community.arm.com/developer/ip-products/processors/b/ml-ip-blog/posts/bfloat16-processing-for-neural-networks-on-armv8_2d00_a|title=BFloat16 extensions for ARMv8-A|website=community.arm.com|date=29 August 2019 |language=en|access-date=30 August 2019}}

{{anchor|ARMv8.7-A|ARMv9.2-A}}

In September 2020, ARMv8.7-A was announced. Its enhancements fell into these categories:{{cite web |last1=Weidmann |first1=Martin |title=Arm A-Profile Architecture Developments 2020 |url=https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2020 |website=community.arm.com |publisher=ARM |access-date=28 September 2022 |date=21 September 2020}}

• Scalable Matrix Extension (SME)(ARMv9.2 only).{{Cite web|title=Scalable Matrix Extension for the ARMv9-A Architecture|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/scalable-matrix-extension-armv9-a-architecture|access-date=27 July 2021|website=community.arm.com|date=14 July 2021 |language=en}} SME adds new features to process matrices efficiently, such as:
• Matrix tile storage.
• On-the-fly matrix transposition.
• Load/store/insert/extract tile vectors.
• Matrix outer product of SVE vectors.
• "Streaming mode" SVE.
• Enhanced support for PCIe hot plug (AArch64).
• Atomic 64-byte load and stores to accelerators (AArch64).
• Wait For Interrupt (WFI) and Wait For Event (WFE) with timeout (AArch64).
• Branch-Record recording (ARMv9.2 only).
• Call Stack Recorder

{{anchor|ARMv8.8-A|ARMv9.3-A}}

In September 2021, ARMv8.8-A and ARMv9.3-A were announced. Their enhancements fell into these categories:{{cite web |last1=Weidmann |first1=Martin |title=Arm A-Profile Architecture Developments 2021 |url=https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2021 |website=community.arm.com |publisher=ARM |access-date=28 September 2022 |date=8 September 2021}}

• Non-maskable interrupts (AArch64).
• Instructions to optimize memcpy() and memset() style operations (AArch64).
• Enhancements to PAC (AArch64).
• Hinted conditional branches (AArch64).

LLVM 15 supports ARMv8.8-A and ARMv9.3-A.{{cite web |title=What is New in LLVM 15? - Architectures and Processors blog - Arm Community blogs - Arm Community |date=27 February 2023 |url=https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/llvm-15 |access-date=2023-04-15}}

{{anchor|ARMv8.9-A|ARMv9.4-A}}

In September 2022, ARMv8.9-A and ARMv9.4-A were announced, including:{{Cite web |title=Arm A-Profile Architecture Developments 2022 - Architectures and Processors blog - Arm Community blogs - Arm Community |url=https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022 |access-date=2022-12-09 |website=community.arm.com |date=29 September 2022 |language=en}}

• Virtual Memory System Architecture (VMSA) enhancements.
• Permission indirection and overlays.
• Translation hardening.
• 128-bit translation tables (ARMv9 only).
• Scalable Matrix Extension 2 (SME2) (ARMv9 only).
• Multi-vector instructions.
• Multi-vector predicates.
• 2b/4b weight compression.
• 1b binary networks.
• Range Prefetch.
• Guarded Control Stack (GCS) (ARMv9 only).
• Confidential Computing.
• Memory Encryption Contexts.
• Device Assignment.

{{anchor|ARMv9.5-A}}

In October 2023, ARMv9.5-A was announced, including:{{Cite web |title=Arm A-Profile Architecture Developments 2023 - Architectures and Processors blog - Arm Community blogs - Arm Community |url=https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023 |access-date=2024-10-14 |website=community.arm.com |date=5 October 2023 |language=en}}

• FP8 support (E5M2 and E4M3 formats) added to:
• SME2
• SVE2
• Advanced SIMD (Neon)
• Live migration of Virtual Machines using Hardware Dirty state tracking structures (FEAT_HDBSS)
• Checked Point Arithmetic
• Support for using a combination of the PC and SP as the modifier when generating or checking Pointer Authentication codes.
• Support for Realm Management Extension (RME) enabled designs, support for non-secure only in the Granule Protection Tables and the ability to disable certain Physical Address Spaces (PAS).
• EL3 configuration write-traps.
• Breakpoint support for address range and mismatch triggering without the need for linking.
• Support for efficiently delegating SErrors from EL3 to EL2 or EL1.

{{anchor|ARMv9.6-A}}

In October 2024, ARMv9.6-A was announced, including:{{Cite web |title=Arm A-Profile Architecture Developments 2024 - Architectures and Processors blog - Arm Community blogs - Arm Community |url=https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2024 |access-date=2024-10-14 |website=community.arm.com |date=1 October 2024 |language=en}}

• Improved SME efficiency with structured sparsity and quarter tile operations
• MPAM Domains to better support shared-memory computer systems on multi-chiplet and multi-chip systems
• Hypervisor memory control for Trace and Statistical Profiling on virtual machines
• Improved Caching and Data Placement
• Granular Data Isolation for Confidential Compute
• Bitwise locking of EL1 system registers
• Improved scaling of Granular Protection Tables (GPT) for large memory systems
• New SVE instructions for expand/compact and finding first/last active element
• Additional unprivileged load and store instructions to enable OS to interact with application memory
• New compare and branch instruction
• Injection of Undefined-Instruction exceptions from EL3

{{Expand section|1=examples and additional citations|section=1|date=May 2021|small=no|talksection=Talk:AArch64}}

The ARM-R architecture, specifically the Armv8-R profile, is designed to address the needs of real-time applications, where predictable and deterministic behavior is essential. This profile focuses on delivering high performance, reliability, and efficiency in embedded systems where real-time constraints are critical.

With the introduction of optional AArch64 support in the Armv8-R profile, the real-time capabilities have been further enhanced. The Cortex-R82{{cite web |last=Frumusanu |first=Andrei |date=3 September 2020 |title=ARM Announced Cortex-R82: First 64-bit Real Time Processor |url=https://www.anandtech.com/show/16056/arm-announces-cortexr82-first-64bit-real-time-processor |website=AnandTech}} is the first processor to implement this extended support, bringing several new features and improvements to the real-time domain.{{cite web |title=Arm Architecture Reference Manual Supplement - Armv8, for Armv8-R AArch64 architecture profile |url=https://developer.arm.com/documentation/ddi0600/ac |publisher=Arm Ltd.}}

1. AArch64 Instruction Set (A64):
2. * The A64 instruction set in the Cortex-R82 provides 64-bit data handling and operations, which improves performance for certain computational tasks and enhances overall system efficiency.
3. * Example Instruction: ADD X0, X1, X2 adds the values in 64-bit registers X1 and X2 and stores the result in X0. This 64-bit operation allows for larger and more complex calculations compared to the 32-bit operations of the previous A32 instruction set.
4. Enhanced Memory Management:
5. * Memory Barrier Instructions: The Cortex-R82 introduces improved memory barrier instructions to ensure proper ordering of memory operations, which is critical in real-time systems where the timing of memory operations must be strictly controlled.{{Cite web |title=Cortex-R82 Technical Reference Manual |url=https://developer.arm.com/documentation/102670/0101}}
6. ** Data Synchronization Barrier (DSB): Ensures that all data accesses before the barrier are completed before continuing with subsequent operations.
7. ** Data Memory Barrier (DMB): Guarantees that all memory accesses before the barrier are completed before any memory accesses after the barrier can proceed.
8. * Example: In a real-time automotive control system, DSB might be used to ensure that sensor data is fully written to memory before the system proceeds with processing or decision-making, preventing data corruption or inconsistencies.
9. Improved Address Space:
10. * 64-bit Addressing: AArch64 allows the Cortex-R82 to address a much larger memory space compared to its 32-bit predecessors, making it suitable for applications requiring extensive memory.
11. * Example: A complex industrial automation system can utilize the expanded address space to manage large data sets and buffers more efficiently, improving system performance and capability.
12. Real-Time Performance Enhancements:
13. * Interrupt Handling: With AArch64 support, the Cortex-R82 can handle interrupts with lower latency and improved predictability, crucial for real-time operations.
14. * Example: In a robotics application, the Cortex-R82's enhanced interrupt handling can ensure timely responses to external stimuli, such as changes in sensor data or control commands.

{{Reflist}}

• [https://developer.arm.com Arm Developer]

Category:Computer-related introductions in 2011

Category:ARM architecture

Category:64-bit computers