ARM Cortex-A520

{{Infobox CPU

|name=ARM Cortex-A520

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|produced-start=2023

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|soldby=

|designfirm=ARM Ltd.

|manuf1=

|cpuid=

|slowest=1.8 GHz

|fastest=2.27 GHz

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|l1cache={{Nowrap|64/128 KiB}}
{{Small|({{Nowrap|32/64 KiB}} I-cache with parity,
{{Nowrap|32/64 KiB}} D-cache) per core}}

|l2cache={{Nowrap|0–512 KiB}} {{Small|per complex}}

|l3cache={{Nowrap|256 KiB – 32 MiB}} {{Small|(optional)}}

|l4cache=

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|arch=ARMv9.2-A

|microarch=ARM Cortex-A520

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|pcode1=Hayes

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|predecessor=ARM Cortex-A510

|successor=ARM Cortex-A530

}}

The ARM Cortex-A520 is a "little" CPU core model from Arm{{Cite web |date=2023-05-28 |title=Arm Launches Next-Gen Efficiency Core; Cortex-A520 |url=https://fuse.wikichip.org/news/7527/arm-launches-next-gen-efficiency-core-cortex-a520/ |access-date=2023-09-16 |website=WikiChip Fuse |language=en-US}} unveiled in TCS23 (total compute solution) it serves as a successor to the CPU core ARM Cortex-A510{{Cite web |date=2023-05-29 |title=Arm Cortex-X4, A720, and A520: 2024 smartphone CPUs deep dive |url=https://www.androidauthority.com/arm-cortex-x4-explained-3328008/ |access-date=2023-06-05 |website=Android Authority |language=en}}. The Cortex-A5xx CPU cores series generally focus on high efficiency, the CPU core can be paired with the other CPU cores in its family like ARM Cortex-A720 or/and Cortex-X4 in a CPU cluster.{{Cite web |title=Cortex-A520 |url=https://developer.arm.com/Processors/Cortex-A520 |access-date=2023-09-16 |website=developer.arm.com}}

Improvements

8% peak performance improvement over the Cortex-A510{{Cite web |last=Bonshor |first=Gavin |title=Arm Unveils 2023 Mobile CPU Core Designs: Cortex-X4, A720, and A520 - the ARMv9.2 Family |url=https://www.anandtech.com/show/18871/arm-unveils-armv92-mobile-architecture-cortex-x4-a720-and-a520-64bit-exclusive |access-date=2023-05-30 |website=www.anandtech.com}}
Support only 64-bit applications
Up to 512 KiB of private L2 cache (From 256 KiB)
Add QARMA3 Pointer Authentication (PAC) algorithm support
Update to ARMv9.2{{Cite web |last=Ltd |first=Arm |title=Cortex-A520 |url=https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a520 |access-date=2023-06-05 |website=Arm {{!}} The Architecture for the Digital World |language=en}}

Architecture comparison

:;"LITTLE" core

class="wikitable sortable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 100%; text-align:center; !uArch !Cortex-A53 !Cortex-A55 !Cortex-A510 !Cortex-A520 !Cortex-A530
Codename \| Apollo \| Ananke \| Klein \| Hayes \| Nevis
Peak clock speed \|2.3 GHz \|2.1 GHz \|2.0 GHz \|2.0 GHz \| -
Architecture \|ARMv8.0-A \|ARMv8.2-A \|ARMv9.0-A \|colspan="2" \|ARMv9.2-A
AArch \| colspan="3" \|32-bit and 64-bit \| colspan="2" \|64-bit
Branch predictor history (entries) \|3072{{Cite web \|date=2023-05-28 \|title=ARM’s Cortex A53: Tiny But Important \|url=https://chipsandcheese.com/2023/05/28/arms-cortex-a53-tiny-but-important/ \|access-date=2023-06-14 \|website=Chips and Cheese \|language=en-US}} \| colspan="4" \| -
Max In-flight \| colspan="5" \|None (In-order)
L0 (Mops entries) \| colspan="5" \|None
L1-I + L1-D \|8/64+8/64 KiB \|16/64+16/64 KiB \| colspan="2" \|32/64+32/64 KiB \| -
L2 \| colspan="2" \|0–256 KiB \| colspan="2" \|0–512 KiB \| -
L3 \|None \|0–4 MiB \|0–16 MiB \|0–32 MiB \| -
Decode Width \| colspan="2" \|2 \|3 \|3 (2 ALU) \| -
Dispatch \| colspan="2" \|8{{Cite web \|date=2017-05-31 \|title=A closer look at ARM’s new Cortex-A75 and Cortex-A55 CPUs \|url=https://www.androidauthority.com/arm-cortex-a75-cortex-a55-breakdown-770380/ \|access-date=2023-06-05 \|website=Android Authority \|language=en}} \| \| \|

class="wikitable sortable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 100%; text-align:center;

!uArch

Codename

| Apollo

| Ananke

| Klein

| Hayes

| Nevis

Peak clock speed

|2.3 GHz

|2.1 GHz

|2.0 GHz

| -

Architecture

|ARMv8.0-A

|ARMv8.2-A

|ARMv9.0-A

|colspan="2" |ARMv9.2-A

AArch

| colspan="3" |32-bit and 64-bit

| colspan="2" |64-bit

Branch predictor
history (entries)

|3072{{Cite web |date=2023-05-28 |title=ARM’s Cortex A53: Tiny But Important |url=https://chipsandcheese.com/2023/05/28/arms-cortex-a53-tiny-but-important/ |access-date=2023-06-14 |website=Chips and Cheese |language=en-US}}

| colspan="4" | -

Max In-flight

| colspan="5" |None (In-order)

L0 (Mops entries)

| colspan="5" |None

L1-I + L1-D

|8/64+8/64 KiB

|16/64+16/64 KiB

| colspan="2" |32/64+32/64 KiB

| -

| colspan="2" |0–256 KiB

| colspan="2" |0–512 KiB

| -

|None

|0–4 MiB

|0–16 MiB

|0–32 MiB

| -

Decode Width

| colspan="2" |2

|3 (2 ALU)

| -

Dispatch

| colspan="2" |8{{Cite web |date=2017-05-31 |title=A closer look at ARM’s new Cortex-A75 and Cortex-A55 CPUs |url=https://www.androidauthority.com/arm-cortex-a75-cortex-a55-breakdown-770380/ |access-date=2023-06-05 |website=Android Authority |language=en}}

References

Category:ARM processors

ARM Cortex-A520

Improvements

Architecture comparison

See also

References