List of Intel chipsets#5/6/7/8/9 Series chipsets

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{{Multiple issues|{{Overly detailed|date=May 2023}}

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File:Pentium E2220 with Intel i945GC Chipset.jpg with Pentium Dual-Core microprocessor]]

This article provides a list of motherboard chipsets made by Intel, divided into three main categories: those that use the PCI bus for interconnection (the 4xx series), those that connect using specialized "hub links" (the 8xx series), and those that connect using PCI Express (the 9xx series). The chipsets are listed in chronological order.

Pre-chipset situation

An earlier chipset support for Intel 8085 microprocessor can be found at MCS-85 family section.

Early IBM XT-compatible mainboards did not yet have a chipset, but relied instead on a collection of discrete TTL chips by Intel:{{cite book|title=PC Based Instrumentation and Control|url=https://archive.org/details/pcbasedinstrumen00bami_789|url-access=limited|author=Michael H. Tooley |page=[https://archive.org/details/pcbasedinstrumen00bami_789/page/n48 32] |publisher=Elsevier |date=2005 |isbn=9780750647168}}

  • the 8284 clock generator
  • the 8288 bus controller
  • the 8254 programmable interval timer
  • the 8255 parallel I/O interface
  • the 8259 programmable interrupt controller
  • the 8237 DMA controller

Early chipsets

To integrate the functions needed on a mainboard into a smaller number of ICs, Intel licensed the ZyMOS POACH chipset for its Intel 80286 and Intel 80386SX processors (the 82230/82231 High Integration AT-Compatible Chip Set). The 82230 covers this combination of chips: 82C284 clock, 82288 bus controller, and dual 8259A interrupt controllers among with other components. The 82231 covers this combination of chips: 8254 interrupt timer, 74LS612 memory mapper and dual 8237A DMA controller among with other components. Both set were available US$60 for 10 MHz version and US$90 for 12 MHz version in quantities of 100.Ormsby, John, Editor, "New Product Focus: Components: Intel's 82X3X Chip-set Handles Logic Functions That Once Required The Services Of Sources Of Chips", Intel Corporation, Microcomputer Solutions, January/February 1988, page 13 This chipset can be used with an 82335 High-integration Interface Device to provide support for the Intel 386SX.Lewnes, Ann, "Welcome 80386SX", Microcomputer Solutions, September/October 1988, page 2

List of early Intel chipset includes:{{cite web |url=ftp://download.intel.com/museum/research/arc_collect/timeline/TimelineDateSort7_05.pdf |title=Archived copy |access-date=2008-09-02 |url-status=dead |archive-url=https://web.archive.org/web/20080910041059/http://download.intel.com/museum/research/arc_collect/timeline/TimelineDateSort7_05.pdf |archive-date=2008-09-10 }}{{cite web

| title = Time Line 1980-1989

| url = http://www.intel-vintage.com/timeline19801989.htm

| access-date = 2012-01-14

| archive-url = https://web.archive.org/web/20120113013236/http://www.intel-vintage.com/timeline19801989.htm

| archive-date = 2012-01-13

| url-status = dead

}}

  • 82077AA CHMOS Single-Chip Floppy Disk Controller for the 32-bit systems.[http://www.bitsavers.org/components/intel/_dataSheets/290410-001_82077SL_Floppy_Disk_Controller_May91.pdf Intel Corporation, "82077SL CHMOS Single-Chip Floppy Disk Controller", May 1991, Order Number: 290410-001]Chen, Allan, "The 386 SL Microprocessor Superset: The 32-bit Notebook Hits the Road", Intel Corporation, Microcomputer Solutions, January/February 1991, page 2
  • 82091AA EISA/ISA - Advanced Integrated Peripheral (AIP), includes: floppy disk controller, 2× UARTs, parallel port, IDE controller, oscillator, etc.{{cite web |title=82091AA ADVANCED INTEGRATED PERIPHERAL (AIP) |url=http://www.intel.com/design/archives/periphrl/docs/29048603.htm |access-date=2013-08-02 |archive-url=https://web.archive.org/web/20140116221203/http://www.intel.com/design/archives/periphrl/docs/29048603.htm |archive-date=2014-01-16 |url-status=live }}
  • 82310 MCA family chipset - announced in April 1988.{{Cite news

| title = PS/2 Model 80 Clones Based on Intel Chipset

| first1 = Tom

| last1 = Moran

| newspaper = InfoWorld

| date = April 25, 1988

| page = 1

| url = https://books.google.com/books?id=pj0EAAAAMBAJ

| access-date = October 15, 2016

| archive-url = https://web.archive.org/web/20140627025936/http://books.google.com/books?id=pj0EAAAAMBAJ

| archive-date = June 27, 2014

| url-status = live

}} This chipset also supports the 80386SX based machines as well. Which it does includes:{{cite web|url=https://archive.org/details/bitsavers_inteldataBrocessorandPeripheralHandbookVol1_114989017|title=1989 Intel Microprocessor and Peripheral Handbook Vol 1|work=Internet Archive|access-date=2016-08-18|archive-url=https://web.archive.org/web/20160703235950/https://archive.org/details/bitsavers_inteldataBrocessorandPeripheralHandbookVol1_114989017|archive-date=2016-07-03|url-status=live}}Intel Corporation, "NewsBit: Intel Technology Powers New Tandy PC", Microcomputer Solutions, July/August 1988, page 1

  • 82306 Local Channel Support Chip
  • 82307 DMA Controller/Central Arbiter
  • 82308 Micro Channel Bus Controller
  • 82309 Address Bus Controller
  • 82706 VGA Graphics Controller
  • 82311 MCA - announced in November 1988.{{Cite news

| title = MCA Multiprocessing In the Works at Intel

| first1 = Martin

| last1 = Marshall

| newspaper = InfoWorld

| date = November 14, 1988

| page = 1

| url = https://books.google.com/books?id=wTsEAAAAMBAJ

| access-date = October 15, 2016

| archive-url = https://web.archive.org/web/20170227013930/https://books.google.com/books?id=wTsEAAAAMBAJ

| archive-date = February 27, 2017

| url-status = live

}}{{cite web

| title = Intel Introduces the Second Generation Micro Channel Chip Set

| date = November 29, 1988

}} Includes: 82303 and 82304 Local I/O Channel Support Chips, 82307 DMA Controller/Central Arbiter, 82308 Micro Channel Bus Controller, 82309 Address Bus Controller, 82706 VGA Graphics Controller, 82077 Floppy Disk Controller.{{Cite news

| title = Uncorking the future

| first1 = Mark

| last1 = Brownstein

| newspaper = InfoWorld

| date = November 13, 1989

| page = 101

| url = https://books.google.com/books?id=sTAEAAAAMBAJ

| access-date = October 15, 2016

| archive-url = https://web.archive.org/web/20140627030045/http://books.google.com/books?id=sTAEAAAAMBAJ

| archive-date = June 27, 2014

| url-status = live

}}

  • 82320 MCA - announced in April 1989.{{Cite news

| title = Intel Adds Low-Power 386SX To List of Chip Announcements

| first1 = Ron

| last1 = Copeland

| newspaper = InfoWorld

| date = April 17, 1989

| page = 105

| url = https://books.google.com/books?id=CDoEAAAAMBAJ

| access-date = October 15, 2016

| archive-url = https://web.archive.org/web/20140627030632/http://books.google.com/books?id=CDoEAAAAMBAJ

| archive-date = June 27, 2014

| url-status = live

}} This chipset supports the i486 microprocessor. It was expected to be available in the later half of 1989.

  • 82340SX PC AT - announced in January 1990, it is the Topcat chipset licensed from VLSI.{{Cite news

| title = Intel to Market VLSI Topcat Chips

| first1 = Ron

| last1 = Copeland

| newspaper = InfoWorld

| date = January 8, 1990

| page = 3

| url = https://books.google.com/books?id=dzAEAAAAMBAJ

| access-date = October 15, 2016

| archive-url = https://web.archive.org/web/20140627030754/http://books.google.com/books?id=dzAEAAAAMBAJ

| archive-date = June 27, 2014

| url-status = live

}}

  • 82340DX PC AT - announced in January 1990, it is the Topcat chipset licensed from VLSI.
  • 82350 EISA - announced in September 1988.{{Cite news

| title = New EISA Features Set It Apart From the AT Bus

| first1 = Tom

| last1 = Moran

| first2 = Ed

| last2 = Scannel

| newspaper = InfoWorld

| date = September 26, 1988

| page = 23

| url = https://books.google.com/books?id=kDoEAAAAMBAJ

| access-date = October 15, 2016

| archive-url = https://web.archive.org/web/20140627025440/http://books.google.com/books?id=kDoEAAAAMBAJ

| archive-date = June 27, 2014

| url-status = live

}} This chipset supports the i486 microprocessor. It was expected to be available in the later half of 1989.Intel Corporation, "NewsBits: Intel Introduces EISA and MCA Support for i486 Microprocessor", Microcomputer Solutions, July/August 1989, page 1

  • 82350DT EISA - announced in April 1991.{{Cite news

| title = Intel Debuts EISA Chip Set for Lower Cost 32-Bit Systems

| first1 = Louise

| last1 = Fickel

| newspaper = InfoWorld

| date = April 29, 1991

| page = 28

| url = https://books.google.com/books?id=y1AEAAAAMBAJ

| access-date = October 15, 2016

| archive-url = https://web.archive.org/web/20140627025609/http://books.google.com/books?id=y1AEAAAAMBAJ

| archive-date = June 27, 2014

| url-status = live

}} This version supports Intel486 DX2 CPU.Hodson, Gerri, "The Intel486 DX2 Microprocessor: Speed-Doubler Technology", Intel Corporation, Microcomputer Solutions, May/June 1992, page 2-5

  • 82360SL - announced in October 1990.{{Cite news

| title = Intel to Introduce 20-MHz Chip Set

| first1 = Nico

| last1 = Krohn

| newspaper = InfoWorld

| date = October 15, 1990

| page = 5

| url = https://books.google.com/books?id=LjwEAAAAMBAJ

| access-date = October 15, 2016

| archive-url = https://web.archive.org/web/20140627024041/http://books.google.com/books?id=LjwEAAAAMBAJ

| archive-date = June 27, 2014

| url-status = live

}} It was a chipset for the mobile 80386SL and 80486SL processors. It integrated DMA controller, an interrupt controller PIC, serial and parallel ports, I/O Control, NMI, Real Time Clock, Timers and power-management logic for the processor. This chipset contains 226,000 transistors using the one-micron CHMOS IV technology. It was available for US$45 in quantities of 1,000.

  • 82365SL - PC Card Interface Controller. This support PCMCIA 2.0 standard using the Exchangeable Card Architecture which supports both I/O and memory ExCA-compliant cards. It uses the Intel386SL power-management features. This was available for US$35 in samples of quantities of 1,000-unit.Intel Corporation, "New Product Focus: Components: First Exchangeable Plug-In Cards Support PCMCIA", Microcomputer Solutions, November/December 1991, page 11
  • 82380 - High Performance 32-Bit DMA Controller with Integrated System Support Peripherals. This chipset has 20-level programmable interrupt controller a superset of Intel's 82C59 PIC. It also has four (x4) 16-bit programmable internal timers which its superset Intel's 82C54 PIT. It also has built-in DRAM refresh controller as well. It is available for US$149 and US$299 for 16 MHz and 20 MHz respectively in quantities of 100.Intel Corporation, "New Product Focus Components: The 32-Bit Computing Engine Full Speed Ahead", Solutions, May/June 1987, page 10 The Intel M82380 met under MIL-STD-883 Rev. C standard. This military device was tested which includes temperature cycling between -55 and 125 °C, hermeticity and extended burn-in. This military version can have transfer rate of 32 Mbytes per seconds at 16 MHz. This military version were available in 132-lead CPGA and 164-lead CQPK. This military version were available for US$520 100-unit of quantities for the PGA version.Intel Corporation, "Focus: Components: Militarized Peripherals Support M386 Microprocessor", Microcomputer Solutions, March/April 1989, page 12
  • 82384 - Clock Generator. The available version for US$15 in quantities of 100.Intel Corporation, "New Product Focus Component: A 32-Bit Microprocessor With A Little Help From Some Friends", Special 32-Bit Issue Solutions, November/December 1985, page 13
  • 82385 - High Performance 32-Bit Cache Controller. This chipset was introduced in February 1987. It was available for 20 MHz version.Intel Corporation, "NewsBit: 80386 Computing Engine Now Complete", Microcomputer Solutions, November/December 1987, page 1 There is 33 MHz version available for the 386DX processor.Lewnes, Ann, "The Intel386 Architecture Here to Stay", Intel Corporation, Microcomputer Solutions, July/August 1989, page 2 Paired with 33 MHz 386 CPU and 64-Kbyte memory subsystem, it performed up to 7.8 MIPS.Intel Corporation, "New Product Focus: Components: 386 Smart Cache Reduces Subsystem to One Chip", Microcomputer Solutions, September/October 1990, page 10 There is 82385SX version for the 386SX microprocessor.
  • 82395DX - High Performance Smart Cache. This chipset contains internal 16-Kbye of SRAM and 1,000 cache tags. This controller supports up to 128-Kbytes of cache memory subsystem which it features four-way set associativity; a 16-byte line size; a four, double-word write buffer; and concurrent line-buffer caching. This also support write-buffer memory update protocol and maintains cache coherency during bus snooping. Paired with 33 MHz 386 CPU and the controller can perform up to 8.3 MIPS. This was available in 196-pin PQFP for US$90 and $109 for 25- and 33-MHZ version in quantites of 1000 respectively. There is Intel 82395SX version which it contains 8-Kbyte of cache memory for the 80386SX microprocessor family which it performs as much as 7% better than the 82385SX version. It was available for US$44 in quantities of 1000 units housed by 132-pin PQFP. The Intel 82396SX version contains 16-Kbyte of cache memory which were available in second quarter of 1991.Intel Corporation, "New Product Focus: Components: Two New Devices Extend Smart Cache Family", Microcomputer Solutions, March/April 1991, page 13

4xx chipsets

=80486 chipsets=

class="wikitable" style="font-size: 90%; text-align:center;"

!Chipset

Code NameNorth Bridge

!sSpec Number

South BridgeRelease DateProcessorsFSBSMPMemory typesMax. memoryMax. cacheableParity/ECCL2 Cache TypePCI support
420TXSaturnCDC (82424TX), DPU (82423TX)

|SZ839

SZ868

| rowspan="2" | SIO (System I/O)

November 1992V 486rowspan="2" | Up to 33 MHzrowspan="3" {{No}}rowspan="3" | FPM128 MB{{efn|reference=When applied to computer memory (RAM or cache) the quantities KB, MB and GB are defined as: 1 KB = 1024 B, 1 MB = 1024 KB, 1 GB = 1024 MB, consistent with the JEDEC memory standard.}}rowspan="3" {{Yes|Parity}}rowspan="3" | Async.1.0
420ZXSaturn IICDC (82424ZX), DPU (82423TX)

|SZ884

rowspan="2" | March 1994rowspan="2" | 5 V/3.3 V 486160 MB2.1
420EXAriesPSC (82425EX)

|SZ897 (PSC)

SZ898 (IB)

| IB (82426EX)

Up to 50 MHz128 MB128 MB (/w 32KB Tag Ram & 512KB L2 Cache[https://www.datasheetarchive.com/pdf/download.php?id=627c5536733eef9412c0b62885d1f092f1048d&type=P&term=82420EX Intel 420EX Aries Datasheet], Page #1122.0

== Other 80486 chipsets ==

  • 82495DX - Cache Controller. This support zero-wait-state with two-way set associative cache with several configurable parameters. This support MESI protocol and bus snooping. It is available for US$198.Chen, Allan, "The 50-MHz Intel486 Microprocessor", Intel Corporation, Microcomputer Solutions, September/October 1991, page 2
  • 82490DX - 32-Kbyte Dual Port Intelligent Cache SRAM. Providing second level write-back cache with dual-ported buffers and registers. It is available for US$41.

= Pentium chipsets =

While not an actual Intel chipset bug, the Mercury and Neptune chipsets could be found paired with RZ1000 and CMD640 IDE controllers with data corruption bugs. L2 caches are direct-mapped with SRAM tag RAM, write-back for 430FX, HX, VX, and TX.

class="wikitable" style="font-size: 90%; text-align:center;"
Chipset || Code Name || Part Numbers

!sSpec Number|| South Bridge || Release Date || Processors || FSB || SMP || Memory types || Max. memory || Max. cacheable || Parity/ECC || L2 Cache Type || PCI support || AGP support

430LXMercury[http://www.pcguide.com/ref/mbsys/chip/pop/g5iI430LX-c.html Intel 430LX ("Mercury")] {{Webarchive|url=https://web.archive.org/web/20071013123027/http://pcguide.com/ref/mbsys/chip/pop/g5iI430LX-c.html |date=2007-10-13 }}, PC Guide, accessed August 20, 2007.82434LX (PCMC)
2x 82433LX (LBX)

|SZ914 (PCMC)

SZ942 (LBX)

| SIO (ISA)
PCEB/ESC (EISA)

March 1993P60/6660/66 MHz{{No}}rowspan="2" | FPM192 MB192 MBrowspan="2" {{Partial|Parity}}rowspan="2" | Async.rowspan="4" | 2.0rowspan="7" {{No}}
430NXNeptune[http://www.pcguide.com/ref/mbsys/chip/pop/g5iI430NX-c.html Intel 430NX ("Neptune")] {{Webarchive|url=https://web.archive.org/web/20071013123041/http://pcguide.com/ref/mbsys/chip/pop/g5iI430NX-c.html |date=2007-10-13 }}, PC Guide, accessed August 20, 2007.82434NX (PCMC)
2x 82433NX (LBX)

|SZ919 (PCMC)

SZ899 (LBX)

| SIO (ISA)
SIO.A (DP ISA)
PCEB/ESC (EISA)

March 1994rowspan="6" | P75+rowspan="4" | 50/60/66 MHz{{Yes}}512 MB512 MB
430FXTriton[http://www.pcguide.com/ref/mbsys/chip/pop/g5iI430FX-c.html Intel 430FX ("Triton")] {{Webarchive|url=https://web.archive.org/web/20071013123014/http://pcguide.com/ref/mbsys/chip/pop/g5iI430FX-c.html |date=2007-10-13 }}, PC Guide, accessed August 20, 2007.[https://groups.google.com/group/comp.sys.intel/msg/0a0cd1fe2b61a6ff Summary of P5 chipsets] {{Webarchive|url=https://web.archive.org/web/20121104105131/http://groups.google.com/group/comp.sys.intel/msg/0a0cd1fe2b61a6ff |date=2012-11-04 }}, comp.sys.intel, September 1996.82437FX/JX (TSC)
2x 82438FX (TDP)

|SZ965 (A1)

SZ968 (A1)

SZ969

SZ973 (A1)

SZ975 (A1)

SZ998 (A2)

SZ999

| PIIX

January 1995rowspan="2" {{No}}rowspan="3" | FPM/EDOrowspan="2" | 128 MBrowspan="2" | 64 MBrowspan="2" {{No|Neither}}rowspan="5" | Async. / Pburst
430MXMobile Triton82437MX

|SU036 (A1)

SU037 (A1)

SU069 (B0)

| MPIIX

October 1995
430HXTriton II[http://www.pcguide.com/ref/mbsys/chip/pop/g5iI430HX-c.html Intel 430HX ("Triton II")] {{Webarchive|url=https://web.archive.org/web/20071013123022/http://pcguide.com/ref/mbsys/chip/pop/g5iI430HX-c.html |date=2007-10-13 }}, PC Guide, accessed August 20, 2007.82439HX/JHX (TXC)

|SU087 (A1)

SU102 (A2)

SU115

| rowspan="2" | PIIX3

rowspan="2" | February 1996{{Yes}}512 MB64 MB
512 MB (w/ 11-bit tag RAM)[http://www.pcguide.com/ref/mbsys/cache/charCacheability-c.html System RAM Cacheability] {{Webarchive|url=https://web.archive.org/web/20160817063724/http://www.pcguide.com/ref/mbsys/cache/charCacheability-c.html |date=2016-08-17 }}, PC Guide, accessed July 16, 2016.
{{Yes|Both}}rowspan="3" | 2.1
430VXTriton II[http://www.pcguide.com/ref/mbsys/chip/pop/g5iI430VX-c.html Intel 430VX ("Triton II", a.k.a. "Triton III")] {{Webarchive|url=https://web.archive.org/web/20070820211417/http://www.pcguide.com/ref/mbsys/chip/pop/g5iI430VX-c.html |date=2007-08-20 }}, PC Guide, accessed August 20, 2007.82437VX (TVX)
2x 82438VX (TDX)

|SU085 (A1)

SU116 (A2)

| rowspan="2" | 60/66 MHz

rowspan="2" {{No}}rowspan="2" | FPM/EDO/SDRAM128 MBrowspan="2" | 64 MBrowspan="2" {{No|Neither}}
430TX[http://www.pcguide.com/ref/mbsys/chip/pop/g5iI430TX-c.html Intel 430TX] {{Webarchive|url=https://web.archive.org/web/20070819184910/http://www.pcguide.com/ref/mbsys/chip/pop/g5iI430TX-c.html |date=2007-08-19 }}, PC Guide, accessed August 20, 2007.82439TX (MTXC)

|SL238 (A1)

SL28T (A2)

|PIIX4

February 1997256 MB

= Pentium Pro/II/III chipsets =

class="wikitable" style="font-size: 90%; text-align:center;"
rowspan="2" | Chipset || rowspan="2" | Code Name || rowspan="2" | Part numbers

! rowspan="2" |sSpec Number|| rowspan="2" | South Bridge || rowspan="2" | Release Date || rowspan="2" | Processors{{Efn|The Pentium Pro, Pentium II/III, and the Celerons based on them are essentially the same design with minor internal revisions and varying cache designs. Because of this, the same chipset can be used for Socket 8, Socket 370, Slot 1, or Slot 2 designs with any CPU in the P6 family. In practice however, newer chipset designs are usually made only for the newer processor packages, and older ones may not be updated to accommodate for recent package designs. In addition, certain chipsets may be implemented in motherboards with different processor packages, much like how the 440FX could be used either with a Pentium Pro (Socket 8) or Pentium II (Slot 1). A new feature for the latest Intel chipsets is hardware virtualization support (Intel VT-d).{{cite web |url=https://www.intel.com/technology/itj/2006/v10i3/2-io/1-abstract.htm |title=Ultrabook, SmartPhone, Laptop, Desktop, Server, & Embedded– Intel |publisher=Intel.com |access-date=2014-01-19 |archive-url=https://web.archive.org/web/20121013065422/http://www.intel.com/technology/itj/2006/v10i3/2-io/1-abstract.htm |archive-date=2012-10-13 |url-status=live }} The chipset support for this technology is not very clear for the moment.[https://software.intel.com/en-us/forums/virtualization-software-development/topic/56802/] {{webarchive |url=https://web.archive.org/web/20090314051946/https://software.intel.com/en-us/forums/virtualization-software-development/topic/56802/ |date=March 14, 2009 }}}} || rowspan="2" | FSB || rowspan="2" | SMP || colspan="3" | Memory || rowspan="2" | Parity/ECC || rowspan="2" | PCI support || rowspan="2" | AGP support

Type || Max. || Bank
450KXMars82451KX, 82452KX, 82453KX, 82454KX

|SU022 (A2)

SU024 (A2)

SU025 (A1)

SU026 (A1)

SU027 (A2)

SU028 (A2)

SU029 (A1)

SU030 (A2)

SU039 (A1)

SU040 (A1)

SU041 (A2)

SU042 (A2)

SU043 (A1)

SU044 (A2)

SU061 (A3)

SU062 (A4)

SU064 (A4)

| SIO, SIO.A, PIIX (ISA)
PCEB/ESC (EISA)

rowspan="2" | November 1995rowspan="2" | Pentium Prorowspan="3" | 60/66 MHz{{Yes}}rowspan="2" | FPMGBrowspan="4" {{Yes|Both}}rowspan="2" | 2.0rowspan="3" {{No}}
450GXOrion82451GX, 82452GX, 82453GX, 82454GX

|SU019 (A1)

SU055 (A1)

SU056 (A3)

SU057 (A3)

SU058 (A4)

SU059 (A4)

SU063 (A4)

SY050 (A4)

SY051 (A5)

SY052 (A6)

SY053 (A4)

SY054 (A6)

| SIO.A (ISA)
PCEB/ESC (EISA)

{{Yes}} (up to four)8 GB
440FXNatoma82441FX, 82442FX

|SU053 (A1)

SU054 (A1)

| PIIX3 (ISA)
PCEB/ESC (EISA)

May 1996Pentium Pro, Pentium IIrowspan="2" {{Yes}}FPM / EDO / BEDO1 GBrowspan="2" | 4rowspan="3" | 2.1
440LXBalboa82443LX

|SL2KK (A3)

SL2KN (A3)

| PIIX4

August 1997rowspan="2" | Pentium II, Celeronrowspan="2" | 66 MHzFPM / EDO / SDRAM1 GB EDO / 512 MB SDRAM{{Cite web |url=http://www.yc-zj.com:8084/dz/qt/%E7%94%B5%E8%84%91%E7%A1%AC%E4%BB%B6%E7%BB%B4%E4%BF%AE/%E4%B8%BB%E6%9D%BF%E7%BB%B4%E4%BF%AE%E8%A7%86%E9%A2%91/%E4%B8%BB%E6%9D%BF%E8%A7%86%E9%A2%918DVD%E4%B9%8B01%E7%BB%B4%E4%BF%AE%E8%B5%84%E6%96%99/%E4%B8%BB%E6%9D%BF%E8%8A%AF%E7%89%87%E7%BA%A7%E7%BB%B4%E4%BF%AEVCD7-%E4%B8%BB%E6%9D%BF%E7%94%B5%E8%B7%AF%E7%9B%981/INTEL%E8%8A%AF%E7%89%87%E7%BB%84%E8%B5%84%E6%96%99/440LX/II%20Processor.pdf |title=Archived copy |access-date=2017-12-14 |archive-url=https://web.archive.org/web/20171214182959/http://www.yc-zj.com:8084/dz/qt/%E7%94%B5%E8%84%91%E7%A1%AC%E4%BB%B6%E7%BB%B4%E4%BF%AE/%E4%B8%BB%E6%9D%BF%E7%BB%B4%E4%BF%AE%E8%A7%86%E9%A2%91/%E4%B8%BB%E6%9D%BF%E8%A7%86%E9%A2%918DVD%E4%B9%8B01%E7%BB%B4%E4%BF%AE%E8%B5%84%E6%96%99/%E4%B8%BB%E6%9D%BF%E8%8A%AF%E7%89%87%E7%BA%A7%E7%BB%B4%E4%BF%AEVCD7-%E4%B8%BB%E6%9D%BF%E7%94%B5%E8%B7%AF%E7%9B%981/INTEL%E8%8A%AF%E7%89%87%E7%BB%84%E8%B5%84%E6%96%99/440LX/II%20Processor.pdf |archive-date=2017-12-14 |url-status=dead }}rowspan="4" {{Yes|AGP 2×}}
440EX{{n/a}}82443EX

|SL2SA (A0)

SL2SB

| rowspan="6" | PIIX4E

rowspan="2" | April 1998{{No}}rowspan="2" | EDO / SDRAM256 MB2{{No|Neither}}
440BXSeattle82443BX

82443BXE

|SL278 (C1)

SL2T5 (B1)

SL2VH (C1) SL85Y

| Pentium II/III, Celeron

66/100 MHzrowspan="2" {{Yes}}512 MB (1 GB w/ Registered){{cite web |url=http://www.o3one.org/hwdocs/p2manuals/440BX_82443BX_29063301.pdf |title=BX_DS_10.book |access-date=2018-07-07 |archive-url=https://web.archive.org/web/20180707202358/http://www.o3one.org/hwdocs/p2manuals/440BX_82443BX_29063301.pdf |archive-date=2018-07-07 |url-status=live }}rowspan="3" | 4rowspan="3" {{Yes|Both}}2.1
440GXMarlinspike82443GX

|SL2TF (A0)

SL2VJ (A0)

| rowspan="2" | June 1998

rowspan="2" | Pentium II/III, Xeonrowspan="2" | 66/100 MHzSDRAM2 GB2.1
450NXrowspan="4" {{n/a}}82451NX, 82452NX, 82453NX, 82454NXSL2RU (B0)

SL2RV (B1)

SL2RW (B0)

SL2RX (B0)

SL2ZA (B1)

SL36R (C0)

| {{Yes}} (up to four)

FPM / EDO8 GB2.1 (64-bit optional){{No}}
440ZX-66rowspan="2" | 82443ZX

|SL37A

rowspan="2" | November 1998rowspan="2" | Celeron, Pentium II/III66 MHzrowspan="4" {{No}}rowspan="4" | SDRAMrowspan="2" | 512 MBrowspan="4" | 2rowspan="4" {{No|Neither}}rowspan="3" | 2.1rowspan="3" {{Yes|AGP 2×}}
440ZX

|SL33W

rowspan="3" | 66/100 MHz
440ZX-M82443ZX-M

|SL3VP

PIIX4MPentium III, Celeron256 MB
440MXBanister82443MX

|SL37L (B0)

SL3N4 (B0)

| Same chip

Pentium II/III, Celeron512 MB2.2{{No}}

=Southbridge 4xx chipsets=

{{Main article|PCI IDE ISA Xcelerator}}

class="wikitable" style="font-size: 90%; text-align:center;"
Chipset || Part Number

!sSpec Number|| ATA support || USB support || CMOS/clock || ISA support || LPC support || Power management

ESC82374EB/SB

|SZ867

rowspan="4" | Nonerowspan="6" | Nonerowspan="10" {{Yes}}
PCEB82375EB/SB

|

SIO82378IB/ZB

|SZ905

rowspan="5" {{No}}rowspan="8" {{No}}rowspan="8" | SMM
SIO.A82379AB

|

MPIIX82371MX

|SU034 (A1)

SU035 (A1)

SU067 (A2)

| PIO

PIIX82371FB

|SZ964 (A1)

SZ967 (A1)

SZ997 (A1)

| rowspan="2" | PIO/WDMA

PIIX382371SB

|SU052 (A1)

SU093 (B0)

| rowspan="4" | 1 Controller

2 Ports

PIIX482371AB

|SL23P

SL2 km (B0)

| rowspan="3" | PIO/UDMA 33

rowspan="3" {{Yes}}
PIIX4E82371EB

82371EBE

|SL2MY (A0)

SL2T3 (A0)

SL37M (A0)

SL37U (A0)

SL87F

PIIX4M82371MB

|SL3CG (A0)

SL3DD (A0)

8xx chipsets

=Pentium II/III chipsets=

class="wikitable" style="font-size: 90%; text-align:center;"
ChipsetCode namePart numbers

!sSpec Number

South bridgeRelease dateProcessorsFSBSMPMemory typesMax. memoryMemory banksParity or ECCPCIExt. AGP/speedIGP
810rowspan="3" | Whitney82810

|SL3P6

SL3P7 (A3)

SL35K

| ICH/ICH0

April 1999rowspan="5" | Celeron, Pentium II/III66/100 MHzrowspan="4" {{No}}EDO/PC100 SDRAMrowspan="9" | 512 MBrowspan="3" | 4rowspan="9" {{No|Neither}}rowspan="11" | v2.2/33 MHzrowspan="3" {{No}}rowspan="7" {{Yes}}
810Erowspan="2" | 82810E

|SL3MD (A3)

ICHSeptember 1999rowspan="11" | 66/100/133 MHzrowspan="8" | PC100/133 SDRAM
810E2

|

ICH2
815rowspan="6" | Solanorowspan="2" | 82815

| rowspan="2" |SL4DF (A2)

SL5YN

SL5NQ

| ICH

rowspan="2" | June 2000rowspan="6" | 6rowspan="2" {{Yes|Yes/AGP 4×}}
815EICH2{{Yes}} (2)
815Growspan="2" | 82815G

|

ICH/ICH0rowspan="2" | September 2001rowspan="3" | Celeron, Pentium IIIrowspan="4" {{No}}rowspan="2" {{No}}
815EG

|

ICH2
815Prowspan="2" | 82815EP

|

ICH/ICH0March 2001rowspan="5" {{Yes|Yes/AGP 4×}}rowspan="5" {{No}}
815EP

|SL5NR (B0)

ICH2November 2000rowspan="3" | Celeron, Pentium II/III
820rowspan="2" | Caminorowspan="2" | 82820

82820DP

| rowspan="2" |SL353 (B1)

SL3FT (B1)

SL3NF (B1)

SL47D (B2)

SL47F (B2)

| ICH

November 1999rowspan="3" {{Yes}}rowspan="2" | PC800 RDRAM/PC100 SDRAM (with MTH adapter)rowspan="2" | 1 GBrowspan="2" | 2rowspan="3" {{Yes|Both}}
820EICH2June 2000
840Carmel82840

|SL3QR

ICHOctober 1999Pentium III, XeonDual-Channel PC800 RDRAM/PC100 SDRAM (with MTH adapter)4 GB2×4v2.2/33 MHz + PCI-X/66 MHz

=Pentium III mobile chipsets=

class="wikitable" style="font-size: 90%; text-align:center;"
ChipsetCode namePart numbers

!sSpec Number

South bridgeRelease dateProcessorsFSBSMPMemory typesMax. memoryMemory banksParity or ECCPCIExt. AGP/speedIGP
815EM

|

|82815EM

|SL4MP

|ICH2-M

|October 2000

|Mobile Celeron, Mobile Pentium III

|100 MHz

|{{No}}

|PC100 SDRAM

|512 MB

|2

|{{No|Neither}}

|v2.2/33 MHz

|{{Yes|Yes/AGP 4×}}

|{{Yes}}

830Mrowspan="3" | Almador82830M

|SL62D

rowspan="3" | ICH3-MJuly 2001rowspan="3" | Celeron, Pentium III-Mrowspan="3" | 100/133 MHzrowspan="3" {{No}}rowspan="3" | PC133 SDRAMrowspan="3" | 1 GBrowspan="3" | 2rowspan="3" {{No|Neither}}rowspan="3" | v2.2/33 MHzrowspan="2" {{Yes|Yes/AGP 4×}}{{Yes}}
830MP82830MP

|SL5P7

SL62F

SL7A6

|

{{No}}
830MG82830MG

|SL5P9

SL62E

|

{{No}}{{Yes}}

=Pentium 4 chipsets=

class="wikitable" style="font-size: 100%; text-align:center;"
ChipsetCode namePart numbers

!sSpec Number

South bridgeRelease dateSocketProcessor brandsFSBSMPMemory types

!Memory Channels

Max. memory
[ GiB ]
Parity/ECCGraphicsTDP
860{{Cite web|date=May 2001|title=Intel 860 Chipset: 82860 Memory Controller Hub (MCH) Datasheet|url=http://download.intel.com/design/chipsets/datashts/29071301.pdf|url-status=dead|archive-url=https://web.archive.org/web/20060218024857/http://download.intel.com/design/chipsets/datashts/29071301.pdf|archive-date=2006-02-18|website=Intel}}Colusa82860 (MCH)

|SL5HB

rowspan="3" | ICH2May 2001Socket 603 Socket 604Xeonrowspan="3" | 400 MT/s
(100 MHz QDR)
{{Yes}}PC800/600 RDRAM

|2

4 (w. 2 repeaters)rowspan="5" {{Yes|Yes/Yes}}rowspan="5" | AGP
845Brookdale82845 (MCH)

|SL5V7 (A3)

SL5YQ

SL63W (B0)

| September 2001{{Cite web|last=Shimpi|first=Anand Lal|title=Intel 845 Chipset Review & Motherboard Roundup: September 2001|url=https://www.anandtech.com/show/826|access-date=2021-12-05|website=www.anandtech.com}}

rowspan="2" |Socket 423

Socket 478

| rowspan="3" | Celeron, Pentium 4

rowspan="16" {{No}}DDR 200/266
SDR 133

| rowspan="10" |1

2 (DDR)
3 (SDR)
850Tehama82850 (MCH)

|SL4NG (A2)

SL5HA (A3)

| November 2000

PC800/600 RDRAMrowspan="9" | 2
850ETehama-E82850E (MCH)

|SL64X (A3)

ICH2/ICH4rowspan="3" | May 2002

| rowspan="3" |Socket 478

| rowspan="4" | 400/533 MT/s

PC1066/800/600 RDRAM
845EBrookdale-E82845E (MCH)

|SL66N

SL69S

| rowspan="6" | ICH4

rowspan="3" | Celeron, Celeron D, Pentium 4DDR 200/2665.8 W
845GBrookdale-G82845G (GMCH)

|SL66F (A1)

SL6PR (B1)

|DDR 200/266
SDR 133

rowspan="10" {{No|No/No}}Intel Extreme Graphics
AGP 4×
rowspan="2" | 5.1 W (SDRAM),
5.7 W (DDR)
845GVBrookdale-GV82845GV (GMCH)

|SL6NR (A1)

SL6PU (B1)

SL8DA

| October 2002

|Socket 478
LGA 775

DDR 200/266
SDR 133

| rowspan="2" |Intel Extreme Graphics
no AGP slot

845GLBrookdale-GL82845GL (GMCH)

|SL66G (A1)

SL6PT (B1)

| May 2002

Socket 478

| Celeron, Pentium 4

400 MT/sDDR 200/266
SDR 133
5.1 W (SDRAM),
5.8 W (DDR){{cite web |url=https://download.intel.com/design/chipsets/designex/29865502.pdf |title=Intel 82845G/82845GL/82845GV GMCH Thermal and Mechanical Design Guidelines |access-date=2016-04-22 |archive-url=https://web.archive.org/web/20160304062219/http://download.intel.com/design/chipsets/designex/29865502.pdf |archive-date=2016-03-04 |url-status=dead }}
845GEBrookdale-GE82845GE (GMCH)

|SL6PS

rowspan="2" | October 2002

|Socket 478
LGA 775

| rowspan="2" |Celeron, Celeron D, Pentium 4

| rowspan="2" | 400/533 MT/s

rowspan="2" |DDR 200/266/333

|Intel Extreme Graphics
AGP 4×

6.3 W
845PEBrookdale-PE82845PE (MCH)

|SL6H5

SL6Q3

|Socket 478

| AGP 4×

5.6 W
style="border-top:2px solid gray;"

|848P

Breeds Hill82848P (MCH)

|SL77Y (A2)

SL7YG (A2)

| rowspan="5" | ICH5/ICH5R

August 2003rowspan="5" | Socket 478
LGA 775
Pentium 4, Pentium 4 EE, Pentium D,
Celeron, Celeron D
400/533/800 MT/sDDR-400rowspan="2" | AGP 8×8.1 W
865PSpringdale-P82865P

|SL6UY

rowspan="3" | May 2003Pentium 4, Celeron D400/533 MT/sDDR-333

| rowspan="11" |2

rowspan="6" | 410.3 W
865PESpringdale-PE82865PE

|SL722 (A2)

SL7YE (A2)

| rowspan="3" | Pentium 4, Pentium 4 EE, Pentium D,
Pentium Extreme Edition, Celeron,
Celeron D

rowspan="4" | 400/533/800 MT/srowspan="4" | DDR-400AGP 8×11.3 W
865GSpringdale82865G (GMCH)

|SL99Y

SL743 (A2)

| Intel Extreme Graphics 2
AGP 8×

12.9 W
865GVSpringdale-GV82865GV (GMCH)

|SL77X (A2)

SL7YF (A2)

| September 2003

Intel Extreme Graphics 2
no AGP slot
style="border-top:2px solid gray;"

|875P{{Cite web|date=February 2004|title=Intel 875P Chipset Datasheet|url=https://www.intel.com/content/dam/doc/datasheet/875p-chipset-datasheet.pdf|access-date=2021-06-02|website=Intel}}

Canterwood82875P (MCH)

|SL744 (A2)

SL8DB

|ICH5/ICH5R/6300ESB

April 2003Socket 478
Socket 604
LGA 775
Pentium 4, Pentium 4 EE, Pentium D,
Pentium Extreme Edition, Celeron,
Celeron D, Xeon
rowspan="5" {{Yes|Yes/Yes}}rowspan="2" | AGP 8×12.1 W
E7205{{Cite web|date=December 2002|title=Intel E7205 Chipset Memory Controller Hub (MCH) Datasheet|url=https://www.intel.com/content/dam/doc/datasheet/e7205-chipset-memory-controller-hub-datasheet.pdf|access-date=2021-06-02|website=Intel}}Granite BayE7205 (MCH)

|SL65P (B0)

SL6TU

| ICH4

November 2002Socket 478Pentium 4400/533 MT/sDDR-200/266
E7500{{Cite web|date=February 2002|title=Intel E7500 Chipset Datasheet|url=https://www.intel.com/content/dam/doc/datasheet/e7500-chipset-datasheet.pdf|access-date=2021-06-02|website=Intel}}Plumasrowspan="2" | E7500 (MCH)

|SL64H

SL69U

| rowspan="2" | ICH3-S

February 2002Socket 604Xeon400 MT/srowspan="3" {{Yes}}

|DDR-200

rowspan="3" | 16rowspan="2" | PCI-X
E7501{{Cite web|date=July 2003|title=Intel E7501 Chipset Memory Controller Hub (MCH) Datasheet|url=https://www.intel.com/content/dam/doc/datasheet/e7501-chipset-memory-controller-hub-datasheet.pdf|access-date=2021-06-02|website=Intel}}Plumas 533

|

December 2002Socket 604
Socket 479
Xeon, Pentium M{{cite web |url=https://download.intel.com/design/intarch/manuals/27387901.pdf |title=Intel Pentium M Processor with Intel E7501 Development Kit User's Manual |access-date=2016-04-22 |archive-url=https://web.archive.org/web/20160909102750/http://download.intel.com/design/intarch/manuals/27387901.pdf |archive-date=2016-09-09 |url-status=dead }}rowspan="2" | 400/533 MT/s

| rowspan="2" |DDR-200/266

E7505{{Cite web|date=December 2002|title=Intel E7505 Chipset Memory Controller Hub (MCH) Datasheet|url=https://www.intel.com/content/dam/doc/datasheet/e7505-chipset-memory-controller-hub-datasheet.pdf|access-date=2021-06-02|website=Intel}}PlacerE7505 (MCH)

|SL65N

SL6TU

| ICH4

November 2002Socket 604XeonAGP 8×
E7221 {{cite web |url=http://www.informit.com/articles/article.aspx?p=481869&seqNum=4 |title=Intel Pentium 4 Chipsets for Single-Processor Servers |date=2006-06-12 |access-date=2019-07-13 |archive-url=https://web.archive.org/web/20131004113804/http://www.informit.com/articles/article.aspx?p=481869&seqNum=4 |archive-date=2013-10-04 |url-status=live }}{{cite web |url=https://www.intel.de/content/dam/doc/datasheet/e7221-chipset-datasheet.pdf |title=Intel E7221 Chipset Datasheet |publisher=Intel.com |date=September 2004 |access-date=2019-07-13 |archive-url=https://web.archive.org/web/20190713082638/https://www.intel.de/content/dam/doc/datasheet/e7221-chipset-datasheet.pdf |archive-date=2019-07-13 |url-status=live }}Copper RiverE7221 (MCH)

|SL7YQ

ICH6/ICH6RSeptember 2004LGA 775Pentium 4, Pentium 4 HT533/800 MT/srowspan="2" {{No}}DDR 333/400
DDR2 400/533
4{{Yes|Yes/Yes}}
unbuffered only
• Integrated graphics engine (SVGA)
PCI Express ×8 (1.0a), or
• PCI-X (with PCIe bridge)
not specifically dedicated to graphics
E7230 {{cite web |url=https://www.intel.com.au/content/dam/doc/datasheet/e7230-chipset-memory-controller-hub-datasheet.pdf |title=Intel E7230 Chipset Memory Controller Hub (MCH) Datasheet |publisher=Intel.com |date=July 2005 |access-date=2019-07-13 |archive-url=https://web.archive.org/web/20190713062434/https://www.intel.com.au/content/dam/doc/datasheet/e7230-chipset-memory-controller-hub-datasheet.pdf |archive-date=2019-07-13 |url-status=live }}MukilteoE7230 (MCH)

|SL8kJ

SL8KK

| ICH7/ICH7R

July 2005LGA 775Pentium D,
Pentium 4, Pentium 4 HT, Pentium 4 EE,
Celeron D
533/800/1066 MT/sDDR2 400/533/6678{{Yes|Yes/Yes}}
unbuffered only
PCI Express ×8 (1.0a), or
• PCI-X (with PCIe bridge)
not specifically dedicated to graphics

Summary:

  • 845 (Brookdale)
  • two distinct versions 845 MCH for SDR and 845 MCH for DDR{{cite web |url=https://www.intel.com/content/www/de/de/chipsets/845-chipset-82845-memory-controller-hub-sdr-datasheet.html |title=Intel 845 Chipset: 82845 MCH for SDR: Datasheet |publisher=Intel.com |date=2013-12-15 |access-date=2014-01-19 |archive-url=https://web.archive.org/web/20130603103400/http://www.intel.com/content/www/de/de/chipsets/845-chipset-82845-memory-controller-hub-sdr-datasheet.html |archive-date=2013-06-03 |url-status=live }}{{cite web |url=https://www.intel.com/content/www/de/de/chipsets/845-chipset-82845-memory-controller-hub-ddr-datasheet.html |title=Intel 845 Chipset: Memory Controller Hub (MCH) For DDR |publisher=Intel.com |date=2013-12-13 |access-date=2014-01-19 |archive-url=https://web.archive.org/web/20130603105050/http://www.intel.com/content/www/de/de/chipsets/845-chipset-82845-memory-controller-hub-ddr-datasheet.html |archive-date=2013-06-03 |url-status=live }}
  • 875P (Canterwood)
  • Similar to E7205, but adds support for 800 MHz bus, DDR at 400 MHz, Communication Streaming Architecture (CSA), Serial ATA (with RAID in certain configurations) and Performance Acceleration Technology (PAT), a mode purported to cut down memory latency.
  • SMP capability exists only on Xeon-based (socket 604) motherboards using the 875P chipset. FSB is rated at {{nowrap|533 MHz}} on these motherboards.
  • 865PE (Springdale)
  • 875P without PAT, though it was possible to enable PAT in some early revisions. Also lacks ECC Memory support.
  • Sub-versions:
  • 865P - Similar to 865PE, but supports only 400/533 MHz bus and 333 MHz memory.
  • 848P - Single memory channel version of 865PE.
  • 865G (Springdale-G)
  • 865PE with integrated graphics (Intel Extreme Graphics 2). PAT never supported in any revisions.
  • Sub-versions:
  • 865GV - 865G without external AGP slot.
  • E7221 (Copper River)
  • Designed for Pentium 4-based server.
  • Supports only one physical processor.
  • A basic SVGA controller is integrated for analog video.
  • One PCI-X slot can be bridged to the PCI-e ×8 using the Intel 6702PXH 64-bit PCI Hub.
  • E7230 (Mukilteo)
  • Similar to the Intel 3000 MCH, but mainly designed for Pentium D-based server.
  • Supports only one physical processor.
  • DDR2-667 4-4-4 is not supported.
  • No integrated graphics.
  • One PCI-X slot can be bridged to the PCI-e ×8 using Intel 6700PXH 64-bit PCI Hub/Intel 6702PXH 64-bit PCI Hub.

=Pentium 4-M/Pentium M/Celeron M mobile chipsets=

class="wikitable" style="font-size: 90%; text-align:center;"
ChipsetCode namePart numbers

!sSpec Number

South bridgeRelease dateProcessorsFSBSMPMemory typesMax. memoryParity/ECCPCI TypeGraphicsTDP
845MZBrookdale-MZrowspan="2" | 82845 (MCH)

|SL64T

rowspan="2" | ICH3-Mrowspan="2" | March 2002rowspan="2" | Mobile Celeron, Pentium 4-Mrowspan="4" | 400 MT/srowspan="10" {{No}}DDR 200rowspan="4" | 1 GBrowspan="10" {{No|No/No}}rowspan="10" | v2.2/33 MHzrowspan="2" | AGP 4×
845MPBrookdale-M

|SL66J

rowspan="3" | DDR 200/266
852GMrowspan="4" | Montara-GM82852GM (GMCH)

|SL6ZK

SL7VP

| rowspan="8" | ICH4-M

Q2, '04rowspan="2" | Pentium 4-M, Celeron, Celeron Mrowspan="2" | Integrated 32-bit 3D Core @ 133 MHzrowspan="2" | 3.2 W
852GMV82852GMV (GMCH)|
852PM82852PM (MCH)

|SL72J

SL7VP

|

rowspan="2" | Pentium 4-M, Celeron, Celeron Drowspan="2" | 400 MT/s

533 MT/s

| rowspan="2" | DDR 200/266/333

rowspan="6" | 2 GBAGP 1x/2×/4×rowspan="3" | 5.7 W
852GME82852GME (GMCH)

|SL72K

SL8D7

| Q4, '03

rowspan="4" | Integrated Extreme Graphics 2 graphics core
854 [https://www.intel.com/design/celect/854/] {{Webarchive|url=https://web.archive.org/web/20170413024020/http://www.intel.com/design/celect/854/|date=2017-04-13}} Intel 854 Product Information82854 (GMCH)

|SL794

March 2005Celeron M ULVrowspan="4" | 400 MT/sDDR 266/333
855GMrowspan="2" | Montara-GM82855GM (GMCH)

|SL6WW

SL7VL

| rowspan="3" | March 2003

rowspan="3" | Pentium M, Celeron MDDR 200/2663.2 W
855GME82855GME (MCH)

|SL72L

SL7VN

| rowspan="2" | DDR 200/266/333

4.3 W
855PMOdem82855PM (MCH)

|SL6TJ (A3)

SL752 (B1)

| AGP 2×/4×

5.7 W

=Southbridge 8xx chipsets=

{{Main article|I/O Controller Hub}}

class="wikitable" style="font-size: 90%; text-align:center;"
Chipset

! Part Number

! sSpec Number

! ATA

! SATA

! RAID Level

! USB

! PCI

ICH82801AA

|SL38R

SL3MZ

SL47Z

| UDMA 66/33

rowspan="9" {{No}}rowspan="10" {{No}}rowspan="3" | 1.1, 2 portsRev 2.2, 6 slots
ICH082801AB

|SL38P

SL3N2 (B1)

| UDMA 33

Rev 2.2, 4 slots
ICH2-M82801BAM

|SL45H (B0){{cite web |url=https://www.intel.com/Assets/PDF/specupdate/298242.pdf |title=I/O Controller Hub 2 Specification Update 298242-027| date=May 2004 | page=15}}

SL4HN (B1)

SL4R6 (B2)

| rowspan="10" | UDMA 100/66/33

Rev 2.2, 2 slots
ICH282801BA

|SL45H (B0)

SL5FC (B0)

SL4HM (B1)

SL4YG (B1’)

SL59Z (B4)

SL5WK (B5)

SL7UU (B5){{cite web |url=https://cdrdv2-public.intel.com/812044/PCN105975-01.pdf |title=Product Change Notification 105975–01| date=March 27, 2006| page=6}}

SL5PN (C0)

| 1.1, 4 ports

Rev 2.2, 6 slots
ICH3-M82801CAM

|SL5LF (B0)

SL5YP

| 1.1, 2 ports

Rev 2.2, 2 slots
ICH3-S82801CA

|SL632

SL8AN (B2)

| 1.1, 6 ports

Rev 2.2, 6 slots
ICH4-M82801DBM

|SL6DN

SL7VK (B2)

2.0, 4 portsRev 2.2, 3 slots
ICH482801DB

|SL66K (A1)

SL6DM (B0)

SL8DE

| 2.0, 6 ports

Rev 2.2, 6 slots
ICH5-M82801EBM

|

2.0, 4 portsRev 2.3, 4 slots
ICH582801EB

|SL6TN (A2)

SL73Z (A3)

SL7YC

| rowspan="3" {{Yes|SATA 1.5 Gbit/s, 2 ports}}

rowspan="2" | 2.0, 8 portsrowspan="2" | Rev 2.3, 6 slots
ICH5R82801ER

|SL6ZD

SL73D (A3)

SL742 (A3)

| rowspan="2" {{Yes|RAID 0, RAID 1}}

6300ESB6300ESB

|SL7XJ

2.0, 4 portsRev 2.2 4 PCI slots,
Rev 1.0 2 PCI-X slots + 2 PCI-X devices

9xx chipsets and 3/4 Series chipsets

=Pentium 4/Pentium D/Pentium XE chipsets=

All chipsets listed in the table below:

  • Do not support SMP
  • Support (-R and -DH) variants for South Bridges

class="wikitable" style="font-size: 95%;"
rowspan="2" | Chipset

! rowspan="2" | Code Name

! rowspan="2" | Part numbers

! rowspan="2" |sSpec Number

! rowspan="2" | South Bridge

! rowspan="2" | Release Date

! rowspan="2" | Supported Processors

! rowspan="2" | FSB [MT/s]

! colspan="2" | Memory

! rowspan="2" | Parity / ECC

! colspan="2" | Graphics

! rowspan="2" | TDP [W]

typesmax. [GB]PCIeintegrated core
910GLrowspan="2" | Grantsdale-GL82910GL (GMCH)

|SL7W4 (B1)

SL8AR (C2)

SL8BV (C2)

| rowspan="8" | ICH6/ICH6R

September 2004Pentium 4, Celeron, Celeron D533rowspan="3" | DDR 333/4002rowspan="6" {{No|No/No}}rowspan="2" {{n/a}}rowspan="2" | GMA 900rowspan="6" | 16.3
915GL82915GL (GMCH)

|SL8CK (C2)

SL8CL

SL8DC (C2)

| rowspan="2" | March 2005

rowspan="5" | Pentium 4, Celeron Drowspan="5" | 533/8004
915PLGrantsdale-PL82915PL (MCH)

|SL8D6 (C2)

SL8DD (C2)

| 2

rowspan="3" | ×16rowspan="2" {{n/a}}
915PGrantsdale82915P (MCH)

|SL7LY (B1)

SL8AS (C2)

SL8BW (C2)

| rowspan="4" | June 2004

rowspan="3" | DDR 333/400,
DDR2 400/533
rowspan="3" | 4
915GGrantsdale-G82915G (GMCH)

|SL7LX (B1)

SL8AT (C2)

SL8BU (C2)

| rowspan="2" | GMA 900

915GVGrantsdale-GV82915GV (GMCH)

|SL7W5 (B1)

SL8AU (C2)

SL8BT (C2)

| {{n/a}}

925XAlderwood82925X (MCH)

|SL7LZ

SL7RC

| rowspan="2" | Pentium 4, Pentium 4 XE

800rowspan="3" | DDR2 400/533rowspan="2" | 4[*]rowspan="2" {{Yes|Yes/Yes}}rowspan="6" | ×16rowspan="4" {{n/a}}12.3
925XEAlderwood-XE82925XE (MCH)

|SL84Z

November 2004800/106613.3
style="border-top:2px solid gray;"

| 945PL

Lakeport-PL82945PL (MCH)

|SL8V4 (A2)

SL93C (A1)

| ICH7

March 2006Pentium 4, Pentium D, Celeron D,
(Core 2)[1]
533/8002[*]rowspan="3" {{No|No/No}}rowspan="2" | 15.2
945PLakeport82945P (MCH)

|SL8FV (A1)

SL8HT (A2)

| rowspan="3" | ICH7/ICH7R

rowspan="2" | May 2005rowspan="2" | Pentium 4, Pentium D, Celeron D,
(Core 2)[1]
rowspan="2" | 533/800/1066rowspan="2" | DDR2 400/533/667rowspan="2" | 4[*]
945GLakeport-G82945G (GMCH)

|SL8FU

GMA 95022.2
955XLakeport-X82955X (MCH)

|SL8FW

April 2005Pentium 4, Pentium 4 XE, Pentium D, Pentium XE800/1066DDR2 533/6678{{Yes|Yes/Yes}}{{n/a}}13.5

[*] Remapping of PCIE/APIC memory ranges not supported,[https://www.intel.com/Assets/PDF/datasheet/309219.pdf Mobile Intel 945 Express Chipset Family Datasheet] {{Webarchive|url=https://web.archive.org/web/20171130113624/https://www.intel.com/Assets/PDF/datasheet/309219.pdf |date=2017-11-30 }}, section 9.2[https://download.intel.com/design/chipsets/datashts/30146403.pdf Intel 925X/925XE Datasheet] {{Webarchive|url=https://web.archive.org/web/20131126071912/http://download.intel.com/design/chipsets/datashts/30146403.pdf |date=2013-11-26 }}, section 9.2 some physical memory might not be accessible (e.g. limited to 3.5 GB or similar).

[1] Some later revisions of motherboards based on 945P,945G and 945PL chipset usually supports some Core 2 processors (with later BIOSes). Core 2 Quad is not supported. Only Core 2 Duo, Pentium Dual-Core, and Core2 based Celerons.

Summary:

  • 915P (Grantsdale)
  • Supports Pentium 4 on an 800 MT/s bus. Uses DDR memory up to 400 MHz, or DDR2 at 533 MHz. Replaces AGP and CSA with PCI Express, and also supports "Matrix RAID", a RAID mode designed to allow the usage of RAID levels 0 and 1 simultaneously with two hard drives. (Normally RAID1+0 would have required four hard drives)
  • Sub-versions:
  • 915PL - Cut-down version of 915P with no support for DDR2 and only supporting 2 GB of memory.
  • 915G (Grantsdale-G)
  • 915P with an integrated GMA 900. This core contains Pixel Shader version 2.0 only, it does not contain Vertex Shaders nor does it feature Transform & Lighting (T&L) capabilities and therefore is not Direct X 8.1 or 9.0 compliant.
  • Sub-versions:
  • 915GL - Same feature reductions as 915PL, but supports 4 GB of memory. No support for external graphics cards.
  • 915GV - Same as 915G, but has no way of adding an external graphics card.
  • 910GL - No support for external graphics cards or 800 MT/s bus.
  • 925X (Alderwood)
  • Higher end version of 915. Supports another PAT-like mode and ECC memory, and exclusively uses DDR-II RAM.
  • Sub-versions:
  • 925XE - Supports a 1066 MT/s bus.
  • 945P (Lakeport)
  • Update on 915P, with support for Serial ATA II, RAID mode 5, an improved memory controller with support for DDR-II at 667 MHz and additional PCI Express lanes. Support for DDR-I is dropped. Formal dual-core support was added to this chipset.
  • Sub-versions:
  • 945PL - No support for 1066 MT/s bus, only supports 2 GB of memory.
  • 945G (Lakeport-G)
  • A version of the 945P that has a GMA 950 integrated, supports a 1066 MT/s bus.
  • Sub-versions:
  • 945GC - Same feature reductions as 945PL but with an integrated GMA 950.
  • 945GZ - Same as 945GC but only supports DDR2 memory at 400/533 MT/s. No support for external graphics cards (some boards, like Asus P5GZ-MX, support through ICH7 on PCIe ×16 @4 lanes mode).
  • 955X (Lakeport)
  • Update for 925X, with additional features of "Lakeport" (e.g., PAT features and ECC memory), and uses DDR2.

=Pentium M/Celeron M mobile chipsets=

class="wikitable" style="font-size: 95%;"
Chipset || Code Name || Part numbers

!sSpec Number|| South Bridge || Release Date || Supported Processors || FSB || Memory Types || Max. Memory || Parity/ECC || Graphics || TDP

910GMLrowspan="3" | Alviso-GM82910GML (GMCH)

|SL89H

SL8AE

SL8DX

SL8G5 (C2)

SL8G8 (C2)

| rowspan="4" | ICH6-M

rowspan="4" | January 2005Celeron Mrowspan="2" | 400 MT/sDDR 333/400, DDR2 400rowspan="4" | 2 GBrowspan="4" {{No|No/No}}rowspan="3" | Integrated GMA 9006 W
915GMS82915GMS (GMCH)

|SL8B6

SL8B7

SL8G4 (C2)

SL8G9 (C2)

| rowspan="3" | Pentium M, Celeron M

DDR2 4004.8 W
915GM82915GM (GMCH)

|SL87G

SL89G

SL8DY

SL8G2 (C2)

SL8G6 (C2)

| rowspan="2" | 400/533 MT/s

rowspan="2" | DDR 333, DDR2 400/5336 W
915PMAlviso82915PM (MCH)

|SL8B4

SL8B5

SL8BR

SL8CS

SL8G3 (C2)

SL8G7 (C2)

| PCI Express ×16

5.5 W

=Core/Core 2 mobile chipsets=

class="wikitable" style="font-size: 90%;"
rowspan="2" | Chipsetrowspan="2" | Code namerowspan="2" | Part numbers

! rowspan="2" |sSpec Number

rowspan="2" | South bridgerowspan="2" | Release daterowspan="2" | Processors supported (official)rowspan="2" | FSB (MT/s)colspan="2" | Memorycolspan="2" | Graphicsrowspan="2" | TDP [W]
typesmax. [GB]graphics core3D Render
940GMLrowspan="7" | Calistoga82940GML (GMCH)

|SL8Z5

rowspan="4" | ICH7-Mrowspan="2" | January 2006Celeron Mrowspan="2" | 533rowspan="4" | DDR2 400/533rowspan="4" | 2rowspan="6" | Integrated GMA 950Max. 166 MHz7
943GML82943GML (GMCH)

|

Celeron M, Core Solo, Pentium Dual-Core{{Efn|The Intel 82943GML mobile chipset unofficially supports Core Duo, Core 2 Duo, and Pentium Dual Core processors as well as 667 MHz FSB, which is a popular upgrade for many older notebook computers such as certain models of Acer Aspire 3680.}}Max. 200 MHz
945GSE82945GSE (GMCH)

|SLB2R

Q1'06Intel Atomrowspan="5" | 533/667rowspan="2" | Max. 166 MHz6
945GMS82945GMS (GMCH)

|SL8TC

rowspan="4" | January 2006rowspan="4" | Core 2 Duo, Core Duo, Pentium Dual-Core, Core Solo, Celeron M7
945GM/E82945GM/E (GMCH)

|SL8Z2

| rowspan="3" |ICH7-M/ICH7-M DH

rowspan="3" | DDR2 400/533/667rowspan="3" | 4{{Efn|Remapping of PCIE/APIC memory ranges not supported, some physical memory might not be accessible (e.g. limited to 3.5 GB or similar).}}Max. 250 MHzrowspan="3" | 7
945GT{{Cite web|title=Intel 945GT Express Chipset|url=https://www.intel.com/Assets/PDF/prodbrief/945gt-prodbrief.pdf}}

|82945GT (GMCH)

|SL8Z6

|Max. 400 MHz

945PM82945PM (MCH)

|SL8Z4

colspan="2" | PCI Express ×16

=Core 2 chipsets=

All Core 2 chipsets support the Pentium Dual-Core and Celeron processors based on the Core architecture. Support for all NetBurst based processors was officially dropped starting with the Bearlake chipset family.{{cite web|author=Patrick Schmid |url=http://www.tomshardware.com/reviews/intel-intros-3-series-chipsets-fsb1333-ddr3,1607-3.html |title=The 3-Series Chipset Family A.k.a. Bearlake - Intel Intros 3-Series Chipsets with FSB1333 and DDR3 |publisher=Tomshardware.com |date=2007-05-21 |access-date=2014-01-19}} However, some motherboards still support the older processors.{{cite web |url=https://www.asrock.com/mb/cpu.asp?Model=4Core1600Twins-P35 |title=> Products > 4Core1600Twins-P35 > CPU Support List |publisher=ASRock |access-date=2014-01-19 |archive-url=https://web.archive.org/web/20140102191712/http://www.asrock.com/mb/cpu.asp?Model=4Core1600Twins-P35 |archive-date=2014-01-02 |url-status=live }}

class="wikitable" style="font-size: 90%;"
rowspan="2" | Chipset

! rowspan="2" | Code Name

! rowspan="2" | Part numbers

! rowspan="2" |sSpec Number

! rowspan="2" | South Bridge

! rowspan="2" | Release Date

! rowspan="2" | Processors

! rowspan="2" | Lithography

! rowspan="2" | VT-d support{{cite web |url=https://www.intel.com/technology/itj/2006/v10i3/2-io/5-platform-hardware-support.htm |title=Ultrabook, SmartPhone, Laptop, Desktop, Server, & Embedded– Intel |publisher=Intel.com |access-date=2014-01-19 |archive-url=https://web.archive.org/web/20121013233409/http://www.intel.com/technology/itj/2006/v10i3/2-io/5-platform-hardware-support.htm |archive-date=2012-10-13 |url-status=live }}

! rowspan="2" | FSB

(MT/)

! colspan="2" | Memory

! rowspan="2" | Parity/ECC

! rowspan="2" | PCIe

! rowspan="2" | iGraphics

typesmax.
945GC{{cite web |url=https://ark.intel.com/products/34505/Intel-82945GC-Graphics-and-Memory-Controller |title=Intel 945GC Express Chipset (Intel 82945GC Graphics and Memory Controller) |publisher=Ark.intel.com |access-date=2014-04-16 |archive-url=https://web.archive.org/web/20140705005618/http://ark.intel.com/products/34505/Intel-82945GC-Graphics-and-Memory-Controller |archive-date=2014-07-05 |url-status=live }}Lakeport-GC82945GC (MCH)

|SL9ZC (A2)

SLA9C (A2)

SLB86 (A2)

| ICH7/ICH7R/ICH7-DH {{cite web |url=https://ark.intel.com/products/chipsets/22687 |title=ARK | Intel 82801GB I/O Controller |publisher=Ark.intel.com |access-date=2014-01-19 |archive-url=https://web.archive.org/web/20120718094106/http://ark.intel.com/products/chipsets/22687 |archive-date=2012-07-18 |url-status=live }}

May 2005{{cite web|url = https://ark.intel.com/products/34505/Intel-82945GC-Graphics-and-Memory-Controller|title = ARK | Intel 82945GC|publisher = Ark.intel.com|access-date = 2015-05-04|archive-url = https://web.archive.org/web/20150430124524/http://ark.intel.com/products/34505/Intel-82945GC-Graphics-and-Memory-Controller|archive-date = 2015-04-30|url-status = live}}Pentium 4, Pentium D, Celeron D, Core 2 Duo, Pentium Dual-Core, Atomrowspan=9 | 130 nmrowspan="15" {{No}}rowspan="4" | 533/800 (last rev.1066)DDR2 400/533/6672 GB (some boards supports 4 GB shrunk to 3.27 GB) [*]rowspan="8" {{No|No/No}}1x16rowspan="2" | GMA 950
945GZLakeport-GZ82945GZ (GMCH)

|SL927 (A2)

ICH7June 2005rowspan="3" | Pentium 4, Pentium D, Celeron D, Core 2 Duo, Pentium Dual-CoreDDR2 400/5334 GB (shrunk to 3.27 GB due to chipset limitation {{cite web |url=https://ark.intel.com/products/27722/Intel-82945GZ-Memory-Controller |title=ARK | Intel 945GZ Express Chipset (Intel 82945GZ Memory Controller) |work=Intel® ARK (Product Specs) |publisher=Ark.intel.com |access-date=2014-01-19 |archive-url=https://web.archive.org/web/20140111075804/http://ark.intel.com/products/27722/Intel-82945GZ-Memory-Controller |archive-date=2014-01-11 |url-status=live }}some motherboards have ×16 @×4 from ICH7{{cite web|url=https://www.asus.com/Motherboards/P5GZMX/#specifications|title=Motherboards - P5GZ-MX|publisher=Asus.com|access-date=2014-01-19|archive-url=https://web.archive.org/web/20140120004237/http://www.asus.com/Motherboards/P5GZMX#specifications|archive-date=2014-01-20|url-status=live}}
946PLLakeport-PL82946PL (MCH)

|SL9NV

SL9QY

| rowspan="2" | ICH7/ICH7R

rowspan="2" | July 2006rowspan="2" | DDR2 533/667rowspan="2" | 4 GBrowspan="2" | ×16{{n/a}}
946GZLakeport-GZ82946GZ (GMCH)

|SL9NV

SL9R4

| GMA 3000

style="border-top:2px solid gray;"

| P965

Broadwater(P)82P965 (MCH)

|SL9NU

SL9QX

| rowspan="4" | ICH8/ICH8R/ICH8-DH

rowspan="4" | June 2006Pentium Dual-Core, Core 2 Quad, Core 2 Duorowspan="4" | 533/800/1066rowspan="4" | DDR2 533/667/800rowspan="5" | 8 GB×16, ×4{{n/a}}
G965Broadwater(GC)82G965 (GMCH)

|SL9P2

SL9R5

| rowspan="3" | Pentium Dual-Core, Core 2 Duo

rowspan="2" | ×16GMA X3000
Q965Broadwater(G)82Q965 (GMCH)

|SL9NW

SL9QZ

| rowspan="2" | GMA 3000

Q963|Broadwater(G)82Q963 (GMCH)

|SL9R2

{{No|No}}
975XGlenwood82975X (MCH){{cite web|url=https://www.intel.com/products/chipsets/975x/index.htm|title=Intel 975X Express Chipset Overview|work=Intel ARK (Product Specs)|access-date=2017-10-07|archive-url=https://web.archive.org/web/20080513134103/http://www.intel.com/products/chipsets/975x/index.htm|archive-date=2008-05-13|url-status=live}}

|SL8YS

ICH7/ICH7R/ICH7-DHNovember 2005Pentium 4, Pentium 4 EE, Pentium D, Pentium XE, (Celeron D, Core 2 Quad, Core 2 Duo, Pentium Dual-Core)2533/800/10662DDR2 533/667/8003{{Yes|Yes/Yes}}1x161, 2×8rowspan="2" {{n/a}}
style="border-top:2px solid gray;"

| P31

Bearlake (P)82P31 (MCH)

|SLAHX

SLASK (B0)

| rowspan="2" | ICH7

rowspan="2" | August 2007rowspan="7" | Pentium Dual-Core, Core 2 Duo, Core 2 Quadrowspan="7" | 90 nmrowspan="16" | 800/1066/1333
(P45 unofficial 1600)
rowspan="2" | DDR2 667/800rowspan="2" | 4 GBrowspan="15" {{No|No/No}}rowspan="3" | 1×16 rev. 1.1
G31Bearlake (G)82G31 (GMCH)

|SLASJ (B0)

SLAJ3 (A2)

| rowspan="2" | GMA 3100

G33Bearlake (G+)82G33 (GMCH)

|SLA9Q (A2)

rowspan="3" | ICH9/ICH9R/ICH9-DHrowspan="2" | June 2007rowspan="2" | DDR2 667/800
DDR3 800/1066
8 GB
4 GB
P35Bearlake (P+)82P35 (MCH)

|SLA9R (A2)

rowspan="4" | 8 GB1×16, 1x4 rev. 1.1{{n/a}}
G35Bearlake82G35 (GMCH)

|SLAJJ

August 2007rowspan="3" | DDR2 667/800rowspan="4" | 1×16 rev. 1.1GMA X3500
Q33Bearlake (QF)82Q33 (GMCH)

|SLAEW (A2)

ICH9/ICH9Rrowspan="2" | June 2007rowspan="2" | GMA 3100
Q35Bearlake (Q)82Q35 (GMCH)

|SLAEX

ICH9/ICH9R/ICH9-DO{{Yes}}4
style="border-top:2px solid gray;"

| G41

Eaglelake (G)82G41 (GMCH)

|SLB8D

SLGQ3

| ICH7

September 2008rowspan="8" | Core 2 Duo, Core 2 Quad

| rowspan="8" |65 nm

rowspan="7" {{No}}rowspan="8" | DDR2 667/800
DDR3 800/1066

| 4 GB
8 GB

GMA X4500
B43Eaglelake (B)82B43 (GMCH)

|SLGL7 (A3)

ICH10DDecember 200816 GBrowspan="2" | 1×16 rev. 2.0

|GMA 4500

P43Eaglelake (P)82P43 (MCH)

|SLB89

rowspan="4" | ICH10/ICH10Rrowspan="4" | June 2008rowspan="8" | 8 GB
16 GB
rowspan="2" {{n/a}}
P45Eaglelake (P+)82P45 (MCH)

|SLB7Z (A1)

SLB8C (A2)

| 1×16, 2×8 rev. 2.0

G43Eaglelake (G)82G43 (GMCH)

|SLB85 (A3)

SLGQ2 (A3)

| rowspan="4" | 1x16 rev. 1.1

GMA X4500
G45Eaglelake (G+)82G45 (GMCH)

|SLB84

|GMA X4500HD

Q43Eaglelake (Q)82Q43 (GMCH)

|SLB88 (A3)

ICH10/ICH10R/ICH10Drowspan="2" | August 2008

| rowspan="2" |GMA 4500

Q45Eaglelake (Q)82Q45 (GMCH)

|SLB8A

ICH10/ICH10R/ICH10-DOrowspan="3" {{Yes}}4
X38rowspan="2" | Bearlake (X)82X38 (MCH)

|SLALJ (A1)

rowspan="2" | ICH9/ICH9R/ICH9-DHSeptember 2007Pancescu, Alexandru. [http://news.softpedia.com/news/Intel-039-s-X38-Express-Chipset-Is-Ready-62908.shtml Intel's X38 Express Chipset Is Ready] {{Webarchive|url=https://web.archive.org/web/20070818022921/http://news.softpedia.com/news/Intel-039-s-X38-Express-Chipset-Is-Ready-62908.shtml |date=2007-08-18 }}, Softpedia News, August 16, 2007.rowspan="2" | Core 2 Duo, Core 2 Quad, Core 2 Extreme

| rowspan="2" |90 nm

rowspan="2" | DDR3 800/1066/1333
DDR2 667/800/1066
rowspan="2" {{Partial|No/DDR2 only}}rowspan="2" | 2×16 rev. 2.0rowspan="2" {{n/a}}
X4882X48 (MCH)

|SLASF (A1)

March 2008800/1066/1333/1600

[*] Remapping of PCIE/APIC memory ranges not supported, some physical memory might not be accessible (e.g. limited to 3.5 GB or similar). Operational configuration is 4 ranks - 2× 2 GB dual rank modules or 4× 1 GB single rank modules - depends on number of motherboard DDR2 slots.

Summary:

  • 946PL (Lakeport)
  • Update on 945PL, supports 4 GB of memory.
  • 946GZ (Lakeport-G)
  • A version of 946PL with GMA 3000 graphics core.
  • P965 (Broadwater)
  • Update on 945P, no native PATA support, improved memory controller with support for DDR2 memory up to 800 MHz and official Core 2 Duo support.
  • G965 (BroadwaterG)
  • A version of P965 that has a GMA X3000 integrated graphics core.
  • Q965 (Broadwater)
  • Expected G965 intended for Intel's vPro office computing brand, with GMA 3000 graphics instead of GMA X3000 graphics. Supports an ADD2 card to add a second display.
  • Sub-versions:
  • Q963 - Q965 without an external graphics interface or support for ADD2.
  • 975X (Glenwood)
  • Update of 955, with support for ATI Crossfire Dual Graphics systems and 65 nm processors, including Core 2 Duo.
  • P35 (Bearlake)
  • The P35 chipset provides updated support for the new Core 2 Duo E6550, E6750, E6800, and E6850. Processors with a number ending in "50" have a 1333 MT/s FSB. Support for all NetBurst based processors is dropped with this chipset.
  • G33 (BearlakeG)
  • A version of P35 with a GMA 3100 integrated graphics core and uses an ICH9 South Bridge.
  • Sub-versions:
  • G35 - G33 with a GMA x3500 integrated graphics core and uses an ICH8 South Bridge, no DDR3 support.
  • Q35 (BearlakeG)
  • Expected G33 intended for Intel's vPro office computing brand, no DDR3 Support.
  • Sub-versions:
  • Q33 - Q35 without vPro support.
  • P31 (BearlakeG)
  • A version of P35 with an ICH7 South Bridge, supports only 4 GB of DDR2 memory and does not support DDR3 memory.
  • Operational configuration is 4 ranks - 2× 2 GB dual rank modules or 4 × 1 GB single rank modules - depends on number of motherboard DDR2 slots. 4GBs modules are not supported.
  • G31 (BearlakeG)
  • A version of P31 with a GMA 3100 integrated graphics core. It supports a 1333 MT/s FSB with Core 2 Duo processors, but Core 2 Quad processors are only supported up to 1066 MT/s.{{cite web |url=https://www.intel.com/assets/pdf/prodbrief/317838.pdf |title=Intel G31 Express Chipset Product Brief |access-date=2018-07-07 |archive-url=https://web.archive.org/web/20180912131428/https://www.intel.com/Assets/PDF/prodbrief/317838.pdf |archive-date=2018-09-12 |url-status=live }}
  • G41 (EaglelakeG)
  • Update of G31 with a GMA X4500 integrated graphics core and DDR3 800/1066 support.
  • P45 (Eaglelake)
  • Update of P35, with PCIe 2.0 support, Hardware Virtualization, Extreme Memory Profile (XMP) and support for ATI Crossfire (x8+x8).
  • Sub-versions:
  • P43 - P45 without Crossfire support.
  • G45 (EaglelakeG)
  • A version of P45 that has a GMA X4500HD integrated graphics core and lacks Crossfire support.
  • Sub-versions:
  • G43 - Same feature reductions as P43, but with a GMA X4500 integrated graphics core.
  • Q45 (EaglelakeQ)
  • Expected G43 intended for Intel's vPro office computing brand. Also supports Hardware Virtualization Technology and Intel Trusted Platform Module 1.2 feature.
  • Sub-versions:
  • Q43 - Q45 without vPro support. Also lacks Intel Trusted Platform Module 1.2 support.
  • B43 - Q43 with an ICH10D South Bridge.

[1] The 975X chipset supports only ×16 PCI Express (electrically) in the top slot when the slot below it is unpopulated. Otherwise it and the lower slot (both attached to the Memory Controller Hub) operate at ×8 electrically.

[2] Only later revisions of the 975X chipset boards support Core 2 processors. See MSI 975X Platinum (MS-7246) rev 1.0 (first release), and MSI 975X Platinum Powerup revision (MS-7246) rev 2.1 (released autumn 2006) as example. source: https://web.archive.org/web/20210515170458/http://ixbtlabs.com/articles2/mainboard/msi-975x-platinum-powerup-edition-i975x.html

Officially 975X supports a maximum of 1066 MT/s FSB. Unofficially, third-party motherboards (Asus, Gigabyte) support certain 1333FSB 45 nm Core2 processors, usually with later BIOS updates.

As for Celeron and Celeron D support, some boards and revisions support it, some not. (see upper example, MSI Powerup Edition has reintroduced back Celeron support, probably due to later released Core2-based Celerons, which were often more powerful than higher clocked Netburst Pentiums 4.

[3] The 975X chipset technical specification shows only DDR2-533/667 memory support. Actual implementations of 975X do support DDR2 800.

[4] VT-d is inherently supported on these chipsets, but may not be enabled by individual OEMs. Always read the motherboard manual and check for BIOS updates. X38/X48 VT-d support is limited to certain Intel, Supermicro, DFI (LanParty) and Tyan boards. VT-d is broken or non existent on some boards until the BIOS is updated. Note that VT-d is a chipset Memory Controller Hub technology, not a processor feature, but this is complicated by later processor generations (Core i3/i5/i7) moving the MCH from the motherboard to the processor package, making only certain I series CPUs support VT-d.

=Core 2 mobile chipsets=

class="wikitable" style="font-size: 90%;"
rowspan="2" | Chipsetrowspan="2" | Code namerowspan="2" | Part numbers

! rowspan="2" |sSpec Number

rowspan="2" | South bridgerowspan="2" | Release daterowspan="2" | Lithographyrowspan="2" | Processors supported (official)rowspan="2" | FSB [MT/s]colspan="2" | Memorycolspan="2" | Graphicsrowspan="2" | TDP [W]
types.max. [GB]graphics core3D Render
GL960rowspan="3" | Crestline82960GL (GMCH)

|SLA5V (C0)

rowspan="3" | ICH8-Mrowspan="3" | May 2007rowspan="3" | ?? nmCeleron M, Pentium Dual-Core533rowspan="3" | DDR2 533/6673/51rowspan="2" | Integrated GMA X3100Max. 400 MHzrowspan="2" | 13.5
GM96582965GM (GMCH)

|SLA9F (C0)

rowspan="2" | Core 2 Duorowspan="2" | 533/667/800rowspan="2" | 4/82Max. 500 MHz
PM96582965PM (MCH)

|SLA5U (C0)

colspan="2" | PCIe ×168
GL40rowspan="5" | Cantiga82GL40 (GMCH)

|SLB95 (B3)

SLGGM (A1)

| rowspan="5" | ICH9-M

rowspan="5" | July 2008{{Cite press release | publisher = Intel Corporation | title = INTEL ENABLES RICHER GRAPHICS, FASTER PERFORMANCE FOR EMBEDDED APPLICATIONS | date = 2008-07-15 | url = https://www.intel.com/pressroom/kits/centrino2/FactSheet_Mobile_Intel_GM45_Express_Chipset.pdf | access-date = 2025-02-16}}rowspan="5" | 65 nmCore 2 Duo, Celeron, Celeron M, Pentium Dual-Corerowspan="2" | 667/800rowspan="5" | DDR2 667/800, DDR3 800/10664/82rowspan="4" | Integrated GMA X4500MHDrowspan="2" | Max. 400 MHzrowspan="2" | 12
GS4082GS40 (GMCH)

|SLGT8 (B3)

Core 2 Duo, Celeron, Celeron M?, Pentium Dual-Core4
GS4582GS45 (GMCH) (For CULV)

|SLB92 (B3)

Core 2 Solo, Core 2 Duo, Core 2 Extreme, Celeron M800/1066rowspan="3" | 8rowspan="2" | Max. 533 MHz7/8/123
GM4582GM45 (GMCH)

|SLB94 (B3)

SLGGN (A1)

|Core 2 Duo, Core 2 Extreme, Celeron M

rowspan="2" | 667/800/106612
PM4582PM45 (MCH)

|SLB97 (B3)

SLGGN (A1)

|Core 2 Duo, Core 2 Quad, Core 2 Extreme

colspan="2" | PCIe ×167

  • 1 Unofficially this chipset support 5 GB.
  • 2 Officially only 4 GB is supported. Unofficially many laptops with this chipset support 8 GB.
  • 3 Low power mode, HD playback mode and Full performance mode respectively.

=Southbridge 9xx and 3/4 Series chipsets=

{{Main article|I/O Controller Hub}}{{None}}

class="wikitable" style="font-size: 90%;"
rowspan="2" | Chipset || rowspan="2" | Part
Number

! rowspan="2" |sSpec Number|| rowspan="2" | Parallel ATA || colspan="2" | Serial ATA

! rowspan="2" |AHCI Support

! rowspan="2" | RAID Levels || USB || rowspan="2" | TDP
[W]

3.0 Gbit/s1.5 Gbit/sv2.0
ICH6-M82801FBM

|SL7W6 (B2)

SL89K (B2)

|! rowspan="10" {{Yes|UDMA 100/66/33}}

rowspan="4" {{n/a}}2 ports

|{{Yes|Yes}}

{{No|None}}

|4 ports

| rowspan="3" | 3.8

ICH682801FB

|SL7AG (B1)

SL7Y5 (B2)

SL89L (B2)

SL8BZ (C0)

| rowspan="2" | 4 ports

|{{No|No}}

{{No|None}}

|8 ports

ICH6R82801FR

|SL79N (B1)

SL7W7 (B2)

SL89J (B2)

SL8C2 (C0)

|{{Yes|Yes}}

{{Yes|0, 1, Matrix}}

|8 ports

style="border-top:2px solid gray;"

| ICH7-M

82801GBM

|SL8YB (B0)

2 ports{{Yes|Yes}}

|{{No|None}}

rowspan="2" | 4 portsrowspan="5" | 3.3
ICH7-M DH82801GHM

|SL8YR (B0)

rowspan="4" | 4 portsrowspan="20" {{n/a}}

| {{Yes|Yes}}

{{Yes|0, 1, Matrix}}
ICH782801GB

|SL8FX (A1)

SLGSP

|{{No|No}}

{{No|None}}rowspan="3" | 8 ports
ICH7DH82801GDHSL8UK (A1){{Yes|Yes}}{{Yes|0, 1, Matrix}}
ICH7R82801GR

|SL8FY (A1)

SL8KL (A1)

| {{Yes|Yes}}

{{Yes|0, 1, 5, 10, Matrix}}
style="border-top:2px solid gray;"

| ICH8M

82801HBM

|SLA5Q (B1)

SLB9A (B2)

SLJ4Y (B2)

| rowspan="2" | 3 ports

|{{Yes|Yes}}

{{No|None}}rowspan="6" | 10 portsrowspan="2" | 2.4
ICH8M-E82801HEM

|SLA5R (B1)

SLB9B (B2)

|{{Yes|Yes}}

{{Yes|0, 1, Matrix}}
ICH882801HB

|SL9MN (B0)

rowspan="14" {{No}}4 ports

|{{No|No}}

{{No|None}}rowspan="4" | 3.7
ICH8R82801HRSL9MK (B0)rowspan="3" | 6 ports

|{{Yes|Yes}}

rowspan="3" {{Yes|0, 1, 5, 10, Matrix}}
ICH8DH82801HHSL9ML (B0){{Yes|Yes}}
ICH8DO82801HOSL9MM (B0){{Yes|Yes}}
style="border-top:2px solid gray;"

| ICH9M

82801IBM

|SLB8Q (A3)

rowspan="3" | 4 ports

|{{Yes|Yes}}

{{No|None}}rowspan="2" | 8 portsrowspan="2" | 2.5
ICH9M-E82801IEMSLB8P (A3){{Yes|Yes}}{{Yes|0, 1, Matrix}}
ICH982801IBSLA9M (A2){{Yes|No(Yes{{Cite web|url=https://www.bios-mods.com/forum/Thread-solved-How-to-add-AHCI-mod-to-ASUS-P5K-SE-bios-not-EPU|title=[solved] How to add AHCI mod to ASUS "P5K SE" bios not EPU ?|website=www.bios-mods.com|access-date=2016-10-22}})}}{{No|None}}rowspan="8" | 12 portsrowspan="4" | 4.3
ICH9R82801IRSLA9N (A2)

SLAXE (A2)

| rowspan="7" | 6 ports

|{{Yes|Yes}}

rowspan="3" {{Yes|0, 1, 5, 10, Matrix}}
ICH9DH82801IHSLA9P (A2){{Yes|Yes}}
ICH9DO82801IOSLAFD (A2){{Yes|Yes}}
style="border-top:2px solid gray;"

| ICH10

82801JBSLB8R (A0){{Yes|Yes}}rowspan="2" {{No|None}}rowspan="4" | 4.5
ICH10D82801JHSLG8T (B0){{Yes|Yes}}
ICH10R82801JRSLB8S (A0){{Yes|Yes}}rowspan="2" {{Yes|0, 1, 5, 10, Matrix}}
ICH10DO82801JO|{{Yes|Yes}}

{{anchor|56789SERIES}}5/6/7/8/9 Series chipsets

The Nehalem microarchitecture moves the memory controller into the processor. For high-end Nehalem processors, the X58 IOH acts as a bridge from the QPI to PCI Express peripherals and DMI to the ICH10 southbridge. For mainstream and lower-end Nehalem processors, the integrated memory controller (IMC) is an entire northbridge (some even having GPUs), and the PCH (Platform Controller Hub) acts as a southbridge.

=LGA 1156=

{{Main article|Intel 5 Series}}

Chipsets supporting LGA 1156 CPUs (Lynnfield and Clarkdale).

Not listed below is the 3450 chipset (see Xeon chipsets) which is compatible with Nehalem mainstream and high-end processors but does not claim core iX-compatibility. With either a Core i5 or i3 processor, the 3400-series chipsets enable the ECC functionality of unbuffered ECC memory.{{cite web |title=Intel correspondence quoted on silentpcreview forum |url=http://www.silentpcreview.com/forums/viewtopic.php?f=13&t=60512&start=60 |url-status=dead |archive-url=https://web.archive.org/web/20120105202008/http://www.silentpcreview.com/forums/viewtopic.php?f=13&t=60512&start=60 |archive-date=2012-01-05 |access-date=2011-09-26}} Otherwise these chipsets do not enable unbuffered ECC functionality.

class="wikitable" style="font-size: 90%;"
rowspan="2" | Chipset

! rowspan="2" | Code{{Br}}name

! rowspan="2" | sSpec{{Br}}number

! rowspan="2" | Part{{Br}}numbers

! rowspan="2" | Release{{Br}}Date

! rowspan="2" | Bus{{Br}}Interface

! rowspan="2" | Link{{Br}}Speed

! rowspan="2" | PCI Express lanes

! rowspan="2" | PCI

! SATA

USB

! rowspan="2" | FDI{{Br}}support

! rowspan="2" | TDP

3 Gbit/sv2.0
H55

| rowspan="4" | Ibex Peak

SLGZX(B3)BD82H55 (PCH)Jan 2010

| rowspan="4" | DMI 1.0

| rowspan="4" | 1 GB/s

6 PCIe 2.0 at 2.5 GT/s

| rowspan="4" {{Yes}}

| rowspan="4" | 6 ports

12 ports{{Yes}}5.2 W
P55SLH24 (B3),
SLGWV (B2)
BD82P55 (PCH)Sep 2009

| rowspan="3" | 8 PCIe 2.0 at 2.5 GT/s

| rowspan="3" | 14 ports

{{No}}4.7 W
H57SLGZL(B3)BD82H57 (PCH)

| rowspan="2" | Jan 2010

| rowspan="2" {{Yes}}

5.2 W
Q57SLGZW(B3)BD82Q57 (PCH)5.1 W

=LGA 1155=

{{See also

| LGA 1155#Sandy Bridge family of chipsets | label 1=Sandy Bridge chipsets (6 Series)

| LGA 1155#Ivy Bridge family of chipsets | label 2=Ivy Bridge chipsets (7 Series)}}

Chipsets supporting LGA 1155 CPUs (Sandy Bridge and Ivy Bridge). The PCIe 2.0 lanes from the PCH ran at 5 GT/s in this series, unlike in the previous LGA 1156 chips.{{cite web |url=https://www.anandtech.com/show/3574 |title=P55 Chipset - Quick Primer |author=Gary Key |publisher=AnandTech.com |date=2009-09-08 |access-date=2019-05-05 |archive-url=https://web.archive.org/web/20190504233100/https://www.anandtech.com/show/3574 |archive-date=2019-05-04 |url-status=live }}

The Cougar Point Intel 6 series chipsets with stepping B2 were recalled due to a hardware bug that causes their 3 Gbit/s Serial ATA to degrade over time until they become unusable. Stepping B3 of the Intel 6 series chipsets will have the fix for this. The Z68 chipset which supports CPU overclocking and use of the integrated graphics does not have this hardware bug, however all other ones with B2 did.{{cite web |title=Intel Discovers Bug in 6-Series Chipset: Our Analysis |url=http://www.anandtech.com/show/4142/intel-discovers-bug-in-6series-chipset-begins-recall |url-status=live |archive-url=https://web.archive.org/web/20131224114540/http://www.anandtech.com/show/4142/intel-discovers-bug-in-6series-chipset-begins-recall |archive-date=2013-12-24 |access-date=2014-01-19 |publisher=AnandTech}} The Z68 also added support for transparently caching hard disk data on to solid-state drives (up to 64 GB), a technology called Smart Response Technology.[http://www.pcper.com/reviews/Storage/Intel-Smart-Response-Technology-SSD-Caching-Z68-Tested/Boot-Option-ROM-Boot-Performa Intel Smart Response Technology: SSD Caching on Z68 Tested] {{Webarchive|url=https://web.archive.org/web/20120404031013/http://pcper.com/reviews/Storage/Intel-Smart-Response-Technology-SSD-Caching-Z68-Tested/Boot-Option-ROM-Boot-Performa|date=2012-04-04}}, PC Perspective

class="wikitable" style="font-size: 90%;"
rowspan="2" | Chipset

! rowspan="2" | Code{{Br}}name

! rowspan="2" | sSpec{{Br}}number

! rowspan="2" | Part{{Br}}numbers

! rowspan="2" | Release{{Br}}date

! rowspan="2" | Bus{{Br}}interface

! rowspan="2" | Link{{Br}}speed

! rowspan="2" | PCI Express{{Br}}lanes

! rowspan="2" | PCI

! colspan="2" | SATA

! colspan="2" | USB

! rowspan="2" | FDI{{Br}}support

! rowspan="2" | TDP

6 Gbit/s

! 3 Gbit/s

! v3.2 Gen 1x1

! v2.0

H611

| rowspan="7" | Cougar Point

SLH83(B2)
SLJ4B(B3)
BD82H61 (PCH)February 20, 2011

| rowspan="13" | DMI 2.0

| rowspan="13" | 2 GB/s

6 PCIe 2.0{{No}}{{no|None}}4 ports

| rowspan="7" {{no|None}}

10 ports

| rowspan="3" {{Yes}}

| rowspan="7" | 6.1 W

B651SLH98(B2)
SLJ4A(B3)
BD82B65 (PCH)February 25, 2011

| rowspan="12" | 8 PCIe 2.0

| rowspan="2" {{Yes}}

| rowspan="2" | 1 port

| rowspan="2" | 5 ports

12 ports
Q651SLH99(B2)
SLJ4E(B3)
BD82Q65 (PCH)Q2 2011

| rowspan="5" | 14 ports

P671SLH84(B2) (Recalled)
SLJ4C (B3)
BD82P67 (PCH)

| rowspan="2" | January 9, 2011

| rowspan="2" {{No}}

| rowspan="4" | 2 ports

| rowspan="4" | 4 ports

{{No}}
H671SLH82(B2) (Recalled)
SLJ49 (B3)
BD82H67 (PCH)

| rowspan="9" {{Yes}}

Q671SLH85(B2)
SLJ4D(B3)
BD82Q67 (PCH)February 20, 2011{{yes}}
Z681SLJ4F(B3)BD82Z68 (PCH)May 11, 2011{{No}}
B752

| rowspan="6" | Panther Point

SLJ85(C1)BD82B75 (PCH)

| rowspan="2" | May 13, 2012

| rowspan="2" {{Yes}}

| rowspan="2" | 1 port

| rowspan="2" | 5 ports

| rowspan="6" | 4 ports

8 ports

| rowspan="6" | 6.7 W

Q752SLJ84(C1)BD82Q75 (PCH)

| rowspan="5" | 10 ports

Z752SLJ87(C1)BD82Z75 (PCH)

| rowspan="2" | April 8, 2012

| rowspan="2" {{No}}

| rowspan="4" | 2 ports

| rowspan="4" | 4 ports

H772SLJ88(C1)BD82H77 (PCH)
Q772SLJ83(C1)BD82Q77 (PCH)May 13, 2012{{Yes}}
Z772SLJC7(C1)BD82Z77 (PCH)April 8, 2012{{No}}

  • 1 For Sandy Bridge mainstream desktop and business platforms. Sandy Bridge CPUs provide 16 PCIe 2.0 lanes for direct GPU connectivity.
  • 2 For Ivy Bridge mainstream desktop platform. Ivy Bridge CPUs provide 16 PCIe 3.0 lanes for direct GPU connectivity and additional 4 PCIe 2.0 lanes.{{cite web |author=Paul Goodhead |url=http://www.bit-tech.net/news/hardware/2011/03/29/leaked-slide-confirms-pci-e-3-0-for-intel-c/1 |title=Leaked slide confirms PCIe 3.0 for Intel Ivy Bridge CPUs |publisher=bit-tech.net |date=2011-03-29 |access-date=2014-01-19 |archive-url=https://web.archive.org/web/20131021143309/http://www.bit-tech.net/news/hardware/2011/03/29/leaked-slide-confirms-pci-e-3-0-for-intel-c/1 |archive-date=2013-10-21 |url-status=live }}

= LGA 1150 =

{{See also | LGA 1150#Haswell chipsets | label 1=Haswell / Broadwell chipsets (8/9 Series)}}

Chipsets that support LGA 1150 CPUs are listed below. Haswell and Haswell Refresh CPUs are supported by all listed chipsets; however, a BIOS update is usually required for 8-Series Lynx Point motherboards to support Haswell Refresh CPUs.{{cite web |url=https://www.asus.com/Motherboards/Z87DELUXE/HelpDesk_CPU/ |title=Motherboards - Z87-DELUXE |publisher=ASUS |access-date=2014-07-26 |archive-url=https://web.archive.org/web/20140523064443/http://www.asus.com/Motherboards/Z87DELUXE/HelpDesk_CPU/ |archive-date=2014-05-23 |url-status=live }} Broadwell CPUs are supported only by 9-Series chipsets, which are usually referred to as Wildcat Point.{{cite web|url=https://ark.intel.com/products/codename/37530/Lynx-Point|title=Products (Formerly Lynx Point)|work=Intel ARK (Product Specs)|access-date=2017-10-07|archive-url=https://web.archive.org/web/20171007070048/https://ark.intel.com/products/codename/37530/Lynx-Point|archive-date=2017-10-07|url-status=live}}

The C1 stepping of the Lynx Point chipset contains a bug{{snd}}a system could lose connectivity with USB devices plugged into USB 3.0 ports provided by the chipset if the system enters the S3 sleep mode.{{Cite news |url=http://www.pcauthority.com.au/News/335598,intels-upcoming-z87-chipset-has-an-annoying-usb-3-bug.aspx |first=John |last=Gilloy |title=Intel's upcoming Z87 chipset has an annoying USB 3 bug |date=6 March 2013 |newspaper=PC & Tech Authority |access-date=5 November 2014 |archive-url=https://web.archive.org/web/20141106044323/http://www.pcauthority.com.au/News/335598,intels-upcoming-z87-chipset-has-an-annoying-usb-3-bug.aspx |archive-date=6 November 2014 |url-status=live }}

class="wikitable" style="font-size: 90%;"
rowspan="2" | Chipset

! rowspan="2" | Code

name

! rowspan="2" | sSpec

number

! rowspan="2" | Part

numbers

! rowspan="2" | Release

date

! rowspan="2" | Bus

interface

! rowspan="2" | Link

speed

! rowspan="2" | PCI Express

lanes

! rowspan="2" | VT-d

support

! rowspan="2" | PCI

! colspan="2" | SATA

! colspan="2" | USB

! rowspan="2" | FDI

support

! rowspan="2" | TDP

! rowspan="2" | PCIe M.2

support

6 Gbit/s3 Gbit/sv3.2 Gen 1x1v2.0
H81

| rowspan="6" | Lynx Point

SR13B(C1)
SR177(C2)
DH82H81 (PCH)

| rowspan="6" | June 2013

| rowspan="8" | DMI 2.0

| rowspan="8" | 2 GB/s

6 PCIe 2.0

| rowspan="3" {{No}}

| rowspan="8" {{No}}

2 ports

| rowspan="3" | 2 ports

2 ports

| rowspan="8" | 8 ports

| rowspan="8" {{Yes}}

| rowspan="8" | 4.1 W

| rowspan="6" {{No}}

B85SR13C(C1)
SR178(C2)
DH82B85 (PCH)

| rowspan="7" | 8 PCIe 2.0

| rowspan="2" | 4 ports

4 ports
Q85SR138(C1)
SR174(C2)
DH82Q85 (PCH)

| rowspan="6" | 6 ports

Q87SR137(C1)
SR173(C2)
SR19E(C2)
DH82Q87 (PCH){{Yes}}

| rowspan="5" | 6 ports

| rowspan="5" {{no|None}}

H87SR139(C1)
SR175(C2)
DH82H87 (PCH)

| rowspan="4" {{No}}

Z87SR13A(C1)
SR176(C2)
DH82Z87 (PCH)
Z97

| rowspan="2" | Wildcat Point

SR1JJ(A0)DH82Z97 (PCH)

| rowspan="2" | May 2014

| rowspan="2" {{Yes}}

H97SR1JK(A0)DH82H97 (PCH)

=LGA 1366, LGA 2011, and LGA 2011-v3=

Single socket chipsets supporting LGA 1366, LGA 2011, and LGA 2011-v3 CPUs. Please consult List of Intel Xeon chipsets for further, multi-socket, chipsets for these sockets.

class="wikitable" style="font-size: 90%;"
rowspan="2" | Chipset

! rowspan="2" | Code name

! rowspan="2" | sSpec Number

! rowspan="2" | Part

numbers

! rowspan="2" | Release date

! rowspan="2" | Socket

! rowspan="2" | Bus

interface

! rowspan="2" | Link

speed{{Efn|name="aggrLink"|Aggregated speed for both directions}}

! rowspan="2" | PCI Express lanes

! rowspan="2" | VT-d

support

! rowspan="2" | PCI

! colspan="2" | SATA

! colspan="2" | USB

! rowspan="2" | FDI

support

! rowspan="2" | TDP

6 Gbit/s3 Gbit/sv3.2 Gen 1x1v2.0
X58 (I/O hub)1TylersburgSLGBT (B2),
SLGMX (B3),
SLH3M (C2)
AC82X58 (IOH)November 2008LGA 1366QPIUp to 25.6 GB/s36 PCIe 2.0 at 5 GT/s (IOH);
6 PCIe 1.1 (ICH)
rowspan="3" {{Yes}}rowspan="2" {{Yes}}{{no|None}}6 ports

| rowspan="2" {{no|None}}

12 portsrowspan="3" {{No}}28.6 W2
X793PatsburgSLJHW (C0),{{cite web|url=https://www.intel.com/content/dam/doc/specification-update/x79-express-chipset-specification-update.pdf |title=Archived copy |access-date=December 24, 2013 |url-status=dead |archive-url=https://web.archive.org/web/20120629144936/https://www.intel.com/content/dam/doc/specification-update/x79-express-chipset-specification-update.pdf |archive-date=June 29, 2012 }}
SLJN7 (C1){{cite web |url=https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/c600-series-chipset-spec-update.pdf |title=Spec listing |website=www.intel.com |access-date=2017-10-07 |archive-url=https://web.archive.org/web/20181210232413/https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/c600-series-chipset-spec-update.pdf |archive-date=2018-12-10 |url-status=live }}
BD82X79 (PCH){{cite web|url=https://ark.intel.com/products/chipsets/64013|title=ARK - Intel X79 Express Chipset (Intel BD82X79 PCH)|work=Intel ARK (Product Specs)|access-date=12 February 2015|archive-url=https://web.archive.org/web/20120529123006/http://ark.intel.com/products/chipsets/64013|archive-date=29 May 2012|url-status=live}}November 14, 2011LGA 2011rowspan="2" | DMI 2.0rowspan="2" | 32 GB/srowspan="2" | 40 PCIe 3.02 ports4 ports14 ports7.8 W
X994WellsburgSLKDE (B1),
SLKM9 (B1)
DH82031PCH (PCH)August 29, 2014LGA 2011-v3{{No}}10 ports{{no|None}}6 ports8 ports6.5 W

  • 1 X58 South Bridge is ICH10/ICH10R.
  • 2 X58 TDP includes the X58 IOH TDP in addition to the ICH10/ICH10R TDP.
  • 3 For Sandy Bridge enthusiast desktop platform. Sandy Bridge CPUs will provide up to 40 PCIe 3.0 lanes for direct GPU connectivity and additional 4 PCIe 2.0 lanes. NOTE : This reference number 4 is on X79, which is a Sandy bridge -E, not Sandy Bridge, and PCIe 3.0 only is enabled when an Ivy Bridge-E CPU or Xeon E-5 series is used.
  • 4 For Haswell enthusiast desktop platform. Haswell CPUs will provide up to 40 PCIe 3.0 lanes for direct GPU connectivity and additional 4 PCIe 2.0 lanes.

=LGA 2066=

Chipsets supporting LGA 2066 socket for Skylake-X processors and Kaby Lake-X processors.

The C621 Chipset also supports LGA 3647 socket for Skylake-SP as well as Cascade Lake-W and Cascade Lake-SP processors.

class="wikitable" style="font-size: 90%;"
rowspan="2" | Chipset

! rowspan="2" | Code

name

! rowspan="2" | sSpec

number

! rowspan="2" | Part numbers

! rowspan="2" | Release Date

! rowspan="2" | Bus

interface

! rowspan="2" | Link

speed{{Efn|name="aggrLink"}}

! rowspan="2" | PCI Express lanes

! SATA

! rowspan="2" | SATAe

! rowspan="2" | PCIe

M.2

! rowspan="2" | QAT

! colspan="2" | USB ports

! rowspan="2" | TDP

6 Gbit/sv3.0v2.0
X299Basin FallsSR2Z2(A0)GL82X299May 30, 2017rowspan="2" | DMI 3.0rowspan="2" |

32 GB/s

| rowspan="2" | 16 PCIe 3.0 (for i5), 28-44 PCIe 3.0 (i7), 48 PCIe 3.0 (i9)

{{dunno}}{{dunno}}rowspan="5" | Norowspan="9" | Up to 10rowspan="9" | Up to 14rowspan="9" | ?6 W
C422

|Kaby Lake

|SR2WG(A0)

|GL82C422

| rowspan="8" | July 11, 2017

|24 PCIe 3.0

| rowspan="8" |?

|6 W

C621

| rowspan="7" | Lewisburg

|SR36S(B1)
SR354(S0)
SR3HE(B2)
SR3HL(S1)

|EY82C621x

| rowspan="7" | UPI

| rowspan="7" | 32 GB/s

| rowspan="7" | 48 PCIe 3.0

| rowspan="7" | Up to 14

|15 W

C622

|SR36X(S0)
SR3HK(S1)

|EY82C622

|17 W

C624

|SR36Y(S0)
SR3HM(S1)

|EY82C624

|19 W

C625

|SR36W(B1)
SR3HJ(B2)

|EY82C625

|rowspan="4" | Yes

|21 W

C626

|SR36V(B1)
SR3HH(B2)

|EY82C626

|23 W

C627

|SR36U(B1)
SR3HG(B2)

|EY82C627

|28.6 W

C628

|SR36T(B1)
SR3HF(B2)

|EY82C628

|26.3 W

=Dedicated mobile chipsets=

All Core-i series mobile chipsets have an integrated south bridge.

class="wikitable" style="font-size: 90%;"
rowspan="2" | Chipset

! rowspan="2" | Code

name

! rowspan="2" | sSpec

number

! rowspan="2" | Part

numbers

! rowspan="2" | Release date

! rowspan="2" | Process

support

! rowspan="2" | Bus

interface

! rowspan="2" | Link

speed

! rowspan="2" | PCI Express

lanes

! rowspan="2" | VT-d

support

! colspan="2" | SATA

! colspan="2" | USB

! rowspan="2" | FDI

support

! rowspan="2" | TDP

6 Gbit/s3 Gbit/sv3.2 Gen 1x1v2.0
PM55

| rowspan="5" | Ibex Peak-M

SLGWN(B2),
SLH23(B3),
SLGWP
BD82PM55 (PCH)September 2009

| rowspan="5" | 45 nm, 32 nm

| rowspan="5" | DMI

| rowspan="5" | 1 GB/s

8 PCIe 2.0rowspan="5" {{Yes}}

| rowspan="5" {{no|None}}

6 ports

| rowspan="11" {{no|None}}

14 ports{{No}}

| rowspan="4" | 3.5 W

HM55SLGZS(B3)BD82HM55 (PCH)

| rowspan="4" | January 2010

6 PCIe 2.04 ports12 ports

| rowspan="21" {{Yes}}

HM57SLGZR(B3)BD82HM57 (PCH)

| rowspan="3" | 8 PCIe 2.0

| rowspan="3" | 6 ports

| rowspan="3" | 14 ports

QM57SLGZQ(B3)BD82QM57 (PCH)
QS57SLGZV(B3)BD82QS57 (PCH)3.4 W
HM65

| rowspan="5" | Cougar Point-M

SLH9D(B2) (Recalled)
SLJ4P(B3)
BD82HM65 (PCH)

| rowspan="2" | January 9, 2011

| rowspan="5" | 32 nm

| rowspan="17" | DMI 2.0

| rowspan="17" | 2 GB/s

| rowspan="5" | 8 PCIe 2.0

| rowspan="3" {{No}}

| rowspan="5" | 2 ports

| rowspan="5" | 4 ports

12 ports

| rowspan="2" | 3.9 W

HM67SLH9C(B2) (Recalled)
SLJ4N(B3)
BD82HM67 (PCH)

| rowspan="4" | 14 ports

UM67SLH9U(B2)
SLJ4L(B3)
BD82UM67 (PCH)

| rowspan="3" | February 20, 2011

3.4 W
QM67SLH9B(B2)
SLJ4M(B3)
BD82QM67 (PCH)rowspan="2" {{Yes}}3.9 W
QS67SLHAG(B2)
SLJ4K(B3)
BD82QS67 (PCH)3.4 W
NM70

| rowspan="8" | Panther Point-M

SLJTA(C1)BD82NM70 (PCH)August 2012

| rowspan="12" | 22 nm

4 PCIe 2.0{{Dunno}}

| rowspan="2" | 1 port

3 ports8 ports

| rowspan="4" | 4.1 W

HM70SJTNV(C1)BD82HM70 (PCH)

| rowspan="7" | April 8, 2012

| rowspan="3" | 8 PCIe 2.0

rowspan="5" {{No}}

| rowspan="3" | 4 ports

4 ports6 ports
HM75SLJ8F(C1)BD82HM75 (PCH)

| rowspan="2" | 2 ports

{{no|None}}12 ports
HM76SLJ8E(C1)BD82HM76 (PCH)

| rowspan="5" | 4 ports

8 ports
UM77SLJ8D(C1)BD82UM77 (PCH)4 PCIe 2.01 port3 ports6 ports3.0 W
HM77SLJ8C(C1)BD82HM77 (PCH)

| rowspan="7" | 8 PCIe 2.0

| rowspan="3" | 2 ports

| rowspan="3" | 4 ports

| rowspan="4" | 10 ports

| rowspan="2" | 4.1 W

QM77SLJ8A(C1)BD82QM77 (PCH)rowspan="5" {{Yes}}
QS77SLJ8B(C1)BD82QS77 (PCH)3.0 to 3.6 W
HM86

| rowspan="3" | Lynx Point-M

SR13J(C1)
SR17E(C2)
DH82HM86 (PCH)

| rowspan="3" | June 2013

| rowspan="4" | 4 ports

| rowspan="4" | 2 ports

5 ports

| rowspan="4" | 2.7 W

QM87SR13G(C1)
SR17C(C2)
DH82QM87 (PCH)

| rowspan="3" | 6 ports

8 ports
HM87SR13H(C1)
SR17D(C2)
DH82HM87 (PCH)

| rowspan="2" | 10 ports

HM97Wildcat Point-MSR1JN(A0)DH82HM97 (PCH)May 2014

| rowspan="1" {{Dunno}}

= On-package mobile chipsets =

Every 4th Generation Intel Core and 5th Generation Intel Core processor based on Mobile U-Processor and Y-Processor Lines has an on-package Platform Controller Hub.{{Cite web |last=Hassan |first=Mujtaba |date=Nov 12, 2012 |title=Intel Haswell ULT Processors Power Saving Features and Lynx Point-LP Chipset Detailed |url=https://wccftech.com/intel-haswell-ult-processors-power-saving-features-lynx-point-lp-chipset-detailed/}}

class="wikitable" style="font-size: 90%"

! rowspan="2" | CPU on-package chipset

! rowspan="2" | Code name

! rowspan="2" | Release date

! rowspan="2" | Process support

! rowspan="2" | Bus interface

! rowspan="2" | Link speed

! rowspan="2" | PCI Express lanes

! rowspan="2" | VT-d support

! colspan="2" | SATA

! colspan="2" | USB

! rowspan="2" | FDI support

! rowspan="2" width="6%"| TDP

6 Gbit/s3 Gbit/sv3.2 Gen 1x1v2.0
8 series low-power, premium

|Lynx Point-LP

|June 2013

|22 nm

|OPI✕8

| {{unknown}}

|12 PCIe 2.0

| {{Yes}}

|Up to 3

|Up to 4

|Up to 4

|8

| {{No}}

| {{unknown}}

9 series U-processor line, base{{Cite web |title=5th-gen-core-family-platform-i-o-datasheet |url=https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/5th-gen-core-family-platform-i-o-datasheet.pdf}}

| rowspan="3" |Wildcat Point-LP

| rowspan="2" |January 2015

|?

| rowspan="3" |DMI 2.0

| rowspan="3" {{Unknown}}

|10 PCIe 2.0

| rowspan="3" {{Yes}}

| colspan="2" |2

| rowspan="3" |Up to 4

| rowspan="2" |8

| rowspan="3" {{Yes}}

| rowspan="3" {{Unknown}}

9 series U-processor line, premium

|?

| rowspan="2" |12 PCIe 2.0

| colspan="2" rowspan="2" |Up to 4

9 series Core M processor line, premium

|September 2014

|?

|10

100/200/300 Series chipsets

=LGA 1151 rev 1=

{{See also

| LGA_1151#Skylake chipsets (100 series) | label 1=Skylake chipsets (100 series)

| LGA 1151#Kaby Lake chipsets (200 series) | label 2=Kaby Lake chipsets (200 series)}}

The 100 Series chipsets (codenamed Sunrise Point), for Skylake processors using the LGA 1151 socket,{{cite web|url=http://hexus.net/tech/news/mainboard/80342-intels-skylake-100-series-chipset-revealed/|title=Intel's Skylake 100-Series chipset is revealed|work=hexus.net|date=4 February 2015 |access-date=12 February 2015|archive-url=https://web.archive.org/web/20150207164325/http://hexus.net/tech/news/mainboard/80342-intels-skylake-100-series-chipset-revealed/|archive-date=7 February 2015|url-status=live}} were released in the third quarter of 2015.{{cite web |url=https://ark.intel.com/products/codename/37572/Skylake |title=Products formerly Skylake |website=Intel ARK |access-date=2017-03-09 |archive-url=https://web.archive.org/web/20170330002953/https://ark.intel.com/products/codename/37572/Skylake |archive-date=2017-03-30 |url-status=live }}

The 200 Series chipsets (codenamed Union Point) were introduced along with Kaby Lake processors, which also use the LGA 1151 socket;{{cite news|last1=Cutress|first1=Ian|last2=Shilov|first2=Anton|title=Desktop Kaby Lake-S i7/i5 Lineup and 200-Series Chipsets Leaked|url=http://www.anandtech.com/show/10802/desktop-kaby-lakes-lineup-base-frequencies-chipset-names|access-date=31 October 2016|publisher=Anandtech|date=31 October 2016|archive-url=https://web.archive.org/web/20161101101832/http://www.anandtech.com/show/10802/desktop-kaby-lakes-lineup-base-frequencies-chipset-names|archive-date=1 November 2016|url-status=live}} these were released in the first quarter of 2017.{{cite web |url=https://ark.intel.com/products/codename/82879/Kaby-Lake |title=Products formerly Kaby Lake |website=Intel ARK |access-date=2017-03-09 |archive-url=https://web.archive.org/web/20170312034430/http://ark.intel.com/products/codename/82879/Kaby-Lake |archive-date=2017-03-12 |url-status=live }}

class="wikitable" style="font-size: 90%;"
rowspan="2" | Chipset

! rowspan="2" | Code
Name

! rowspan="2" | sSpec
Number

! rowspan="2" | Part
numbers

! rowspan="2" | Release Date

! rowspan="2" | Bus
Interface

! rowspan="2" | Link
Speed

! rowspan="2" | PCI Express
lanes

! rowspan="2" | Optane

Memory

support

! SATA

! rowspan="2" | SATAe

! rowspan="2" | PCIe

M.2

! rowspan="2" | Wireless
MAC

! colspan="3" | USB ports

! rowspan="2" | TDP

6 Gbit/sv3.2 Gen 1x1v3.2 Gen 2x1Total
H110

| rowspan="6" | Sunrise
Point

SR2CA(D1)
SR286
GL82H110
(PCH)
Sep. 27, 2015DMI 2.02.0 GB/s6 PCIe 2.0

| rowspan="6" {{No}}

4{{no|None}}

| rowspan="3" {{no|None}}

| rowspan="11" {{no}}

Up to 4

| rowspan="11" {{No|None}}

| Up to 10

| rowspan="11" | 6 W

B150SR2C7(D1)
SR283
GL82B150
(PCH)
Sep. 1, 2015

| rowspan="10" | DMI 3.0

| rowspan="10" | 3.93 GB/s

8 PCIe 3.0

| rowspan="10" | 6

| rowspan="2" | Up to 1

Up to 6

| Up to 12

Q150SR2C6(D1)
SR282
GL82Q150
(PCH)
H2 201510 PCIe 3.0

| rowspan="2" | Up to 8

| rowspan="4" | Up to 14

H170SR2C8(D1)
SR284
GL82H170
(PCH)
Sep. 1, 201516 PCIe 3.0Up to 2Up to 2
Q170SR2C5(D1)
SR281
GL82Q170
(PCH)
Oct. 2015

| rowspan="2" | 20 PCIe 3.0

| rowspan="2" | Up to 3

| rowspan="2" | Up to 3

| rowspan="2" | Up to 10

Z170SR2C9(D1)
SR285
GL82Z170
(PCH)
Aug. 2015
B250rowspan=5| Union
Point
SR2WC(A0)GL82B250rowspan = 5| Jan. 3, 201712 PCIe 3.0rowspan = 5 {{Yes}}rowspan = 2|Up to 1rowspan = 2|Up to 1Up to 6

| Up to 12

Q250SR2WD(A0)GL82Q25014 PCIe 3.0rowspan=2|Up to 8

| rowspan="4" |Up to 14

H270SR2WA(A0)GL82H27020 PCIe 3.0Up to 2Up to 2
Q270SR2WE(A0)GL82Q270rowspan=2|24 PCIe 3.0rowspan=2|Up to 3rowspan=2|Up to 3rowspan=2|Up to 10
Z270SR2WB(A0)GL82Z270

=LGA 1151 rev 2=

File:Intel B360 Cannon Point Chipset Die Shot.png

{{See also | LGA 1151#Coffee Lake chipsets (300 series and C240 series) | label 1=Coffee Lake chipsets (300 series)}}

While Coffee Lake shares the same socket as Skylake and Kaby Lake, this revision of LGA 1151 is electrically incompatible with 100 and 200 series CPUs.

The 300 Series chipsets were introduced along with Coffee Lake processors, which use the LGA 1151 socket; the enthusiast model was released in the last quarter of 2017,{{cite web |url=https://ark.intel.com/products/codename/125903 |title=Intel Z370 Chipset |website=Intel ARK |access-date=2018-02-21}} the rest of the line was released in 2018.{{cite web|url=https://www.gamersnexus.net/news-pc/3069-hw-news-intel-h370-b360-zen2-aib-partner-vega-cards|title=HW News: Intel H370, B360, & BGA Pentiums, Zen+ & Zen 2|work=gamersnexus.net|date=28 September 2017 |access-date=2018-02-21|archive-url=https://web.archive.org/web/20180221222536/https://www.gamersnexus.net/news-pc/3069-hw-news-intel-h370-b360-zen2-aib-partner-vega-cards|archive-date=2018-02-21|url-status=live}}

class="wikitable" style="font-size: 90%;"
rowspan="2" | Chipset

! rowspan="2" | Code
Name

! rowspan="2" | sSpec
Number

! rowspan="2" | Part
numbers

! rowspan="2" | Release Date

! rowspan="2" | Bus
Interface

! rowspan="2" | Link
Speed

! rowspan="2" | PCI Express
lanes

! rowspan="2" | Optane
Memory

support

! SATA

! rowspan="2" | SATAe

! rowspan="2" | PCIe M.2

! rowspan="2" | Wireless
MAC

! colspan="3" | USB ports

! rowspan="2" | TDP

6 Gbit/sv3.2 Gen 1x1v3.2 Gen 2x1Total
Z370rowspan="3" | Cannon PointSR3MD(A0)GL82Z370October 5, 2017DMI 3.03.93 GB/s24 PCIe 3.0{{yes}}6up to 3up to 3{{no}}Up to 10rowspan=2 {{no|None}}Up to 14rowspan="7" | 6 W
H310SR409(B0)
SRCXT(B0)
SRCXY(B0)
rowspan="5" | ?rowspan=2|April 3, 2018DMI 2.02.0 GB/s6 PCIe 2.0{{No}}4{{no|None}}{{no|None}}rowspan="2" |WiFi 5Up to 4Up to 10
B360SR408(B0)rowspan="5" |DMI 3.0rowspan="5" |3.93 GB/s12 PCIe 3.0rowspan=5 {{Yes}}rowspan="5" |6Up to 1Up to 1Up to 6

|Up to 4

Up to 12
B365Union PointSREVJ(A0)Dec. 14, 2018rowspan=2|20 PCIe 3.0rowspan=2| Up to 2rowspan=2 | Up to 2{{no}}rowspan=2 |Up to 8

|{{no|None}}

rowspan="4" | Up to 14
H370rowspan="3" |Cannon PointSR405(B0)April 3, 2018

| rowspan="3" |WiFi 5

|Up to 4

Q370SR404(B0)

|Q2 2018

rowspan="2" | 24 PCIe 3.0rowspan="2" | Up to 3rowspan="2" | Up to 3rowspan="2" | Up to 10

| rowspan="2" | Up to 6

Z390SR406(B0)FH82Z390October 8, 2018

=Xeon chipsets=

C232 and C242 chipsets do not support CPU integrated GPUs, as they lack FDI support. Officially they support only Xeon processors, but some motherboards also support consumer processors (6/7th generation Core for C230 series, 8/9th generation Core for C240 series and its Pentium/Celeron derivatives).

class="wikitable" style="font-size: 90%;"
rowspan="2" | Chipset

! rowspan="2" | Code

name

! rowspan="2" | sSpec

number

! rowspan="2" | Part numbers

! rowspan="2" | Release date

! rowspan="2" | Bus

interface

! rowspan="2" | Link

speed

! rowspan="2" | PCI Express

lanes

! SATA

! rowspan="2" | SATAe

! rowspan="2" | PCIe

M.2

! rowspan="2" | Wireless
MAC

! colspan="3" | USB ports

! rowspan="2" | TDP

6 Gbit/sv3.2 Gen 1x1v3.2 Gen 2x1Total
C232

| rowspan="2" | Sunrise Point

SR2CB(D1)GL82C232 (PCH)

| rowspan="2" | September 1, 2015

| rowspan="4" | DMI 3.0

| rowspan="4" | 3.93 GB/s

| 8 PCIe 3.0

| Up to 6

| rowspan="2" | Up to 3

| Up to 1

| rowspan=3 {{no}}

| Up to 6

| rowspan=2 {{no|None}}

| Up to 12

| rowspan="4" | 6 W

C236SR2CC(D1)GL82C236 (PCH)

| 20 PCIe 3.0

| Up to 8

| Up to 3

| Up to 10

| Up to 14

C242

| rowspan="2" | Coffee Lake

| SR40C(B0)

| FH82C242

| November 2018

| 10 PCIe 3.0

| Up to 6

| rowspan="2" | ?

| Up to 1

| Up to 6

| Up to 2

| Up to 12

C246

| SR40A(B0)

| FH82C246

| July 2018

| 24 PCIe 3.0

| Up to 8

| Up to 3

| WiFi 5

| Up to 10

| Up to 6

| Up to 14

= Dedicated mobile chipsets =

class="wikitable" style="font-size: 90%;"
rowspan="3" | Chipset

! rowspan="3" | Code Name

! rowspan="3" | sSpec Number

! rowspan="3" | Part numbers

! rowspan="3" | Release Date

! rowspan="3" | Bus Interface

! rowspan="3" | Link Speed

! rowspan="3" | PCI Express lanes

! SATA

! rowspan="3" | SATAe

! rowspan="3" | PCIe M.2

! rowspan="3" | Wireless
MAC

! colspan="3" | USB ports

! rowspan="3" | TDP

rowspan="2" | 6 Gbit/s ports

! colspan="2" | v3.2

! rowspan="2" | v2.0

Gen 1x1Gen 2x1
HM170

| rowspan="8" | Sunrise
Point

SR2C4(D1)
SR27Z
GL82HM170 (PCH)

| rowspan="3" | September 1, 2015

| rowspan="11" | DMI 3.0

| rowspan="11" | 3.93 GB/s

| rowspan="2" | 16 PCIe 3.0

| rowspan="2" | Up to 4

| rowspan="10" {{dunno}}

| rowspan="2" | Up to 2

| rowspan="7" {{no}}

| rowspan="2" | Up to 8

| rowspan="7" {{no|None}}

| rowspan="11" | Up to 14

| rowspan="2" | 2.6 W

QM170SR2C3(D1)
SR27Y
GL82QM170 (PCH)
CM236SR2CE(D1)GL82CM236 (PCH)

| 20 PCIe 3.0

| Up to 8

| Up to 3

| Up to 10

| 3.67 W

QMS180SR2NH(D1)GLQMS180 (PCH)??????
QMU185

|

|

|?

|?

|?

|?

|?

|?

HM175

| SR30W(D1)

| GL82HM175 (PCH)

| rowspan="3" | January 3, 2017

| rowspan="2" | 16 PCIe 3.0

| rowspan="2" | Up to 4

| rowspan="2" | Up to 2

| rowspan="2" | Up to 8

| rowspan="2" | 2.6 W

QM175

| SR30V(D1)

| GL82QM175 (PCH)

CM238

| SR30U(D1)

| GL82CM238 (PCH)

| 20 PCIe 3.0

| Up to 8

| Up to 3

| Up to 10

| 3.67 W

HM370

| rowspan="3" | Coffee Lake

| SR40B(B0)

| FH82HM370 (PCH)

| rowspan="3" | Q2 2018

| 16 PCIe 3.0

| rowspan="2" | Up to 4

| rowspan="2" | Up to 2

| rowspan="3" |WiFi 5

| Up to 8

| Up to 4

| rowspan="3" | 3 W

QM370

| SR40D(B0)

| FH82QM370 (PCH)

| 20 PCIe 3.0

| rowspan="2" | Up to 10

| rowspan="2" | Up to 6

CM246

| SR40E(B0)

| FH82CM246 (PCH)

| 24 PCIe 3.0

| Up to 8

| Up to 4

= On-package mobile chipsets =

class="wikitable" style="font-size: 90%;"
rowspan="3" | CPU On-package Chipset

! rowspan="3" | Code Name

! rowspan="3" | Release Date

! rowspan="3" | Bus Interface

! rowspan="3" | Link Speed{{Efn|name="aggrLink"}}

! rowspan="3" | PCI Express lanes

! SATA

! rowspan="3" | SATAe

! rowspan="3" | PCIe M.2

! rowspan="3" | Wireless
MAC

! colspan="3" | USB ports

! rowspan="3" | TDP

rowspan="2" | 6 Gbit/s ports

! colspan="2" | v3.2

! rowspan="2" | v2.0

Gen 1x1Gen 2x1
100 series (Base-U)

| rowspan="3" |Skylake{{Cite web |title=6th Generation Intel Core Processor Families I/O Platform |url=https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/6th-gen-core-pch-u-y-io-datasheet-vol-1.pdf}}

| rowspan="3" |September 2015

| rowspan="3" |OPI x8

| rowspan="3" |2GT/s and 4GT/s

|10 PCIe 2.0

|2

| rowspan="3" {{Unknown}}

|?

| rowspan="3" {{Unknown}}

|4

| rowspan="3" {{No|None}}

|8

| rowspan="3" {{Unknown}}

100 series (Premium-U)

|12 PCIe 3.0

|3

|?

|6

|10

100 series (Premium-Y)

|10 PCIe 3.0

|2

|?

|6

|6

Kaby Lake (Base-U)

| rowspan="3" |Kaby Lake{{Cite web |title=7th Generation Intel Processor Families I/O for U/Y Platforms: Datasheet |url=https://www.intel.com/content/www/us/en/content-details/334658/7th-generation-intel-processor-families-i-o-for-u-y-platforms-datasheet-volume-1-of-2.html?wapkw=334658}}

| rowspan="3" |September 2016

| rowspan="3" |OPI x8

| rowspan="3" |2GT/s and 4GT/s

|10 PCIe 2.0

|2

| rowspan="3" {{Unknown}}

|?

| rowspan="3" {{Unknown}}

|4

| rowspan="3" {{No|None}}

|10

| rowspan="3" {{Unknown}}

Kaby Lake (Premium-U)

|12 PCIe 3.0

|3

|?

|6

|10

Kaby Lake (Premium-Y)

|10 PCIe 3.0

|2

|?

|6

|6

300 series (Premium-U)

|Coffee Lake{{Cite web |title=Intel 300 Series Chipset Family On-Package Platform Controller Hub (PCH) Datasheet, Volume 1 of 2 |url=https://www.intel.sg/content/www/xa/en/products/docs/chipsets/300-series-chipset-on-package-pch-datasheet-vol-1.html}}

|April 2018

|OPI x8

|Up to 4GT/s

|16 PCIe 3.0

|3

| {{Unknown}}

|?

| {{Unknown}}

|Up to 6

| {{No|None}}

|10

| {{Unknown}}

400/500 Series chipsets

=LGA 1200=

{{See also | LGA 1200#Comet Lake chipsets (400 series) | label 1=Comet Lake chipsets (400 series) | LGA 1200#Rocket Lake chipsets (500 series) | label 2= Rocket Lake chipsets (500 series)}}

LGA 1200 is a CPU socket designed for Comet Lake and Rocket Lake desktop CPUs. Like its predecessors, LGA 1200 has the same number of pins its name would suggest: 1200. Under the hood, LGA 1200 is a modified version of LGA 1151, its predecessor. It features 49 additional protruding pins that are used to improve power delivery and provide support for eventual updates with I/O features.

class="wikitable" style="font-size: 90%;"
rowspan="3" | Chipset

! rowspan="3" | Code
Name

! rowspan="3" | sSpec
Number

! rowspan="3" | Part
numbers

! rowspan="3" | Release Date

! rowspan="3" | Bus
Interface

! rowspan="3" | Link
Speed

! rowspan="3" | PCI Express
lanes

! rowspan="3" | Intel Optane
Memory
support

! SATA

! rowspan="3" | SATAe

! rowspan="3" | PCIe M.2

! rowspan="3" | Wireless
MAC

! colspan="4" | USB ports

! rowspan="3" | Rocket Lake support

! rowspan="3" | TDP

rowspan="2" | 6 Gbit/s

! rowspan="2" | v2.0

! colspan="3" | v3.2

Gen 1x1Gen 2x1Gen 2x2
H410rowspan="9" | Comet LakeSRH1D(A0)FH82H410rowspan="9" | Q2 2020rowspan="14" | DMI 3.0rowspan="9" | ×4{{cite web |url=https://www.anandtech.com/show/16495/intel-rocket-lake-14nm-review-11900k-11700k-11600k/2 |title=Intel Rocket Lake (14nm) Review: Core i9-11900K, Core i7-11700K, and Core i5-11600K |author=Dr. Ian Cuttress |date=2021-03-30 |website=www.anandtech.com}}
(3.93 GB/s)
6 PCIe 3.0{{no}}4rowspan="6" {{no}}rowspan="6" {{yes}}rowspan="2" {{no}}Up to 10Up to 4{{no|None}}{{no|None}}rowspan="2" {{no}}rowspan="6" | 6 W
B460SRH1C(A0)FH82B46016 PCIe 3.0{{yes}}rowspan="4" | 6Up to 12rowspan="2" | Up to 8{{no|None}}{{no|None}}
H470SRH14(A0)FH82H47020 PCIe 3.0{{yes}}rowspan="4" | WiFi 6rowspan="4" | Up to 14Up to 4{{no|None}}rowspan="4" {{yes}}
Q470SRH1A(A0)FH82Q470rowspan="3" | 24 PCIe 3.0{{yes}}rowspan="3" | Up to 10rowspan="2" | Up to 6{{no|None}}
Z490SRH13(A0)FH82Z490{{yes}}{{no|None}}
W480SRH19(A0)FH82W480{{yes}}8Up to 8{{no|None}}
H420E

|SRH8W(A0)

|FH82H420E

|6 PCIe 3.0

| rowspan="3" {{Unknown}}

|4

| rowspan="3" {{No}}

| rowspan="3" {{Unknown}}

| rowspan="3" {{No}}

|Up to 10

|Up to 6

|None

|None

| rowspan="3" {{Unknown}}

| rowspan="3" |6 W

Q470E

|SRJ7X(A0)

|FH82Q470E

| rowspan="2" |24 PCIe 3.0

|6

| rowspan="2" |14

| rowspan="2" |Up to 10

|Up to 6

|None

W480E

|SRJ7Y(A0)

|FH82W480E

|8

|Up to 8

|None

H510rowspan="5" | Rocket LakeSRKM2(B1)FH82H510rowspan="5" | Q1 2021rowspan="2" |×4
(3.93 GB/s)

| 6 PCIe 3.0

{{no}}4rowspan="5" {{no}}rowspan="5" {{yes}}rowspan="5" | WiFi 6Up to 10Up to 4{{no|None}}{{no|None}}rowspan="5" {{yes}}rowspan="5" | 6 W
B560SRKM5(B1)FH82B56012 PCIe 3.0{{yes}}rowspan="3" | 6Up to 12Up to 6rowspan="2" | Up to 4rowspan="2" | Up to 2
H570SRKM6(B1)FH82H570

| rowspan="3" |×8
(7.86 GB/s)

| 20 PCIe 3.0

{{yes}}rowspan="3" | Up to 14Up to 8
Z590SRKM3(B1)FH82Z590

| rowspan="2" |24 PCIe 3.0

{{yes}}rowspan="2" | Up to 10rowspan="2" | Up to 10rowspan="2" | Up to 3
W580

|SRKM7(B1)

|FH82W580

{{yes}}

|8

  • Connection to the CPU will be reduced to DMI 3.0 ×4 if a Comet Lake CPU is installed. DMI 3.0 ×8 is only available with Rocket Lake CPUs.
  • Mainboards advertised as H410 and B460 with Rocket Lake support use other 400-series chipsets. (such as H470){{cite web |url=https://www.notebookcheck.net/Intel-officially-announces-that-B460-and-H410-chipsets-won-t-support-Rocket-Lake-chips-but-Gigabyte-s-H410M-motherboards-offer-a-cheeky-workaround.519339.0.html |title=Intel officially announces that B460 and H410 chipsets won't support Rocket Lake chips but Gigabyte's H410M motherboards offer a cheeky workaround |last=Deakin |first=Daniel |date=2021-02-09 |website=www.notebookcheck.net}}

= Dedicated mobile and embedded chipsets =

class="wikitable" style="font-size: 90%;"
rowspan="3" | Chipset

! rowspan="3" | Code
Name

! rowspan="3" | sSpec
Number

! rowspan="3" | Part
numbers

! rowspan="3" | Release Date

! rowspan="3" | Bus
Interface

! rowspan="3" | Link
Speed

! rowspan="3" | PCI Express
lanes

! rowspan="3" | Intel Optane
Memory
support

! SATA

! rowspan="3" | SATAe

! rowspan="3" | PCIe M.2

! rowspan="3" | Wireless
MAC

! colspan="4" | USB ports

! rowspan="3" | TDP

rowspan="2" | 6 Gbit/s

! rowspan="2" | v2.0

! colspan="3" | v3.2

Gen 1x1Gen 2x1Gen 2x2
HM470

| rowspan="3" |Comet Lake

| SRJAU(A0)

| FH82HM470

| rowspan="3" |Q2 2020

| rowspan="3" |DMI 3.0

| rowspan="3" |3.93 GB/s

| 16 PCIe 3.0

| rowspan="3" {{yes}}

| rowspan="2" |4

| rowspan="3" {{no}}

| rowspan="3" {{yes}}

| rowspan="3" |WiFi 6

| rowspan="3" |Up to 14

| Up to 8

| Up to 4

| rowspan="2" {{unknown}}

| rowspan="3" |3 W

QM480

| SRH16 {{cite web |url=https://www.mouser.com/ProductDetail/Intel/FH82QM480-S-RH16?qs=vHuUswq2%252BszZ2TzJfKbW%252BQ%3D%3D |author=Mouser Electronics |date=2022-12-28 |website=www.mouser.com}}

| FH82QM480

| 20 PCIe 3.0

| rowspan="2" |Up to 10

| rowspan="2" |Up to 6

WM490SRH17(A0)FH82WM490

| rowspan="1" | 24 PCIe 3.0

| rowspan="1" |8

| rowspan="1" {{no}}

HM570E

| rowspan="6" |Tiger Lake

|SRKLS(B1)

|FH82HM570E

| rowspan="3" |Q3 2021

| rowspan="6" |DMI 3.0

| rowspan="6" |3.93 GB/s

|16 PCIe 3.0

| rowspan="3" {{unknown}}

| rowspan="2" |4

| rowspan="6" {{no}}

| rowspan="3" {{unknown}}

| rowspan="3" {{no}}

| rowspan="4" |Up to 14

| rowspan="3" |Up to 10

| rowspan="3" |Up to 10

| rowspan="5" {{unknown}}

| rowspan="2" |2.9 W

QM580E

|SRKLT(B1)

|FH82QM580E

|20 PCIe 3.0

RM590E

|SRKLR(B1)

|FH82RM590E

|24 PCIe 3.0

|8

| rowspan="4" |3.4 W

HM570

|SRKMA(B1)

|FH82HM570

| rowspan="3" |Q2 2021

|16 PCIe 3.0

| rowspan="3" {{yes}}

| rowspan="2" |4

| rowspan="3" {{yes}}

| rowspan="3" |WiFi 6

|Up to 8

|Up to 8

QM580

|SRKMC(B1)

|FH82QM580

|20 PCIe 3.0

| rowspan="2" |Up to 14

| rowspan="2" |Up to 10

| rowspan="2" |Up to 10

WM590SRKMB(B1)FH82WM590

| 24 PCIe 3.0

| rowspan="1" | 8

| rowspan="1" {{no}}

= On-package mobile chipsets =

class="wikitable" style="font-size: 90%;"
rowspan="3" | CPU On-package Chipset

! rowspan="3" | Code Name

! rowspan="3" | Release Date

! rowspan="3" | Bus Interface

! rowspan="3" | Link Speed{{Efn|name="aggrLink"}}

! rowspan="3" | PCI Express lanes

! SATA

! rowspan="3" | SATAe

! rowspan="3" | PCIe M.2

! rowspan="3" | Wireless
MAC

! colspan="3" | USB ports

! rowspan="3" | TDP

rowspan="2" | 6 Gbit/s ports

! colspan="2" | v3.2

! rowspan="2" | v2.0

Gen 1x1Gen 2x1
400 series (Mainstream/Base-U)

| rowspan="2" |Comet Lake{{Cite web |title=Intel 400 Series Chipset Family On-Package Platform Controller Hub (PCH) |url=https://cdrdv2.intel.com/v1/dl/getContent/615170}}

| rowspan="2" |August 2019

| rowspan="2" |OPI x8

| rowspan="2" |Up to 4GT/s

|12 PCIe 2.0

|Up to 2

| rowspan="2" {{No}}

| rowspan="2" {{Yes}}

|?

|Up to 4

| {{No|None}}

|8

| rowspan="2" {{Unknown}}

400 series (Premium-U)

|16 PCIe 3.0

|Up to 3

|?

|Up to 6

|Up to 6

|10

495 series (Premium-U)

| rowspan="2" |Ice Lake{{Cite web |title=Intel 495 Series Chipset Family On-Package Platform Controller Hub (PCH) |url=https://cdrdv2.intel.com/v1/dl/getContent/341080}}

| rowspan="2" |August 2019

| rowspan="2" |OPI x8

| rowspan="2" |Up to 4GT/s

|16 PCIe 3.0

|Up to 3

| rowspan="2" {{No}}

| rowspan="2" {{Yes}}

|?

| rowspan="2" |Up to 6

| rowspan="2" |Up to 6

|10

| rowspan="2" {{Unknown}}

495 series (Premium-Y)

|14 PCIe 3.0

|Up to 2

|?

|6

500 series (Premium-UP3)

| rowspan="2" |Tiger Lake{{Cite web |title=Intel 500 Series Chipset Family On-Package Platform Controller Hub (PCH) |url=https://cdrdv2.intel.com/v1/dl/getContent/631119}}

| rowspan="2" |September 2020

| rowspan="2" |OPI x8

|Up to 4GT/s

|12 PCIe 3.0

|2

| rowspan="2" {{No}}

| rowspan="2" {{Yes}}

|?

|4

|4

|10

| rowspan="2" {{Unknown}}

500 series (Premium-UP4)

|Up to 2GT/s

|10 PCIe 3.0

| {{No|None}}

|?

|4

|4

|6

600/700 Series chipsets

=LGA 1700=

{{See also|LGA 1700#Alder Lake chipsets (600 series)|label 1=Alder Lake chipsets (600 series)|LGA 1700#Raptor Lake chipsets (700 series)|label 2=Raptor Lake chipsets (700 series)}}

class="wikitable" style="font-size: 90%;"
rowspan="3" | Chipset

! rowspan="3" | Code
Name

! rowspan="3" | sSpec
Number

! rowspan="3" | Part
numbers

! rowspan="3" | Release Date

! rowspan="3" | Bus
Interface

! rowspan="3" | Link
Speed

! rowspan="2" colspan="2" | PCI Express
lanes

! rowspan="3" | Optane
Memory
support

! SATA

! rowspan="3" | SATAe

! rowspan="3" | PCIe

M.2

! rowspan="3" | Wireless
MAC

! colspan="4" | USB ports

! rowspan="3" | TDP

rowspan="2" | 6 Gbit/s

! rowspan="2" | v2.0

! colspan="3" | v3.2

4.03.0Gen 1x1Gen 2x1Gen 2x2
Z690

| rowspan="9" | Alder Lake

| SRKZZ(B1)

| FH82Z690

| Q4 2021

| rowspan="9" | DMI 4.0

| rowspan="4" | ✕8{{cite web |url=https://www.anandtech.com/show/16959/intel-innovation-alder-lake-november-4th |title=Intel 12th Gen Core Alder Lake for Desktops: Top SKUs Only, Coming November 4th |author=Dr. Ian Cuttress |date=2021-10-27 |website=www.anandtech.com}}
(15.76 GB/s)

| rowspan="4" | 12{{cite web |url=https://www.youtube.com/watch?v=ydgN4W97Esk?t=200 |title=Intel Core i7-12700 vs. AMD Ryzen 7 5800X, Best Value CPU? |author=Steven Walton |date=2022-01-05 |website=www.youtube.com}}

| rowspan="2" | 16

| rowspan="5" {{Yes}}

| rowspan="4" | 8

| rowspan="6"{{No}}

| rowspan="6" {{Yes}}

| rowspan="6" |WiFi 6E

| rowspan="4" | 14

| rowspan="3" | 10

| rowspan="2" | 10

| rowspan="3" | 4

| rowspan="12" | 6 W

W680

| SRL00(B1)

| FH82W680

| Q2 2022

Q670

| SRL01(B1)

| FH82Q670

| rowspan="7" | Q1 2022

| rowspan="2" | 12

| 8

H670

| SRKZY(B1)

| FH82H670

| 8

| rowspan="2" | 4

| rowspan="2" | 2

B660

| SRKZX(B1)

| FH82B660

| rowspan="2" | ✕4
(7.88 GB/s)

| 6

| rowspan="2" | 8

| rowspan="2" | 4

| 12

| 6

H610

| SRKZW(B1)

| FH82H610

| {{No|None}}

| {{No}}

| 10

| 4

| 2

| {{No|None}}

R680E

|SRL2S(B1)

|FH82R680E

| rowspan="2" |✕8
(15.76 GB/s)

| rowspan="2" |12

|16

| rowspan="3" {{No}}

| rowspan="2" | 8

| rowspan="3" {{No}}

| rowspan="3" {{Unknown}}

| rowspan="2" |WiFi 5

| rowspan="2" |14

| rowspan="2" |10

|10

| rowspan="2" |4

Q670E

|SRL2R(B1)

|FH82Q670E

|12

|8

H610E

|SRL2T(B1)

|FH82H610E

|✕4
(7.88 GB/s)

| {{No|None}}

|12

|4

|WiFi 6E

|10

|4

|2

| {{No|None}}

Z790

| rowspan="3" | Raptor Lake

| SRM8P(B1)

| FH82Z790

| Q4 2022

| rowspan="3" | DMI 4.0

| rowspan="2" | ✕8
(15.76 GB/s)

| 20

| rowspan="2" | 8

| rowspan="3" {{Yes}}

| rowspan="2" | 8

| rowspan="3" {{No}}

| rowspan="3" {{Yes}}

| rowspan="3" |WiFi 6E

| rowspan="2" | 14

| colspan="2" | 10

| 5

H770

| SRM8T(B1)

| FH82H770

| rowspan="2" |Q1 2023

|16

|8

| rowspan="2" |4

| rowspan="2" |2

B760

| SRM8V(B1)

| FH82B760

|✕4
(7.88 GB/s)

|10

|4

|4

|12

|6

= Dedicated mobile chipsets =

Every 12th Gen and 13th Gen Intel Core-i mobile CPU excluding HX-series has an on-package Platform Controller Hub.

class="wikitable" style="font-size: 90%;"
rowspan="3" | Chipset

! rowspan="3" | Code
Name

! rowspan="3" | sSpec
Number

! rowspan="3" | Part
numbers

! rowspan="3" | Release Date

! rowspan="3" | Bus
Interface

! rowspan="3" | Link
Speed

! colspan="2" | PCI Express lanes

! rowspan="3" | Optane
Memory
support

! SATA

! rowspan="3" | SATAe

! rowspan="3" | PCIe M.2

! rowspan="3" | Wireless
MAC

! colspan="4" | USB ports

! rowspan="3" | TDP

rowspan="2" | 4.0

! rowspan="2" | 3.0

! rowspan="2" | 6 Gbit/s

! rowspan="2" | v2.0

! colspan="3" | v3.2

Gen 1x1Gen 2x1Gen 2x2
HM670

| rowspan="2" |Alder Lake

| SRL2Y(B1)

| FH82HM670

| rowspan="2" |Q2 2022

| rowspan="4" |DMI 4.0

| rowspan="4" |✕8
(15.76 GB/s)

| rowspan="2" |Up to 16

| rowspan="2" |Up to 12

| rowspan="2" {{yes}}

| rowspan="4" |8

| rowspan="2" {{no}}

| rowspan="2" {{yes}}

| rowspan="4" |WiFi 6E

| rowspan="4" |Up to 14

| colspan="2" rowspan="4" |Up to 10

| rowspan="4" |Up to 4

| rowspan="4" |3.7 W

WM690

| SRL2Z(B1)

| FH82WM690

HM770

| rowspan="2" |Raptor Lake

|SRM8M(B1)

|FH82HM770

| rowspan="2" |January 3, 2023

| colspan="2" rowspan="2" |28 including PCIe 3.0

| rowspan="2" {{unknown}}

| rowspan="2" {{no}}

| rowspan="2" {{yes}}

WM790

|SRM8N(B1)

|FH82WM790

= On-package mobile chipsets =

class="wikitable" style="font-size: 90%;"
rowspan="3" | CPU On-package Chipset

! rowspan="3" | Code Name

! rowspan="3" | Release Date

! rowspan="3" | Bus Interface

! rowspan="3" | Link
Speed

! colspan="2" | PCI Express lanes

! SATA

! rowspan="3" | SATAe

! rowspan="3" | PCIe M.2

! rowspan="3" | Wireless
MAC

! colspan="3" | USB ports

! rowspan="3" | TDP

rowspan="2" |4.0

! rowspan="2" |3.0

! rowspan="2" | 6 Gbit/s ports

! colspan="2" | v3.2

! rowspan="2" | v2.0

Gen 1x1Gen 2x1
600 series (Premium-P){{Cite web |title=Intel 600 Series Chipset Family On-Package Platform Controller Hub Datasheet, Volume 1 of 2 |url=https://cdrdv2.intel.com/v1/dl/getContent/691222/view?wapkw=Intel%C2%AE%20600%20Series%20Chipset%20Family%20On-Package%20Platform%20Controller%20Hub%20(PCH)}}

|Alder Lake

|February 2022

| rowspan="2" |OPI

| rowspan="2" |✕8

(15.76 GB/s)

| {{No|None}}

| rowspan="2" |12

| rowspan="2" |Up to 2

| {{No}}

| {{Yes}}

| rowspan="2" |WiFi 6

| rowspan="2" |Up to 4

| rowspan="2" |Up to 4

| rowspan="2" |10

| {{Unknown}}

700 series (Premium-P){{Cite web |title=Intel 700 Series Chipset Family On-Package Platform Controller Hub (PCH) Datasheet, Volume 1 of 2 |url=https://cdrdv2.intel.com/v1/dl/getContent/763122/view?wapkw=Intel%C2%AE%20700%20Series%20Chipset%20Family%20On-Package%20Platform%20Controller%20Hub%20(PCH)}}

|Raptor Lake

|January 2023

| {{No|None}}

| {{No}}

| {{Yes}}

| {{Unknown}}

800 Series chipsets

=LGA 1851=

{{See also|LGA 1851#Arrow Lake chipsets (800 series)|label 1=Arrow Lake chipsets (800 series)}}

class="wikitable" style="font-size: 90%;"
rowspan="3" | Chipset

! rowspan="3" | Code
Name

! rowspan="3" | sSpec
Number

! rowspan="3" | Part
numbers

! rowspan="3" | Release Date

! rowspan="3" | Bus
Interface

! rowspan="3" | Link
Speed

! rowspan="2" colspan="2" | PCI Express
lanes

! rowspan="3" | Optane
Memory
support

! SATA

! rowspan="3" | PCIe

M.2

! rowspan="3" | Wireless
MAC

! colspan="4" | USB ports

! rowspan="3" | TDP

rowspan="2" | 6 Gbit/s

! rowspan="2" | v2.0

! colspan="3" | v3.2

4.03.0Gen 1x1Gen 2x1Gen 2x2
Z890

| rowspan="3" | Arrow Lake

| SRPEZ(B0)

| FH82Z890

| Q4 2024

| rowspan="3" | DMI 4.0

| ✕8
(15.76 GB/s)

| 24

| rowspan="3" {{N/A}}

| rowspan="3" {{No}}

| 8

| rowspan="3" {{Yes}}

| rowspan="3" | WiFi 6E

| 14

| 10

| 10

| 5

| rowspan="3" | 6 W

B860

| SRPEW(B0)

| FH82B860

| rowspan="2" | Q1 2025

| rowspan="2" | ✕4
(7.88 GB/s)

| 14

| rowspan="3" | 4

| 12

| 6

| 4

| 2

H810

| SRPEV(B0)

| FH82H810

| 8

| 10

| 4

| 2

| {{No|None}}

See also

Notes

{{Notelist}}

References

{{reflist}}