Tiger Lake

{{Further|Willow Cove}}

• Intel Willow Cove CPU cores{{cite web|last=Cutress|first=Dr Ian|title=Intel's 11th Gen Core Tiger Lake SoC Detailed: SuperFin, Willow Cove and Xe-LP|url=https://www.anandtech.com/show/15971/intels-11th-gen-core-tiger-lake-soc-detailed-superfin-willow-cove-and-xelp|access-date=2021-04-06|website=www.anandtech.com|archive-date=2021-05-18|archive-url=https://web.archive.org/web/20210518152431/https://www.anandtech.com/show/15971/intels-11th-gen-core-tiger-lake-soc-detailed-superfin-willow-cove-and-xelp|url-status=live}}
• TAGE-like directional branch predictor (with a global history size of 194 taken branches){{Cite conference |last1=Yavarzadeh |first1=Hosein |last2=Taram |first2=Mohammadkazem |last3=Narayan |first3=Shravan |last4=Stefan |first4=Deian |last5=Tullsen |first5=Dean |conference=2023 IEEE Symposium on Security and Privacy (SP) |title=Half&Half: Demystifying Intel's Directional Branch Predictors for Fast, Secure Partitioned Execution |date=May 2023 |url=https://ieeexplore.ieee.org/document/10179415 |publisher=IEEE |pages=1220–1237 |doi=10.1109/SP46215.2023.10179415 |isbn=978-1-6654-9336-9|s2cid=259255212 }}
• Indirect branch tracking and CET shadow stack{{r|zdnet}}
• Intel Key Locker{{cite web |url=https://software.intel.com/content/dam/develop/external/us/en/documents/343965-intel-key-locker-specification.pdf |title=Intel Key Locker |date=September 2020 |publisher=Intel |archive-url=https://web.archive.org/web/20200918175404/https://software.intel.com/content/dam/develop/external/us/en/documents/343965-intel-key-locker-specification.pdf |archive-date=2020-09-18 |url-status=live}}{{cite web|url=https://www.phoronix.com/scan.php?page=news_item&px=Intel-Key-Locker-LLVM|title=Intel Key Locker Support Added to LLVM - Confirms Presence with Tiger Lake - Phoronix|access-date=2020-10-03|archive-date=2020-10-03|archive-url=https://web.archive.org/web/20201003112533/https://www.phoronix.com/scan.php?page=news_item&px=Intel-Key-Locker-LLVM|url-status=live}}

• Intel Xe-LP ("Gen12") GPU with up to 96 execution units{{cite web|url=https://www.anandtech.com/show/15973/the-intel-xelp-gpu-architecture-deep-dive-building-up-from-the-bottom|title=The Intel Xe-LP GPU Architecture Deep Dive: Building up the Next Generation|access-date=2020-08-28|archive-date=2020-08-16|archive-url=https://web.archive.org/web/20200816002207/https://www.anandtech.com/show/15973/the-intel-xelp-gpu-architecture-deep-dive-building-up-from-the-bottom|url-status=live}}{{cite web|url=https://software.intel.com/content/www/us/en/develop/documentation/graphics-xe-lp-api-developer-optimization-guide/top.html|title=Intel® Processor Graphics Xᵉ-LP API Developer and Optimization Guide|access-date=2021-04-23|archive-date=2021-04-26|archive-url=https://web.archive.org/web/20210426223413/https://software.intel.com/content/www/us/en/develop/documentation/graphics-xe-lp-api-developer-optimization-guide/top.html|url-status=live}} (50% uplift compared to Ice Lake, up from 64) with some yet to be announced processors using Intel's discrete GPU, DG1{{Cite web |url=https://www.pcmag.com/news/372882/intels-tiger-lake-laptop-cpu-brings-thunderbolt-4-ai-graph |title=Intel's Tiger Lake Laptop CPU Brings Thunderbolt 4, AI Graphics Processing |access-date=2020-01-07 |archive-date=2020-01-07 |archive-url=https://web.archive.org/web/20200107131709/https://www.pcmag.com/news/372882/intels-tiger-lake-laptop-cpu-brings-thunderbolt-4-ai-graph |url-status=live }}{{cite web|last=Cutress|first=Dr Ian|title=Intel Launches 11th Gen Core Tiger Lake: Up to 4.8 GHz at 50 W, 2x GPU with Xe, New Branding|url=https://www.anandtech.com/show/16063/intel-launches-11th-gen-core-tiger-lake-processors-and-evo-branding|access-date=2020-09-02|website=www.anandtech.com|archive-date=2020-09-02|archive-url=https://web.archive.org/web/20200902170015/https://www.anandtech.com/show/16063/intel-launches-11th-gen-core-tiger-lake-processors-and-evo-branding|url-status=live}}
• Support for FP64 was removed{{cite web | url=https://www.intel.com/content/www/us/en/developer/articles/guide/lp-api-developer-optimization-guide.html#inpage-nav-3-8-undefined | title=Intel® Processor Graphics Xᵉ-LP API Developer and Optimization Guide }}
• Fixed-function hardware decoding for HEVC 12-bit, 4:2:2/4:4:4; VP9 12-bit 4:4:4 and AV1 8K 10-bit 4:2:0{{cite web|url = https://github.com/intel/media-driver/blob/master/README.md#decodingencoding-features|title = Media-driver/README.md at master · intel/Media-driver|website = GitHub|access-date = 2020-02-20|archive-date = 2020-01-18|archive-url = https://web.archive.org/web/20200118020501/https://github.com/intel/media-driver/blob/master/README.md#decodingencoding-features|url-status = live}}{{cite web|title=[Decode] This enables HW AV1 decode acceleration on Gen12 · intel/media-driver@9491998|url=https://github.com/intel/media-driver/commit/9491998f40d496fc458d282f213c0e9e945b8062|access-date=2020-07-29|website=GitHub|language=en|archive-date=2020-07-13|archive-url=https://web.archive.org/web/20200713101210/https://github.com/intel/media-driver/commit/9491998f40d496fc458d282f213c0e9e945b8062|url-status=live}}{{cite web|url=https://github.com/intel/media-driver/releases/tag/intel-media-20.3.0|title=Release Intel Media Driver Q3'2020 Release · intel/Media-driver|website=GitHub|access-date=2020-10-05|archive-date=2020-12-04|archive-url=https://web.archive.org/web/20201204235545/https://github.com/intel/media-driver/releases/tag/intel-media-20.3.0|url-status=live}}
• Support for a single 8K 12-bit HDR display or two 4K 10-bit HDR displays
• Hardware accelerated Dolby Vision
• Sampler Feedback{{cite web|title=Download Intel® Graphics - Windows® 10 DCH Drivers|url=https://downloadcenter.intel.com/download/29904/Intel-Graphics-Windows-10-DCH-Drivers|access-date=2020-09-30|website=Drivers & Software|language=en|archive-date=2020-10-05|archive-url=https://web.archive.org/web/20201005120630/https://downloadcenter.intel.com/download/29904/Intel-Graphics-Windows-10-DCH-Drivers|url-status=live}}{{cite web|title=Sampler Feedback|url=https://microsoft.github.io/DirectX-Specs/d3d/SamplerFeedback.html|access-date=2020-09-30|website=DirectX-Specs|language=en-US|archive-date=2020-10-05|archive-url=https://web.archive.org/web/20201005013357/https://microsoft.github.io/DirectX-Specs/d3d/SamplerFeedback.html|url-status=live}}{{cite web|date=2019-11-04|title=Coming to DirectX 12— Sampler Feedback: some useful once-hidden data, unlocked|url=https://devblogs.microsoft.com/directx/coming-to-directx-12-sampler-feedback-some-useful-once-hidden-data-unlocked/|access-date=2020-09-30|website=DirectX Developer Blog|language=en-US|archive-date=2020-10-23|archive-url=https://web.archive.org/web/20201023062007/https://devblogs.microsoft.com/directx/coming-to-directx-12-sampler-feedback-some-useful-once-hidden-data-unlocked/|url-status=live}}{{cite web|url=https://software.intel.com/content/www/us/en/develop/documentation/graphics-xe-lp-api-developer-optimization-guide/top/intel-x-lp-architecture-highlights/directx12-sampler-feedback.html|title=DirectX12 Sampler Feedback|access-date=2021-04-23|archive-date=2021-08-04|archive-url=https://web.archive.org/web/20210804202449/https://software.intel.com/content/www/us/en/develop/documentation/graphics-xe-lp-api-developer-optimization-guide/top/intel-x-lp-architecture-highlights/directx12-sampler-feedback.html|url-status=live}} support
• Dual Queue Support{{cite web|url=https://software.intel.com/content/www/us/en/develop/documentation/graphics-xe-lp-api-developer-optimization-guide/top/intel-x-lp-architecture-highlights/dual-queue-support.html|title=Dual Queue Support|access-date=2021-04-23|archive-date=2021-08-04|archive-url=https://web.archive.org/web/20210804202441/https://software.intel.com/content/www/us/en/develop/documentation/graphics-xe-lp-api-developer-optimization-guide/top/intel-x-lp-architecture-highlights/dual-queue-support.html|url-status=live}}

• Image Processing Unit, a special co-processor to improve image and video capture quality
• Not available on embedded models
• Initially there were [https://ark.intel.com/content/www/us/en/ark/products/208662/intel-core-i7-1165g7-processor-12m-cache-up-to-4-70-ghz.html i7-1165G7], [https://ark.intel.com/content/www/us/en/ark/products/208658/intel-core-i5-1135g7-processor-8m-cache-up-to-4-20-ghz.html i5-1135G7], [https://ark.intel.com/content/www/us/en/ark/products/208656/intel-core-i3-1125g4-processor-8m-cache-up-to-3-70-ghz.html i3-1125G4] and [https://ark.intel.com/content/www/us/en/ark/products/208652/intel-core-i3-1115g4-processor-6m-cache-up-to-4-10-ghz.html i3-1115G4] models with no IPU but later embedded processors were introduced instead

• PCI Express 4.0{{Cite web |url=https://www.techpowerup.com/258196/intel-tiger-lake-supports-pcie-gen-4-and-features-xe-graphics-phantom-canyon-nuc-detailed |title=Intel "Tiger Lake" Supports PCIe Gen 4 and Features Xe Graphics, Phantom Canyon NUC Detailed |access-date=2020-01-07 |archive-date=2020-08-09 |archive-url=https://web.archive.org/web/20200809084728/https://www.techpowerup.com/258196/intel-tiger-lake-supports-pcie-gen-4-and-features-xe-graphics-phantom-canyon-nuc-detailed |url-status=live }} (Pentium and Celeron CPUs are limited to PCI Express 3.0)
• Integrated Thunderbolt 4 (includes USB4)
• LPDDR4X-4267 memory support, except on desktop processors
• LPDDR5-5400 "architecture capability" (Intel expected Tiger Lake products with LPDDR5 RAM to be available around Q1 2021 but no companies ever released them){{cite web|url=https://www.tomshardware.com/news/intels-tiger-lake-roars-to-life-willow-cove-cores-xe-graphics-support-for-lpddr5|title=Intel's Tiger Lake Roars to Life: Willow Cove Cores, Xe Graphics, Support for LPDDR5|date=13 August 2020|publisher=Tom's Hardware|access-date=2020-12-03|archive-date=2022-09-04|archive-url=https://web.archive.org/web/20220904015823/https://www.tomshardware.com/news/intels-tiger-lake-roars-to-life-willow-cove-cores-xe-graphics-support-for-lpddr5|url-status=live}}{{cite web|url=https://newsroom.intel.com/wp-content/uploads/sites/11/2020/08/intel-2020-architecture-day-fact-sheet.pdf|publisher=Intel|title=Intel News Factsheet: Intel Unpacks Architectural Innovations and Reveals New Transistor Technology at Architecture Day 2020|access-date=2020-12-03|archive-date=2020-09-21|archive-url=https://web.archive.org/web/20200921191922/https://newsroom.intel.com/wp-content/uploads/sites/11/2020/08/intel-2020-architecture-day-fact-sheet.pdf|url-status=live}}
• Miniaturization of CPU and motherboard into an M.2 SSD-sized small circuit board

• Add Intel Platform Monitoring Technology{{cite web|title=Tiger Lake - Microarchitectures - Intel - WikiChip|url=https://en.wikichip.org/wiki/intel/microarchitectures/tiger_lake|access-date=2021-02-08|website=en.wikichip.org|language=en|archive-date=2021-01-20|archive-url=https://web.archive.org/web/20210120102139/https://en.wikichip.org/wiki/intel/microarchitectures/tiger_lake|url-status=live}}

• All models support DDR4-3200 memory
• All models support 20 reconfigurable PCI Express 4.0 lanes, allowing x16 Gen 4 link for discrete GPU and x4 Gen 4 link for M.2 SSDs

{{Row hover highlight}}

• All models support DDR4-3200 or LPDDR4X-4267 memory

• TDP: 7-15W
• Memory support: LPDDR4X-4267

• Socket: FCBGA1787, a BGA socket, thus [https://ark.intel.com/content/www/us/en/ark/compare.html?productIds=215570,128915,128916,215569 these CPUs] are meant only for system integrators
• Intel Xe UHD Graphics
• Up to 128 GB DDR4-3200 memory

• Process–architecture–optimization model
• List of Intel CPU microarchitectures

{{Reflist|refs=

{{cite web

|title = Intel brings novel CET technology to Tiger Lake mobile CPUs

|author = Catalin Cimpanu

|publisher = ZDNet

|url = https://www.zdnet.com/article/intel-brings-novel-cet-technology-to-tiger-lake-mobile-cpus/

|date = 15 June 2020

|access-date = 23 July 2020

|archive-date = 15 June 2020

|archive-url = https://web.archive.org/web/20200615205831/https://www.zdnet.com/article/intel-brings-novel-cet-technology-to-tiger-lake-mobile-cpus/

|url-status = live

}}

}}

{{Intel processors|Cannonlake}}

{{Intel processor roadmap}}

Category:Intel products

Category:Intel microarchitectures

Category:Transactional memory

Category:X86 microarchitectures