List of Intel CPU microarchitectures
{{Short description|None}}
{{Incomplete list|date=December 2020}}
The following is a partial list of Intel CPU microarchitectures. The list is incomplete, additional details can be found in Intel's tick–tock model, process–architecture–optimization model and Template:Intel processor roadmap.
x86 microarchitectures
{{mw-datatable}}
| class="wikitable floatright sortable mw-datatable"
|+x86 microarchitectures ! Year ! Microarchitecture ! style="width:9.5em" | Pipeline stages ! Max ! Process node |
| 1978
| {{0}}2 | {{0}}{{0}}{{0}}5 | rowspan="2" | 3000 nm |
| 1982
| {{0}}2 | {{0}}{{0}}25 |
| 1982
| 286 (80286) | {{0}}3 | {{0}}{{0}}25 | rowspan="2" | 1500 nm |
| 1985
| 386 (80386) | {{0}}{{0}}33 |
| 1989
| 486 (80486) | {{0}}5 | {{0}}100 | 1000 nm |
| 1993
| P5 (Pentium) | {{0}}5 | {{0}}200 |
| 1995
| P6 (Pentium Pro, Pentium II) | 14 (17 with load & store/ | {{0}}450 |
| 1997
| P5 (Pentium MMX) | {{0}}6 | {{0}}233 | 350 nm |
| 1999
| P6 (Pentium III) | 12 (15 with load & store/retire) | 1400 |
| 2000
| NetBurst (Pentium 4) | rowspan="2" | 20 unified with branch prediction | 2000 | 180 nm |
| 2002
| NetBurst (Pentium 4) | 3466 | 130 nm |
| 2003
| Pentium M (Banias, Dothan) | 10 (12 with fetch/ | 2333 |
| 2004
| NetBurst (Pentium 4, Pentium D) | 31 unified with branch prediction | 3800 | 90, 65 nm |
| 2006
| rowspan="2" | 12 (14 with fetch/retire) | 3000 | 65 nm |
| 2007
| Penryn (die shrink) | 3333 | rowspan="3" | 45 nm |
| rowspan="2" | 2008
| Nehalem | 20 unified (14 without miss prediction) | 3600 |
| Bonnell
| 16 (20 with prediction miss) | 2100 |
| 2010
| Westmere (die shrink) | 20 unified (14 without miss prediction) | 3866 | rowspan="3" | 32 nm |
| rowspan="2" | 2011
| Saltwell (die shrink) | 16 (20 with prediction miss) | 2130 |
| Sandy Bridge
| rowspan="2" | 14 (16 with fetch/retire) | 4000 |
| 2012
| Ivy Bridge (die shrink) | 4100 | rowspan="3" | 22 nm |
| rowspan="2" | 2013
| 14–17 (16–19 with fetch/retire) | 2670 |
| Haswell
| rowspan="2" | 14 (16 with fetch/retire) | 4400 |
| 2014
| Broadwell (die shrink) | 3700 | rowspan="5" | 14 nm |
| rowspan="2" | 2015
| Airmont (die shrink) | 14–17 (16–19 with fetch/retire) | 2640 |
| Skylake
| 14 (16 with fetch/retire) | 5300 |
| 2016
| Goldmont | 20 unified with branch prediction | 2600 |
| 2017
| 20 unified with branch prediction (?) | 2800 |
| 2018
| 14 (16 with fetch/retire) | 3200 | rowspan="4" | 10 nm |
| 2019
| 12–19 (misprediction) | 4100 |
| rowspan="2" | 2020
| Tremont | 20 unified | 3300 |
| Willow Cove
| 12 unified | 5300 |
| rowspan="3" | 2021
| 12 unified | 5300 | 14 nm |
| Golden Cove
| 12 unified | 5500 | rowspan="3" | Intel 7 |
| Gracemont
| 20 unified with misprediction penalty | 4300 |
| 2022
| 12 unified | 6200 |
| rowspan="2" |2023
| 10 unified | | Intel 4, Intel 3 |
| Crestmont
| | | Intel 4, TSMC N6, Intel 3 |
| rowspan="2" |2024
| 10 unified | | rowspan="2" |TSMC N3B |
| Skymont
| 16 unified | |
| colspan="5" |Note: Atom/Power efficient microarchitectures are in Italic |
|---|
= [[16-bit computing|16-bit]] =
; 8086: first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80. The 8088 version, with an 8-bit bus, was used in the original IBM Personal Computer.
; 186: included a DMA controller, interrupt controller, timers, and chip select logic. A small number of additional instructions. The 80188 was a version with an 8-bit bus.
; 286: first x86 processor with protected mode including segmentation based virtual memory management. Performance improved by a factor of 3 to 4 over 8086. Included instructions relating to protected mode. The 80286 had a 24-bit address bus.
= [[32-bit computing|32-bit]] ([[IA-32]]) =
; i386: first 32-bit x86 processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since. Many additional powerful and valuable new instructions.
; i486: Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions.
; P5: original Pentium microprocessors, first x86 processor with super-scalar architecture and branch prediction.
; P6: used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. First x86 processor to support SIMD instruction with XMM register implemented, RISC μop decode scheme, integrated register renaming and out-of-order execution. Some important new instructions, including conditional moves, which allow the avoidance of costly branch instructions. Added 36-bit physical memory addressing, "Physical Address Extension (PAE)".
:* Pentium M: updated version of Pentium III's P6 microarchitecture designed from the ground up for mobile computing and first x86 to support micro-op fusion and smart cache.
:* Enhanced Pentium M: updated, dual core version of the Pentium M microarchitecture used in the first Intel Core microprocessors, first x86 to have shadow register architecture and speed step technology.
; NetBurst:commonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Used in Pentium 4, Pentium D, and some Xeon microprocessors. Very long pipeline. The Prescott was a major architectural revision. Later revisions were the first to feature Intel's x86-64 architecture, enhanced branch prediction and trace cache, and eventually support was added for the NX (No eXecute) bit to implement executable-space protection.
= [[64-bit computing|64-bit]] ([[x86-64]]) =
; Core: reengineered P6-based microarchitecture used in Intel Core 2 and Xeon microprocessors, built on a 65 nm process, supporting x86-64 level SSE instruction and macro-op fusion and enhanced micro-op fusion with a wider front end and decoder, larger out-of-order core and renamed register, support loop stream detector and large shadow register file.
:* Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higher FSB and clock speeds, SSE4.1 instructions, support for XOP and F/SAVE and F/STORE instructions, enhanced register alias table and larger integer register file.
; Nehalem: released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die. Added important powerful new instructions, SSE4.2.
:* Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.
; Sandy Bridge:32 nm microarchitecture, released January 9, 2011. Formerly called Gesher but renamed in 2007.{{cite web | url=http://blogs.intel.com/technology/2010/05/an_update_on_our_graphics-rela.php | title=An Update On Our Graphics-related Programs | date=May 25, 2010}} First x86 to introduce 256 bit AVX instruction set and implementation of YMM registers.
:* Ivy Bridge: successor to Sandy Bridge, using 22 nm process, released in April 2012.
; Haswell: 22 nm microarchitecture, released June 3, 2013. Added a number of new instructions, including AVX2 and FMA.
:* Broadwell: 14 nm derivative of the Haswell microarchitecture, released in September 2014. Three-cycle FMUL latency, 64 entry scheduler. Formerly called Rockwell.
; Skylake:14 nm microarchitecture, released August 5, 2015.
:* Kaby Lake: successor to Skylake, released in August 2016, broke Intel's tick-tock schedule due to delays with the 10 nm process.
:** Amber Lake: ultra low power, mobile-only successor to Kaby Lake, using 14+ nm process, released in August 2018 (no architecture changes){{Cite news|url=https://www.anandtech.com/show/13301/spectre-and-meltdown-in-hardware-intel-clarifies-whiskey-lake-and-amber-lake|title=Spectre and Meltdown in Hardware: Intel Clarifies Whiskey Lake and Amber Lake|last=Cutress|first=Ian|website=AnandTech|access-date=2018-09-02}}
:** Whiskey Lake: mobile-only successor to Kaby Lake Refresh, using 14++ nm process, released in August 2018 (has hardware mitigations for some vulnerabilities)
:* Skylake-X: high-end desktop, workstation and server microarchitecture, released on June 19, 2017 (HEDT), July 11, 2017 (SP) and August 29, 2017 (W). Introduces support for AVX-512 instruction set.
:* Coffee Lake: successor to Kaby Lake, using 14++ nm process, released in October 2017
:* Cascade Lake: server and high-end desktop successor to Kaby Lake-X and Skylake-X, using 14++ nm process, released in April 2019
:* Comet Lake: successor to Coffee Lake, using 14++ nm process, released in August 2019{{cite web|url=https://newsroom.intel.com/news/intel-expands-10th-gen-intel-core-mobile-processor-family-offering-double-digit-performance-gains/|title=Intel Expands 10th Gen Intel Core Mobile Processor Family, Offering Double Digit Performance Gains|website=Intel Newsroom|language=en-US|access-date=2019-08-21}}
:* Cooper Lake: server-only, optimized for AI oriented workloads using bfloat16, with limited availability only to Intel priority partners, using 14++ nm process, released in 2020{{cite web|url=https://www.anandtech.com/show/15631/intels-cooper-lake-plans-the-chip-that-wasnt-meant-to-exist-dies-for-you|title=Intel's Cooper Lake Plans: The Chip That Wasn't Meant to Exist, Fades Away|last=Cutress|first=Ian|website=AnandTech|access-date=2020-03-18}}{{cite web|url=https://www.servethehome.com/intel-cooper-lake-rationalized-still-launching-1h-2020/|title=Intel Cooper Lake Rationalized Still Launching 1H 2020|last=Kennedy|first=Patrick|date=2020-03-16|website=ServeTheHome|language=en-US|access-date=2020-03-18}}
; Palm Cove: Originally meant to be successor to Skylake, but cancelled after releasing just one chip. Includes the AVX-512 instruction set.{{cite web|last=Cutress|first=Ian|title=Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review|url=https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-and-core-i3-8121u-deep-dive-review|access-date=2021-04-06|website=www.anandtech.com}}{{cite web|url=https://en.wikichip.org/wiki/intel/microarchitectures/palm_cove|title=Palm Cove - Microarchitectures - Intel - WikiChip|website=en.wikichip.org|language=en|access-date=2020-01-05}}
:* Cannon Lake: mobile-only successor of Kaby Lake, using Intel's 10 nm process, first and only microarchitecture to implement the Palm Cove core, released in May 2018. Formerly called Skymont, discontinued in December 2019.{{cite web|url=https://www.tomshardware.com/news/intel-fires-10nm-cannon-lake-nuc-into-oblivion|title=Intel Fires 10nm Cannon Lake NUC Into Oblivion|first=Zhiye|last=Liu|date=October 31, 2019|website=Tom's Hardware}}
:Starting with Cannon Lake, Intel has changed their microarchitecture naming scheme, decoupling core codenames from CPU codenames.{{cite web|url=https://fuse.wikichip.org/news/1941/intel-reveals-10nm-sunny-cove-core-a-new-core-roadmap-and-teases-ice-lake-chips/|title=Intel Reveals 10nm Sunny Cove Core, a New Core Roadmap, and Teases Ice Lake Chips|first=David|last=Schor|date=December 23, 2018|website=WikiChip Fuse}}
; Sunny Cove:Successor to the Palm Cove core, first non-Atom core to include hardware acceleration for SHA hashing algorithms.{{cite web|url=https://en.wikichip.org/wiki/intel/microarchitectures/sunny_cove|title=Sunny Cove - Microarchitectures - Intel|website=WikiChip Chips & Semi}}
:* Ice Lake: low power, mobile-only successor to Whiskey Lake, using 10 nm process, released in September 2019
:* Lakefield: mobile-only, Intel's first hybrid processor, released in June 2020. Sunny Cove is used in the singular performance core (P-core) of Lakefield processors.{{cite web|title=The Intel Lakefield Deep Dive: Everything To Know About the First x86 Hybrid CPU|url=https://www.anandtech.com/show/15877/intel-hybrid-cpu-lakefield-all-you-need-to-know|first=Ian|last=Cutress|date=July 2, 2020|website=AnandTech}} AVX and more advanced instruction sets are disabled due to the E-core not supporting them.
:* Ice Lake-SP: server-only successor to Cascade Lake, using 10 nm process, released in April 2021{{cite web|url=https://newsroom.intel.com/news/new-intel-processors-accelerate-5g-network-transformation/ |title=New Intel Processors Accelerate 5G Network Transformation |publisher=Newsroom.intel.com |date=2021-04-06 |accessdate=2022-05-08}}
; Cypress Cove: Backport of Sunny Cove to Intel's 14 nm process
:* Rocket Lake: Successor to Comet Lake, using Intel's 14++ nm process, released on March 30, 2021{{cite web|url=https://www.anandtech.com/show/16495/intel-rocket-lake-14nm-review-11900k-11700k-11600k|title=Intel octet Lake (14nm) Review: Core i911900K, Core i7-11700K, and Core i5-11600K|first=Ian|last=Cutress|date=March 30, 2021|website=AnandTech}}{{cite web|url=https://www.anandtech.com/show/16145/intel-confirms-rocket-lake-on-desktop-for-q1-2021-with-pcie-40|title=Intel Confirms Rocket Lake on Desktop for Q1 2021, with PCIe 4.0|website=AnandTech|access-date=2020-10-07}}{{cite web|url=https://www.anandtech.com/show/16205/intels-11th-gen-core-rocket-lake-detailed-ice-lake-core-with-xe-graphics|title=Intel's 11th Gen Core Rocket Lake Detailed: Ice Lake Core with Xe Graphics|first=Ian|last=Cutress|date=October 29, 2020|website=AnandTech}}
; Willow Cove:Successor to the Sunny Cove core, includes new security features and redesigns the cache subsystem.{{cite web|url=https://en.wikichip.org/wiki/intel/microarchitectures/willow_cove|title=Willow Cove - Microarchitectures - Intel|website=WikiChip Chips & Semi}}
:* Tiger Lake: successor to Ice Lake, using Intel's 10 nm SuperFin (10SF) process, released in Q4 2020
; Golden Cove:Successor to the Willow Cove core, includes improvements to performance and power efficiency. Also includes new instructions.{{cite web|last=Cutress|first=Dr Ian|title=Intel Alder Lake: Confirmed x86 Hybrid with Golden Cove and Gracemont for 2021|url=https://www.anandtech.com/show/15979/intel-alder-lake-confirmed-x86-hybrid-with-golden-cove-and-gracemont-for-2021|access-date=2021-04-10|website=www.anandtech.com}}
:* Alder Lake: hybrid processor, succeeds Rocket Lake and Tiger Lake; uses Intel 7 process (previously known as 10ESF),{{cite web|last=Cutress|first=Dr Ian|title=Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!|url=https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros|access-date=2021-07-27|website=www.anandtech.com}} released on November 4, 2021.{{cite web|url=https://www.anandtech.com/show/15686/intel-updates-isa-manual-new-instructions-for-alder-lake-also-bf16-for-sapphire-rapids|title=Intel Updates ISA Manual: New Instructions for Alder Lake, also BF16 for Sapphire Rapids|first=Ian|last=Cutress|date=April 1, 2020|website=AnandTech}} Golden Cove is used in P-cores of Alder Lake processors.{{cite web|url=https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures|title=Intel Architecture Day 2021: Alder Lake, Golden Cove, and Gracemont Detailed|date=2021-08-19|last1=Cutress|first1=Ian|last2=Frumusanu|first2=Andrei|website=AnandTech|language=en|access-date=2021-08-25}}
:* Sapphire Rapids: server and workstation-only, successor to Ice Lake-SP, manufactured on Intel 7 process,{{cite web|last=Pirzada|first=Usman|date=2020-10-07|title=Intel Sapphire Rapids: MCM Design, 56 Golden Cove Cores, 64GB HBM2 On-Board Memory, Massive IPC Improvement and 400 Watt TDP|url=https://wccftech.com/intel-sapphire-rapids-mcm-design-56-golden-cove-cores-64gb-hbm2-on-board-memory-massive-ipc-improvement-and-400-watt-tdp/|access-date=2021-04-06|website=Wccftech|language=en-US}} released on January 10, 2023. Introduces AMX.
; Raptor Cove:A refresh of Golden Cove with increased L2 and L3 caches and core clocks.
:* Raptor Lake: successor to Alder Lake with increased cache sizes, core clocks and the number of E-cores, released on October 20, 2022. Manufactured using Intel 7 process. Raptor Cove is used in the P-cores while the E-cores are still implemented using Gracemont microarchitecture.
:* Emerald Rapids: successor to Sapphire Rapids, server- and workstation-only. Fifth-generation Xeon Scalable server processors based on the Intel 7 node.
= x86 [[Ultra-low-voltage processor|ULV]] ([[Intel Atom|Atom]]) =
: 45 nm, low-power, in-order microarchitecture for use in Atom processors.
:* Saltwell: 32 nm shrink of the Bonnell microarchitecture.
: 22 nm, out-of-order microarchitecture for use in Atom processors, released on May 6, 2013.
:* Airmont: 14 nm shrink of the Silvermont microarchitecture.
: 14 nm Atom microarchitecture iteration after Silvermont but borrows heavily from Skylake processors (e.g., GPU), released in April 2016.{{cite web|title=Intel Software Development Emulator|url=http://software.intel.com/en-us/articles/intel-software-development-emulator}}{{cite web|title="Goldmont"- the sequel to Silvermont Atom?|date=23 July 2013 |url=https://forums.anandtech.com/threads/goldmont-the-sequel-to-silvermont-atom.2332517/|access-date=2020-03-02}}
:* Goldmont Plus: successor to Goldmont microarchitecture, still based on the 14 nm process, released on December 11, 2017.
; Tremont:10 nm Atom microarchitecture iteration after Goldmont Plus.
:* Lakefield: mobile-only, Intel's first hybrid processor, released in June 2020. Tremont is used in efficiency cores (E-cores) of Lakefield processors.
:* Jasper Lake: Celeron and Pentium Silver desktop and mobile processors, released in Q1 2021.
:* Elkhart Lake: embedded processors targeted at IoT, released in Q1 2021.
:Intel 7 process Atom microarchitecture iteration after Tremont. First Atom class core with AVX and AVX2 support.
:* Alder Lake: hybrid processor, succeeds Rocket Lake and Tiger Lake, released on November 4, 2021. Gracemont is used in E-cores of Alder Lake processors.
:* Raptor Lake: a refresh of Alder Lake, released on October 20, 2022.
= x86 [[Manycore processor|MIC]] (Many Integrated Core) =
;Larrabee (cancelled 2010)
: multi-core in-order x86-64 updated version of P5 microarchitecture, with wide SIMD vector units and texture sampling hardware for use in graphics.
Other microarchitectures
= [[IA-64]] ([[Itanium]]) =
; Merced: original Itanium microarchitecture. Used only in the first Itanium microprocessors.
; McKinley: enhanced microarchitecture used in the first two generations of the Itanium 2 microprocessor. Madison is the 130 nm version.
; Montecito: enhanced McKinley microarchitecture used in the Itanium 2 9000- and 9100-series of processors. Added dual core, coarse multithreading, and other improvements. The Montvale update added demand-based switching (SpeedStep) and core-level lockstep execution.
; Tukwila: enhanced microarchitecture used in the Itanium 9300 series of processors. Added quad core, an integrated memory controller, QuickPath Interconnect, and other improvements e.g. a more active SoEMT.
; Poulson: Itanium processor featuring an all-new microarchitecture.{{cite web | url=http://www.xbitlabs.com/news/cpu/display/20070619230827.html | title=Intel Plans to change Itanium Micro-Architecture | date=June 19, 2007 | author=Anton Shilov | publisher=X-bit Labs | access-date=2007-10-05 | url-status=dead | archive-url=https://web.archive.org/web/20071005082838/http://www.xbitlabs.com/news/cpu/display/20070619230827.html | archive-date=October 5, 2007 }} 8 cores, decoupling in pipeline and in multithreading. 12-wide issue with partial out-of-order execution.{{cite web|author=David Kanter |url=https://www.realworldtech.com/poulson/ |title=Poulson: The Future of Itanium Servers |publisher=Realworldtech.com |date=2011-05-18 |accessdate=2022-05-08}}
; Kittson: the last Itanium. It has the same microarchitecture as Poulson, but slightly higher clock speed for the top two models.
= Miscellaneous =
Roadmap
=Pentium 4 / Core lines=
{{mw-datatable}}
{{notelist}}
= Atom lines =
{{anchor|atom-roadmap}}
{{mw-datatable}}
{{Clear}}
See also
- List of Intel processors - Consumer Computer or non-consumer workstation
- List of AMD CPU microarchitectures
- Marvell Technology Group XScale microarchitecture
- Transient execution CPU vulnerability
Notes
{{NoteFoot}}
References
{{Reflist|colwidth=32em}}
External links
- [http://ark.intel.com/ Intel Automated Relational Knowledgebase]
{{Intel processor roadmap}}
{{Intel processors}}