process–architecture–optimization model

{{Expand Chinese|topic=tech}}{{short description|CPU development model by Intel}}

Process–architecture–optimization is a development model for central processing units (CPUs) that Intel adopted in 2016. Under this three-phase (three-year) model, every microprocessor die shrink is followed by a microarchitecture change and then by one or more optimizations. It replaced the two-phase (two-year) tick–tock model that Intel adopted in 2006. The tick–tock model was no longer economically sustainable, according to Intel, because production of ever smaller dies becomes ever more costly.[https://www.anandtech.com/show/9447/intel-10nm-and-kaby-lake Tick Tock On The Rocks: Intel Delays 10nm, Adds 3rd Gen 14nm Core Product "Kaby Lake"]. AnandTech. 16 July 2015.{{cite web|url=https://www.anandtech.com/show/10183/intels-tick-tock-seemingly-dead-becomes-process-architecture-optimization|title=Intel's 'Tick-Tock' Seemingly Dead, Becomes 'Process-Architecture-Optimization'|first=Ian|last=Cutress|publisher=}}{{cite web|url=https://www.eteknix.com/intel-ditches-tick-tock-for-process-architecture-optimization/|title=Intel Ditches 'Tick-Tock' for 'Process-Architecture-Optimization' - eTeknix|last=eTeknix.com|date=23 March 2016|publisher=}}{{cite web|url=https://www.legitreviews.com/intel-tick-tock-processor-model-replaced-process-architecture-optimization_180140|title=Intel Tick-Tock Processor Model Replaced With Process-Architecture-Optimization - Legit Reviews|date=23 March 2016|publisher=}}{{cite web|url=https://www.tomshardware.com/reviews/intel-7th-gen-core-kaby-lake-preview,4728-6.html|title=Intel 7th Gen Core: Process Architecture Optimization|date=30 August 2016|publisher=}}