WinChip

{{Infobox CPU

| name = WinChip

| image = KL_IDT_WinChip_Marketing_Sample.jpg

| image_size = 200px

| caption = IDT WinChip Marketing sample

| produced-start = {{start date and age|1997}}

| produced-end = {{end date and age|1999}}

| slowest = 180 | slow-unit = Mhz

| fastest = 266 | fast-unit = Mhz

| fsb-slowest = 60 | fsb-slow-unit = MT/s

| fsb-fastest = 100 | fsb-fast-unit = MT/s

| size-from = 0.35 μm

| size-to = 0.25 μm

| soldby = IDT

| designfirm = Centaur Technology

| manuf1 =

| core1 = C6

| core2 = W2, C6+

| core3 = W2A

| core4 = W2B

| core5 = W3

| sock1 = Socket 5

| sock2 = Socket 7

| sock3 = Super Socket 7

| pack1 = CPGA (C6, W2, W2A, W3)

| pack2 = PPGA (W2B)

| brand1 = WinChip

| arch = x86-16, IA-32

| microarch = Single, 4-stage, pipeline in-order execution

| cpuid = 0540h, 0541h, 0585h, 0587h, 058Ah, 0595h

| code =

| numcores = 1

| l1cache = 64 KiB (C6, W2, W2A and W2B)
128 KiB (W3)

| l2cache = Motherboard dependent

| l3cache = none

| application =

| predecessor =

| successor = Cyrix III

}}

The WinChip series is a discontinued low-power Socket 7-based x86 processor that was designed by Centaur Technology and marketed by its parent company IDT.

Overview

=Design=

The design of the WinChip was quite different from other processors of the time. Instead of a large gate count and die area, IDT, using its experience from the RISC processor market, created a small and electrically efficient processor similar to the 80486, because of its single pipeline and in-order execution microarchitecture. It was of much simpler design than its Socket 7 competitors, such as AMD K5/K6, which were superscalar and based on dynamic translation to buffered micro-operations with advanced instruction reordering (out of order execution).

=Use=

WinChip was, in general, designed to perform well with popular applications that did few floating point calculations, if any. This included operating systems of the time and the majority of software used in businesses. It was also designed to be a drop-in replacement for the more complex, and thus more expensive, processors it was competing with. This allowed IDT/Centaur to take advantage of an established system platform (Intel's Socket 7).

=Later developments=

WinChip 2, an update of C6, retained the simple in-order execution pipeline of its predecessor, but added dual MMX/3DNow! processing units that could operate in superscalar execution. This made it the only non-AMD CPU on Socket 7 to support 3DNow! instructions. WinChip 2A added fractional multipliers and adopted a 100 MHz front side bus to improve memory access and L2 cache performance.{{cite web |last=Hare |first=Chris |url=http://users.erols.com/chare/cpuspeed.htm |title=Processor Speed Settings |accessdate=24 April 2007 |url-status=dead |archiveurl=https://web.archive.org/web/20070428051306/http://users.erols.com/chare/cpuspeed.htm |archivedate=28 April 2007 }} It also adopted a performance rating nomenclature instead of reporting the real clock speed, similar to contemporary AMD and Cyrix processors.

Another revision, the WinChip 2B, was also planned. This featured a die shrink to 0.25 μm, but was only shipped in limited numbers.{{cite web |url=http://www.sandpile.org/impl/c2.htm |title=IA-32 implementation: Centaur WinChip 2 |work=SandPile.org |accessdate=29 April 2007 |url-status=dead |archiveurl=https://web.archive.org/web/20070427100243/http://sandpile.org/impl/c2.htm |archivedate=27 April 2007 }}

A third model, the WinChip 3, was planned as well. This was meant to receive a doubled L1 cache, but the W3 CPU never made it to market.

=Performance=

Although the small die size and low power-usage made the processor notably inexpensive to manufacture, it never gained much market share. WinChip C6 was a competitor to the Intel Pentium and Pentium MMX, Cyrix 6x86, and AMD K5/K6. It performed adequately, but only in applications that used little floating point math. Its floating point performance was simply well below that of the Pentium and K6, being even slower than the Cyrix 6x86.{{cite web |last=Pabst |first=Thomas |url=http://www.tomshardware.com/1997/10/09/the_idt_winchip_c6_cpu/ |title=The IDT WinChip C6 CPU |work=Tom's Hardware |date=9 October 1997 |accessdate=29 April 2007}}

Decline

The industry's move away from Socket 7 and the release of the Intel Celeron processor signalled the end of the WinChip. In 1999, the Centaur Technology division of IDT was sold to VIA. Although VIA branded the processors as "Cyrix", the company initially used technology similar to the WinChip in its Cyrix III line.{{cite web |last=Witheiler |first=Matthew |url=http://www.anandtech.com/showdoc.html?i=1396 |title=The New VIA Cyrix III: The Worlds First 0.15 Micron x86 CPU |work=AnandTech |date=5 January 2001 |accessdate=29 April 2007}}

Data

=Winchip C6 (0.35 μm)=

File:KL IDT WinChip C6.jpg

File:IDT WinChip C6 die.JPG]]

All models supported MMX{{cite web |url=http://www.sandpile.org/impl/c6.htm |title=IA-32 implementation: Centaur WinChip |work=Sandpile |accessdate=13 May 2007}}
The 88 mm{{sup|2}} die was made using a 0.35 micron 4-layer metal CMOS technology.
The 64 Kib L1 Cache of the WinChip C6 used a 32 KB 2-way set associative code cache and a 32 KB 2-way set associative data cache.

class="wikitable" style="text-align:center" ! Processor model !! Frequency !! FSB !! Mult. !! L1 cache !! TDP !! CPU core voltage !! Socket !! Release date !! Part number(s) !! Introduction price
WinChip 180	180 MHz	60 MT/s	3	64 KiB	9.4 W	3.45—3.6 V	{{ubl\|Socket 5\|Socket 7\|Super Socket 7\|CPGA 296}}	13 October 1997	DS180GAEM	$90
WinChip 200	200 MHz	66 MT/s	3	64 KiB	10.4 W	3.45—3.6 V	{{ubl\|Socket 5\|Socket 7\|Super Socket 7\|CPGA 296}}	13 October 1997	DS200GAEM	$135
WinChip 225	225 MHz	75 MT/s	3	64 KiB	12.3 W	3.45—3.6 V	{{ubl\|Socket 7\|Super Socket 7\|CPGA 296}}	13 October 1997	PSME225GA
WinChip 240	240 MHz	60 MT/s	4	64 KiB	13.1 W	3.45—3.6 V	{{ubl\|Socket 5\|Socket 7\|Super Socket 7\|CPGA 296}}	November 1997?	PSME240GA

=WinChip 2 (0.35 μm)=

File:KL IDT WinChip2.jpg

All models supported MMX and 3DNow!
The 95 mm{{sup|2}} die was made using a 0.35 micron 5-layer metal CMOS technology.
The 64 Kib L1 Cache of the WinChip 2 used a 32 KB 2-way set associative code cache and a 32 KB 4-way set associative data cache.

class="wikitable" style="text-align:center" ! Processor model !! Frequency !! FSB !! Mult. !! L1 cache !! TDP !! CPU core voltage !! Socket !! Release date !! Part number(s) !! Introduction price
WinChip 2-200	200 MHz	66 MT/s	3	64 KiB	8.8 W	3.45—3.6 V	{{ubl\|Socket 5\|Socket 7\|Super Socket 7\|CPGA 296}}		3DEE200GSA 3DFF200GSA
WinChip 2-225	225 MHz	75 MT/s	3	64 KiB	10.0 W	3.45—3.6 V	{{ubl\|Socket 7\|Super Socket 7\|CPGA 296}}		3DEE225GSA
WinChip 2-240	240 MHz	60 MT/s	4	64 KiB	10.5 W	3.45—3.6 V	{{ubl\|Socket 5\|Socket 7\|Super Socket 7\|CPGA 296}}		3DEE240GSA
WinChip 2-250	250 MHz	83 MT/s	3	64 KiB	10.9 W	3.45—3.6 V	{{ubl\|Super Socket 7\|CPGA 296}}	?

=WinChip 2A (0.35 μm)=

File:KL IDT WinChip2A.jpg

File:IDT_WinChip_2A_die.JPG

All models supported MMX{{cite web |title=PROCESSOR Version A Data Sheet|url=http://www.centtech.com/wc_2_datasheet_a2.pdf |archive-url=https://web.archive.org/web/20030322001250/http://www.centtech.com/wc_2_datasheet_a2.pdf |url-status=usurped |archive-date=March 22, 2003 |date=January 1999 |accessdate=2 November 2011}} and 3DNow!
The 95 mm{{sup|2}} die was made using a 0.35 micron 5-layer metal CMOS technology.
The 64 Kib L1 Cache of the WinChip 2A used a 32 KB 2-way set associative code cache and a 32 KB 4-way set associative data cache.

class="wikitable" style="text-align:center" ! Processor model !! Frequency !! FSB !! Mult. !! L1 cache !! TDP !! CPU core voltage !! Socket !! Release date !! Part number(s) !! Introduction price
WinChip 2A-200	200 MHz	66 MT/s	3	64 KiB	12.0 W	3.45—3.6 V	{{ubl\|Socket 5\|Socket 7\|Super Socket 7\|CPGA 296}}	March 1999?	3DEE200GTA
WinChip 2A-233	233 MHz	66 MT/s	3.5	64 KiB	13.0 W	3.45—3.6 V	{{ubl\|Socket 5\|Socket 7\|Super Socket 7\|CPGA 296}}	March 1999?	3DEE233GTA
align="center" \| WinChip 2A-266	233 MHz	100 MT/s	2.33	64 KiB	14.0 W	3.45—3.6 V	{{ubl\|Super Socket 7\|CPGA 296}}	March 1999?	3DEE266GSA
WinChip 2A-300	250 MHz	100 MT/s	2.5	64 KiB	16.0 W	3.45—3.6 V	{{ubl\|Super Socket 7\|CPGA 296}}		3DEE300GSA

=WinChip 2B (0.25 μm)=

File:KL IDT WinChip2 W2B.jpg

All models supported MMX{{cite web |title=PROCESSOR Data Sheet for WinChip 2 version B |url=http://www.centtech.com/w2b_datasheet.pdf |archive-url=http://wayback.archive-it.org/all/20111013013103/http://www.centtech.com/w2b_datasheet.pdf |url-status=usurped |archive-date=October 13, 2011 |date=April 1999 |accessdate=2 November 2011}} and 3DNow!
The 58 mm{{sup|2}} die was made using a 0.25 micron 5-layer metal CMOS technology.
The 64 Kib L1 Cache of the WinChip 2B used a 32 KB 2-way set associative code cache and a 32 KB 4-way set associative data cache.
Dual-voltage CPU: while the processor core operates at 2.8 V, the external input/output (I/O) voltages remain 3.3 V for backwards compatibility.

class="wikitable" style="text-align:center"

! Processor
model !! Frequency !! FSB !! Mult. !! L1 cache !! TDP !! CPU core voltage !! Socket !! Release date !! Part number(s) !! Introduction price

WinChip 2B-200

200 MHz

66 MT/s

64 KiB

6.3 W

2.7—2.9 V

3DFK200BTA

WinChip 2B-233