Comparison of ARM processors#ARMv8-A

|{{No|1}}|| ||8||{{No}}

|{{Optional|VFPv4 (optional)}}|| ||{{maybe|16 × 64-bit}}||{{Maybe|64-bit wide (optional)}}

|{{no}}

|{{No}}

|40/28 nm

| ||4–64 KiB / core||

|1, 2, 4

|1.57

|0xC05

|{{Maybe|2}}||5||8||{{No}}

|{{Yes|VFPv4}}||{{Yes}}||{{maybe|16 × 64-bit}}||{{Maybe|64-bit wide}}

|{{Yes|LITTLE}}

|{{Yes|Yes}}

|40/28 nm

| ||8–64 KiB / core||up to 1 MiB (optional)

|1, 2, 4, 8

|1.9

|0xC07

|{{Maybe|2}}||2||13||{{No}}

|{{Partial|VFPv3}}||{{No}}||{{good|32 × 64-bit}}||{{Maybe|64-bit wide}}

|{{No}}

|{{No}}

|65/55/45 nm

| ||32 KiB + 32 KiB||256 or 512 (typical) KiB

|1

|2.0

|0xC08

|{{Maybe|2}}||3||8–11||{{Yes}}

|{{Partial|VFPv3 (optional)}}||{{Yes}}||{{depends|(16 or 32) × 64-bit}}||{{Maybe|64-bit wide (optional)}}

|{{Partial|Companion Core}}

|{{No}}

|65/45/40/32/28 nm

| ||32 KiB + 32 KiB||1 MiB

|1, 2, 4

|2.5

|0xC09

|{{Maybe|2}}|| ||11||{{Yes}}

|{{Yes|VFPv4}}||{{Yes}}||{{good|32 × 64-bit}}||{{Good|128-bit wide}}

|{{No}}{{Cite web|url=http://community.arm.com/groups/processors/blog/2014/09/30/arm-cortex-a17-cortex-a12-processor-update|title = ARM Cortex-A17 / Cortex-A12 processor update – Architectures and Processors blog – Arm Community blogs – Arm Community}}

|{{Yes}}

|28 nm

| ||32–64 KiB + 32 KiB||256 KiB, to 8 MiB

|1, 2, 4

|3.0

|0xC0D

|{{Good|3}}||8||15/17-25||{{Yes}}

|{{Yes|VFPv4}}||{{Yes}}||{{good|32 × 64-bit}}||{{Good|128-bit wide}}

|{{Yes|big}}

|{{Yes|Yes}}

|32/28/20 nm

| ||32 KiB + 32 KiB per core||up to 4 MiB per cluster, up to 8 MiB per chip

|2, 4, 8 (4×2)

|3.5 to 4.01

|0xC0F

|{{Maybe|2}}|| ||11+||{{Yes}}

|{{Yes|VFPv4}}||{{Yes}}||{{good|32 × 64-bit}}||{{Good|128-bit wide}}

|{{Yes|big}}

|{{Yes}}

|28 nm

| ||32 KiB + 32 KiB per core||256 KiB, up to 8 MiB

|up to 4

|4.0

|0xC0E

|{{Maybe|2}}||3||10||{{Partial|Yes (FXU&LSU only){{Cite web |url=http://rtcgroup.com/arm/2007/presentations/253%20-%20ARM_DevCon_2007_Snapdragon_FINAL_20071004.pdf |title=Qualcomm High Performance Processor Core and Platform for Mobile Applications |first=Lou |last=Mallia |date=2007 |access-date=8 May 2014 |archive-date=26 April 2017 |archive-url=https://web.archive.org/web/20170426061946/http://rtcgroup.com/arm/2007/presentations/253%20-%20ARM_DevCon_2007_Snapdragon_FINAL_20071004.pdf |url-status=dead }}}}

|{{Partial|VFPv3}}||{{Yes}}|| ||{{Good|128-bit wide}}

|{{No}}

|

|65/45 nm

| ||32 KiB + 32 KiB||256 KiB (single-core)
512 KiB (dual-core)

|1, 2

|2.1

|0x00F

|{{Good|3}}||7||11||{{Yes}}

|{{Yes|VFPv4{{Cite web|url=http://www.anandtech.com/show/5559/qualcomm-snapdragon-s4-krait-performance-preview-msm8960-adreno-225-benchmarks/2|title = Qualcomm Snapdragon S4 (Krait) Performance Preview – 1.5 GHZ MSM8960 MDP and Adreno 225 Benchmarks}}}}||{{Yes}}|| ||{{Good|128-bit wide}}

|{{No}}

|

|28 nm

|4 KiB + 4 KiB direct mapped||16 KiB + 16 KiB 4-way set associative||1 MiB 8-way set associative (dual-core) / 2 MiB (quad-core)

|2, 4

|3.3 (Krait 200)
3.39 (Krait 300)
3.39 (Krait 400)
3.51 (Krait 450)

|0x04D

0x06F

|{{Good|3}}||5||12||{{Yes}}

|{{Yes|VFPv4}}||{{Yes}}||{{good|32 × 64-bit}}||{{Good|128-bit wide}}

|{{No}}

|

|32 nm

| ||32 KiB + 32 KiB||1 MiB

|2

|3.5

|?

!Decode
width

!Execution
ports

!Pipeline
depth

!Out-of-order execution

!FPU

!Pipelined
VFP

!FPU
registers

!NEON
(SIMD)

!big.LITTLE
role

!Virtualization

!Process
technology

!L0
cache

!L1
cache

!L2
cache

!Core
configurations

!Speed
per
core
(DMIPS
/ MHz)

!ARM part number
(in the main ID register)

! rowspan="2" | Core

! rowspan="2" | Released

! rowspan="2" | Revision

! rowspan="2" | Decode

! rowspan="2" | Pipeline
depth

! colspan="2" | Out-of-order
execution

! rowspan="2" | Branch
prediction

! rowspan="2" | big.LITTLE role

! rowspan="2" | Exec.
ports

! rowspan="2" | SIMD

! rowspan="2" | Fab
(in nm)

! rowspan="2" | Simult. MT

! rowspan="2" | L0 cache

! rowspan="2" | L1 cache
Instr + Data
(in KiB)

! rowspan="2" | L2 cache

! rowspan="2" | L3 cache

! rowspan="2" | Core
configu-
rations

! rowspan="2" | Speed per core (DMIPS/
MHz{{refn|group=note|name=first|As Dhrystone (implied in "DMIPS") is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads{{snd}} use with caution.}})

! rowspan="2" | Clock rate

! rowspan="2" | ARM part number (in the main ID register)

!Entries

! Cortex-A32 (32-bit){{cite news|last1=Frumusanu|first1=Andrei|title=ARM Announces Cortex-A32 IoT and Embedded Processor|url=http://www.anandtech.com/show/10061/arm-announces-cortex-a32|access-date=13 June 2016|publisher=Anandtech.com|date=22 February 2016}}

| 2017

| ARMv8.0-A
(only 32-bit) || 2-wide || 8 || {{No}} || 0 || {{dunno}} || {{Yes|LITTLE}} || {{dunno}} || {{dunno}}

| 28{{Cite web|url=https://www.arm.com/about/newsroom/new-ultra-efficient-arm-cortex-a32-processor-expands-embedded-and-iot-portfolio.php|title=New Ultra-efficient ARM Cortex-A32 Processor Expands… – ARM|website=arm.com|access-date=2016-10-01}}

| {{No}} || {{No}} || 8–64 + 8–64 || 0–1 MiB || {{No}} || 1–4+ || 2.3 || {{dunno}} || 0xD01

| 2019

|ARMv8.0-A
(only 64-bit)|| 2-wide || 8 || {{No}} || 0 || {{dunno}} || {{Yes|LITTLE}} || {{dunno}} || {{dunno}}

| {{dunno}} || {{No}} || {{No}} ||8–64 + 8–64 || 0–1 MiB || {{No}} || 1–4+ || {{dunno}} || {{dunno}} || 0xD02

| 2017

| ARMv8.0-A || 2-wide{{cite web|url=http://anandtech.com/show/9769/arm-announces-cortex-a35|title=ARM Announces New Cortex-A35 CPU – Ultra-High Efficiency For Wearables & More|first=Andrei|last=Frumusanu}}|| 8 || {{No}} || 0 || {{Yes}} || {{Yes|LITTLE}} || {{dunno}} || {{dunno}}

| 28 / 16 /
14 / 10 || {{No}} || {{No}} || 8–64 + 8–64 || 0 / 128 KiB–1 MiB || {{No}} || 1–4+ || 1.7-1.85 || {{dunno}} || 0xD04

| 2014

| ARMv8.0-A || 2-wide || 8 || {{No}} || 0 || rowspan="2" | Conditional+
Indirect branch
prediction || {{Yes|big/LITTLE}} || 2 || {{dunno}}

| 28 / 20 /
16 / 14 / 10 || {{No}} || {{No}} || 8–64 + 8–64 || 128 KiB–2 MiB || {{No}} || 1–4+ || 2.24{{cite web|title=Processing In Xilinx Devices|url=https://digilent.com/reference/_media/programmable-logic/arty-z7/processing_in_xilinx_devices.pdf|website=Digilent documents|access-date=24 January 2024}} || {{dunno}} || 0xD03

| 2017

| ARMv8.2-A || 2-wide || 8 || {{No}} || 0 || {{Yes|big/LITTLE}} || 2 || {{dunno}}

| 28 / 20 /
16 / 14 / 12 / 10 / 5{{cite web|title=Qualcomm Snapdragon 888 5G Mobile Platform |url=https://www.qualcomm.com/products/snapdragon-888-5g-mobile-platform|access-date=6 January 2021}}

| {{No}} || {{No}} || 16–64 + 16–64 || 0–256 KiB/core || {{Yes|0–4 MiB}} || 1–8+ || 2.65Based on 18% perf. increment over Cortex-A53 {{cite web|title=Arm Cortex-A55: Efficient performance from edge to cloud|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-cortex-a55-efficient-performance-from-edge-to-cloud|website=ARM|publisher=ARM Ltd}} || {{dunno}}

|0xD05

| 2013

| ARMv8.0-A || 3-wide || 15 || {{Yes}}
3-wide dispatch || {{dunno}} || {{dunno}} || {{Yes|big}} || 8 || {{dunno}}

| 28 / 20 /
16 / 14 || {{No}} || {{No}} || 48 + 32 || 0.5–2 MiB || {{No}} || 1–4+ || 4.1{{cite web|title=High Performance Processors, Other Interesting Talks|url=https://www.phoronix.com/forums/forum/hardware/processors-memory/1295407-risc-v-summit-2021-high-performance-processors-other-interesting-talks?p=1299818#post1299818|website=Phoronix comments|access-date=24 January 2024}}-4.8 || {{dunno}} ||0xD07

|2019

| ARMv8.2-A
(only 64-bit)|| 2-wide || 10-12 || {{Yes}}
4-wide dispatch

| || {{Yes|Two-level}} || {{dunno}} || 9

| || {{dunno}}

|SMT2

|No|| 32–64 + 32–64 KiB || 0, 64–256 KiB || 0, 0.5–4 MiB || 1-8 || {{dunno}} || {{dunno}}

|0xD06

|2019

| ARMv8.2-A || {{dunno}} || {{dunno}} || {{Yes}}

| || {{Yes|Two-level}} || {{dunno}} || 2

| || {{dunno}}

|SMT2

|No|| 32–64 + 32–64 KiB || 64–256 KiB || 0, 0.5–4 MiB || 1–8 || {{dunno}} || {{dunno}}

|0xD43

| 2015

| ARMv8.0-A || 3-wide || 15

|{{Yes}}
5-wide dispatch

| || {{Yes|Two-level}} || {{Yes|big}} || 8

| || 28 / 16

|No

|No|| 48 + 32 || 0.5–4 MiB || No || 1–4+ ||4.7-6.3 || {{dunno}}

|0xD08

| 2016

| ARMv8.0-A || 2-wide || 11–12

|{{Yes}}
4-wide dispatch

| || {{Yes|Two-level}} || {{Yes|big}} || 7

| || 28 / 16 / 10

|No

|No|| 64 + 32/64 || 1–8 MiB || No || 1–4+ || 4.8–8.5 || {{dunno}}

|0xD09

|2018

|ARMv8.2-A

|4-wide

|11–13

|{{Yes}}
8-wide dispatch

|128|| {{Yes|Two-level}} || {{Yes|big}} || 8

|2*128b

|10 / 7

|No

|No

|64 + 64

|256–512 KiB/core

|1–4 MiB

|1–4

|6.4

|{{dunno}}

|0xD0B

|2018

|ARMv8.2-A

|{{dunno}}

|{{dunno}}

|{{Yes}}

|128

|{{Yes|Two-level}}

|{{Yes|big}}

|{{dunno}}

|

|{{dunno}}

|No

|No

|{{dunno}}

|{{dunno}}

|{{dunno}}

|{{dunno}}

|{{dunno}}

|{{dunno}}

|0xD0E

|2019

|ARMv8.2-A

|4-wide

|11–13

|{{Yes}}
10-wide dispatch

|160|| {{Yes|Two-level}} || {{Yes|big}}

|12

|2*128b

|7

|No

|1.5K entries

|64 + 64

|256–512 KiB/core

|1–4 MiB

|1–4

|7.3According to ARM, the Cortex-A77 has a 20% IPC single-thread performance improvement over its predecessor in Geekbench 4, 23% in SPECint2006, 35% in SPECfp2006, 20% in SPECint2017, and 25% in SPECfp2017

|{{dunno}}

|0xD0D

|2020

|ARMv8.2-A

|4-wide

|

|{{Yes}}

|160

|Yes

|{{Yes|big}}

|13

|2*128b

|

|No

|1.5K entries

|32/64 + 32/64

|256–512 KiB/core

|1–4 MiB

|1–4

|7.6-8.2

|{{dunno}}

|0xD41

|2020

|ARMv8.2-A

|5-wide

|{{dunno}}

|{{yes}}

|224

|Yes

|{{Yes|big}}

|15

|4*128b

|

|No

|3K entries

|64 + 64

|up to 1 MiB

|up to 8 MiB

|custom

|10-11

|{{dunno}}

|0xD44

!Cyclone

| 2013

| ARMv8.0-A || 6-wide|| 16|| {{Yes}}

|192|| {{Yes}} || {{No}} || 9

| || 28

|No

|No|| 64 + 64|| 1 MiB|| 4 MiB|| 2 || {{dunno}} || 1.3–1.4 GHz

|

| 2014

| ARMv8.0‑A || 6-wide|| 16|| {{Yes}}

| || {{Yes}} || {{No}} || 9

| || 20

|No

|No|| 64 + 64|| 1 MiB|| 4 MiB|| 2, 3 (A8X) || {{dunno}} || 1.1–1.5 GHz

|

| 2015

| ARMv8.0‑A || 6-wide|| 16|| {{Yes}}

| || {{Yes}} || {{No}} || 9

| || 16 / 14

|No

|No|| 64 + 64|| 3 MiB|| 4 MiB
No (A9X)|| 2 || {{dunno}} || 1.85–2.26 GHz

|

|rowspan="2"|2016

|ARMv8.0‑A

|6-wide{{cite web|url=https://www.anandtech.com/show/13392/the-iphone-xs-xs-max-review-unveiling-the-silicon-secrets/3|title=Apple had shifted the microarchitecture in Hurricane (A10) from a 6-wide decode from to a 7-wide decode|publisher=AnandTech|date=5 October 2018}}

|16

|{{Yes}}

|

|

|{{Yes|"big" (In A10/A10X paired with "LITTLE" Zephyr
cores)}}

|9

|3*128b

|16 (A10)
10 (A10X)

|No

|No

|64 + 64{{Cite web|url=http://system-on-a-chip.specout.com/l/1223/Apple-A10-Fusion|title=Apple A10 Fusion|website=system-on-a-chip.specout.com|access-date=2016-10-01}}{{Dead link|date=July 2019 |bot=InternetArchiveBot |fix-attempted=yes }}

|3 MiB (A10)
8 MiB (A10X)

|4 MiB (A10)
No (A10X)

|2x Hurricane (A10)
3x Hurricane (A10X)

|{{dunno}}

|2.34–2.36 GHz

|

|ARMv8.0‑A

|3-wide

|12

|{{Yes}}

|

|

|{{Yes|LITTLE}}

|5

|

|16 (A10)
10 (A10X)

|No

|No

|32 + 32

|1 MiB

|4 MiB (A10)
No (A10X)

|2x Zephyr (A10)
3x Zephyr (A10X)

|{{dunno}}

|1.09–1.3 GHz

|

|rowspan="2"|2017

|ARMv8.2‑A{{cite web|url=https://devstreaming-cdn.apple.com/videos/wwdc/2018/409t8zw7rumablsh/409/409_whats_new_in_llvm.pdf|title=Apple A11 New Instruction Set Extensions|publisher=Apple Inc.|date=8 June 2018}}

|7-wide

|16

|{{Yes}}

|

|

|{{Yes|"big" (In Apple A11 paired with "LITTLE" Mistral
cores)}}

|11

|3*128b

|10

|No

|No

|64 + 64{{cite web|url=https://www.anandtech.com/show/13392/the-iphone-xs-xs-max-review-unveiling-the-silicon-secrets/2|title=Measured and Estimated Cache Sizes|publisher=AnandTech|date=5 October 2018}}

|8 MiB

|No

|2x Monsoon

|{{dunno}}

|2.39 GHz

|

|ARMv8.2‑A

|3-wide

|12

|{{Yes}}

|

|

|{{Yes|LITTLE}}

|5

|

|10

|No

|No

|32 + 32

|1 MiB

|No

|4× Mistral

|{{dunno}}

|1.19 GHz

|

|rowspan="2"|2018

|ARMv8.3‑A{{cite web|url=http://newosxbook.com/forum/viewtopic.php?f=11&t=19557|title=Apple A12 Pointer Authentication Codes|date=12 September 2018|publisher=Jonathan Levin, @Morpheus|access-date=8 October 2018|archive-date=10 October 2018|archive-url=https://web.archive.org/web/20181010011352/http://newosxbook.com/forum/viewtopic.php?f=11&t=19557|url-status=dead}}

|7-wide

|16

|{{Yes}}

|

|

|{{Yes|"big" (In Apple A12/Apple A12X/Apple A12Z paired with "LITTLE" Tempest
cores)}}

|11

|3*128b

|7

|No

|No

|128 + 128

|8 MiB

|No

|2x Vortex (A12)
4x Vortex (A12X/A12Z)

|{{dunno}}

|2.49 GHz

|

|ARMv8.3‑A

|3-wide

|12

|{{Yes}}

|

|

|{{Yes|LITTLE}}

|5

|

|7

|No

|No

|32 + 32

|2 MiB

|No

|4x Tempest

|{{dunno}}

|1.59 GHz

|

|rowspan="2"|2019

|ARMv8.4‑A{{cite web|url=http://newosxbook.com/ChangeLog.html#v2|title=A13 has ARMv8.4, apparently (LLVM project sources, thanks, @Longhorn)|publisher=Jonathan Levin, @Morpheus|date=13 March 2020}}

|8-wide

|16

|{{Yes}}

|560

|

|{{Yes|"big" (In Apple A13 paired with "LITTLE" Thunder
cores)}}

|11

|3*128b

|7

|No

|No

|128 + 128{{cite web|url=https://www.anandtech.com/show/14892/the-apple-iphone-11-pro-and-max-review/2|title=The Apple A13 SoC: Lightning & Thunder|publisher=AnandTech|date=16 October 2019}}

|8 MiB

|No

|2x Lightning

|{{dunno}}

|2.65 GHz

|

|ARMv8.4‑A

|3-wide

|12

|{{Yes}}

|

|

|{{Yes|LITTLE}}

|5

|

|7

|No

|No

|96 + 48{{cite web|url=https://www.anandtech.com/show/14892/the-apple-iphone-11-pro-and-max-review/3|title=The A13's Memory Subsystem: Faster L2, More SLC BW|publisher=AnandTech|date=16 October 2019}}

|4 MiB

|No

|4x Thunder

|{{dunno}}

|1.8 GHz

|

|rowspan="2"|2020

|ARMv8.4-A{{Cite web |title=llvm-project/llvm/lib/Target/AArch64/AArch64.td at main - llvm/llvm-project - GitHub |url=https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AArch64/AArch64.td |access-date=2023-07-03 |website=github.com |language=en}}

|8-wide{{cite web|url=https://www.anandtech.com/show/16226/apple-silicon-m1-a14-deep-dive/2|title=Apple Announces The Apple Silicon M1: Ditching x86 – What to Expect, Based on A14|publisher=AnandTech|date=10 November 2020}}

|

|{{Yes}}

|630{{Cite web|last=Frumusanu|first=Andrei|title=Apple Announces The Apple Silicon M1: Ditching x86 – What to Expect, Based on A14|url=https://www.anandtech.com/show/16226/apple-silicon-m1-a14-deep-dive|access-date=2020-11-25|website=anandtech.com}}

|

|{{Yes|"big" (In Apple A14 and Apple M1/M1 Pro/M1 Max/M1 Ultra paired with "LITTLE" Icestorm
cores)}}

|14

|4*128b

|5

|No

|

|192 + 128

|8 MiB (A14)
12 MiB (M1)
24 MiB (M1 Pro/M1 Max)
48 MiB (M1 Ultra)

|No

|2x Firestorm (A14)
4x Firestorm (M1)

6x or 8x Firestorm (M1 Pro)

8x Firestorm (M1 Max)

16x Firestorm (M1 Ultra)

|{{dunno}}

|3.0–3.23 GHz

|

|ARMv8.4-A

|4-wide

|

|{{Yes}}

|110

|

|{{Yes|LITTLE}}

|7

|2*128b

|5

|No

|

|128 + 64

|4 MiB
8 MiB (M1 Ultra)

|No

|4x Icestorm (A14/M1)
2x Icestorm (M1 Pro/Max)
4x Icestorm (M1 Ultra)

|{{dunno}}

|1.82–2.06 GHz

|

|rowspan="2"|2021

|ARMv8.6‑A

|8-wide

|

|{{Yes}}

|

|

|{{Yes|"big" (In Apple A15 and Apple M2/M2 Pro/M2 Max/M2 Ultra paired with "LITTLE" Blizzard
cores)}}

|14

|4*128b

|5

|No

|

|192 + 128

|12 MiB (A15)
16 MiB (M2)
32 MiB (M2 Pro/M2 Max)
64 MiB (M2 Ultra)

|No

|2x Avalanche (A15)
4x Avalanche (M2)
6x or 8x Avalanche (M2 Pro)

8x Avalanche (M2 Max)
16x Avalanche (M2 Ultra)

|{{dunno}}

|2.93–3.49 GHz

|

|ARMv8.6‑A

|4-wide

|

|{{Yes}}

|

|

|{{Yes|LITTLE}}

|8

|2*128b

|5

|No

|

|128 + 64

|4 MiB
8 MiB (M2 Ultra)

|No

|4x Blizzard

|{{dunno}}

|2.02–2.42 GHz

|

|rowspan="2"|2022

|ARMv8.6‑A

|8-wide

|

|{{Yes}}

|

|

|{{Yes|"big" (In Apple A16 paired with "LITTLE" Sawtooth
cores)}}

|14

|4*128b

|5

|No

|

|192 + 128

|16 MiB

|No

|2x Everest

|{{dunno}}

|3.46 GHz

|

|ARMv8.6‑A

|4-wide

|

|{{Yes}}

|

|

|{{Yes|LITTLE}}

|8

|2*128b

|5

|No

|

|128 + 64

|4 MiB

|No

|4x Sawtooth

|{{dunno}}

|2.02 GHz

|

!Denver{{cite web|url=http://www.linleygroup.com/mpr/article.php?id=11262|title=Denver Uses Dynamic Translation to Outperform Mobile Rivals|last1=Gwennap|first1=Linley|website=The Linley Group|access-date=24 April 2015}}

|2014

|ARMv8‑A

| 2-wide hardware
decoder, up to
7-wide variable-
length VLIW
micro-ops

| 13

| {{Maybe|Not if the hardware
decoder is in use.
Can be provided
by dynamic software
translation into VLIW.}}

|

| Direct+
Indirect branch
prediction

| No

| 7

|

| 28

|No

|No

| 128 + 64

| 2 MiB

| No

| 2

|{{dunno}}

| {{dunno}}

|

|2016

| ARMv8‑A

| {{dunno}}

| 13

| {{Maybe|Not if the hardware
decoder is in use.
Can be provided
by dynamic software
translation into VLIW.}}

|

| Direct+
Indirect branch
prediction

| "Super" Nvidia's own implementation

| {{dunno}}

|

| 16

|No

|No

| 128 + 64

| 2 MiB

| No

| 2|| {{dunno}}

|{{dunno}}

|

|2018

| ARMv8.2‑A

| {{dunno}}

|

|

|

| Direct+
Indirect branch
prediction

|

| {{dunno}}

|

| 12

|No

|No

| 128 + 64

| 2 MiB

| (4 MiB @ 8 cores)

| 2 (+ 8)

| 6.5-7.4

| {{dunno}}

|

!ThunderX{{cite news|last1=De Gelas|first1=Johan|title=ARM Challenging Intel in the Server Market|url=http://www.anandtech.com/show/8776/arm-challinging-intel-in-the-server-market-an-overview|access-date=8 March 2017|publisher=Anandtech|date=16 December 2014}}{{cite news|last1=De Gelas|first1=Johan|title=Investigating the Cavium ThunderX|url=http://www.anandtech.com/show/10353/investigating-cavium-thunderx-48-arm-cores|access-date=8 March 2017|publisher=Anandtech|date=15 June 2016}}

| 2014

| ARMv8-A || 2-wide || 9 || {{Yes}}

| || {{Yes|Two-level}} || || {{dunno}}

| || 28

|No

|No|| 78 + 32|| 16 MiB|| No || 8–16, 24–48 || {{dunno}} || {{dunno}}

|

| 2018{{cite news|last1=Kennedy|first1=Patrick|title=Cavium ThunderX2 256 Thread Arm Platforms Hit General Availability|url=https://www.servethehome.com/cavium-thunderx2-hits-general-availability/|access-date=10 May 2018|date=7 May 2018}}

| ARMv8.1-A
{{cite web|url=https://reviews.llvm.org/D21500|title=⚙ D21500 [AARCH64] Add support for Broadcom Vulcan|website=reviews.llvm.org}}|| 4-wide
"4 μops"{{Cite web |last=Hayes |first=Eric |date=April 7, 2014 |title=IDC HPC USER FORUM |url=https://hpcuserforum.com/presentations/santafe2014/Broadcom%20Monday%20night.pdf |website=hpcuserforum.com}}{{cite web|url=http://www.linleygroup.com/events/agenda.php?num=24&day=1|title=The Linley Group – Processor Conference 2013|website=linleygroup.com}}|| {{dunno}} || {{Yes}}{{cite web|url=http://www.cavium.com/ThunderX2_ARM_Processors.html|title=ThunderX2 ARM Processors- A Game Changing Family of Workload Optimized Processors for Data Center and Cloud Applications – Cavium|website=cavium.com}}

| || {{Yes|Multi-level}} || {{dunno}} || {{dunno}}

| || 16

|SMT4

|No|| 32 + 32
(data 8-way) || 256 KiB
per core{{cite news|last1=Kennedy|first1=Patrick|title=Cavium ThunderX2 Review and Benchmarks a Real Arm Server Option|url=https://www.servethehome.com/cavium-thunderx2-review-benchmarks-real-arm-server-option/|access-date=10 May 2018|publisher=Serve the Home|date=9 May 2018}}|| 1 MiB
per core|| 16–32|| {{dunno}} || {{dunno}}

|

! ThunderX3

| 2020{{cite news|last1=Frumusanu|first1=Andrei|title=Marvell Announces ThunderX3: 96 Cores & 384 Thread 3rd Gen Arm Server Processor|url=https://www.anandtech.com/show/15621/marvell-announces-thunderx3-96-cores-384-thread-3rd-gen-arm-server-processor|date=16 March 2020}}

| ARMv8.3+|| 8-wide || {{dunno}} || {{Yes}}
4-wide dispatch

| || {{Yes|Multi-level}} || {{dunno}} || 7

| || 7

|SMT4

|{{dunno}} || 64 + 32 || 512 KiB
per core || 90 MiB || 60 || {{dunno}} || {{dunno}}

|

Micro

!Helix

| 2014 || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}}

| || {{dunno}} || {{dunno}} || {{dunno}}

| || 40 / 28

|No

|No|| rowspan="3" | 32 + 32 (per core;
write-through
w/parity){{cite news |url=http://anandtech.com/show/8588/armv8-goes-embedded-with-applied-micros-helix-socs |title=ARMv8 Goes Embedded with Applied Micro's HeliX SoCs |author=Ganesh T S |publisher=AnandTech|date=3 October 2014 |access-date=9 October 2014}}|| rowspan="3" | 256 KiB shared
per core pair (with ECC) || 1 MiB/core || 2, 4, 8 || {{dunno}} || {{dunno}}

|

| 2013

| {{dunno}} || 4-wide || 15 || {{Yes}}

| || {{dunno}} || {{dunno}} || {{dunno}}

| || 40{{cite news |url=http://www.enterprisetech.com/2014/08/12/applied-micro-plots-x-gene-arm-server-future/ |title=Applied Micro Plots Out X-Gene ARM Server Future |first=Timothy Prickett |last=Morgan |publisher=Enterprisetech |date=12 August 2014 |access-date=9 October 2014}}

|No

|No|| 8 MiB || 8 || 4.2 || {{dunno}}

|

| 2015

| {{dunno}} || 4-wide || 15 || {{Yes}}

| || {{dunno}} || {{dunno}} || {{dunno}}

| || 28{{cite news|last1=De Gelas|first1=Johan|title=AppliedMicro's X-Gene 3 SoC Begins Sampling|url=http://www.anandtech.com/show/11189/appliedmicro-x-gene-3-soc-starts-sampling|access-date=15 March 2017|publisher=Anandtech|date=15 March 2017}}

|No

|No|| 8 MiB || 8 || 4.2 || {{dunno}}

|

!Kryo

| 2015

| ARMv8-A || {{dunno}} || {{dunno}} || {{Yes}}

| || {{Yes|Two-level?}} || {{Yes|"big" or "LITTLE"
Qualcomm's own similar implementation}} || {{dunno}}

| || 14{{cite web|url=https://www.qualcomm.com/news/snapdragon/2015/09/02/snapdragon-820-and-kryo-cpu-heterogeneous-computing-and-role-custom |title=Snapdragon 820 and Kryo CPU: heterogeneous computing and the role of custom compute |publisher=Qualcomm |date=2 September 2015 |access-date=6 September 2015}}

|No

|No|| 32+24{{cite web|url=http://www.anandtech.com/show/9837/snapdragon-820-preview/|title=The Qualcomm Snapdragon 820 Performance Preview: Meet Kryo|first=Ryan Smith, Andrei|last=Frumusanu}}|| 0.5–1 MiB || || 2+2 || 6.3 || {{dunno}}

|

| rowspan="2" | 2016

| rowspan="2" |ARMv8-A

|2-wide

|11–12|| {{Yes}}
7-wide dispatch

| || {{Yes|Two-level}} || {{Yes|big}}

|| 7

|

| rowspan="2" |14 / 11 / 10 / 6{{Cite news|url=https://www.anandtech.com/show/12420/snapdragon-845-performance-preview|title=The Snapdragon 845 Performance Preview: Setting the Stage for Flagship Android 2018|last=Smith|first=Andrei Frumusanu, Ryan|access-date=2018-06-11}}

| rowspan="2" |No

| rowspan="2" |No

|64 + 32/64?

|512 KiB/Gold Core

| rowspan="2" |No

|4||{{dunno}}||1.8–2.45 GHz

|

| rowspan="2" |2017

| rowspan="2" |ARMv8.2-A

|3-wide

|11–13|| {{Yes}}
8-wide dispatch

| || {{Yes|Two-level}} || {{Yes|big}}

||8

|

| rowspan="2" |10

| rowspan="2" |No

| rowspan="2" |No

|64+64

|256 KiB/Gold Core

| rowspan="2" |2 MiB

|2, 4||{{dunno}}||2.0–2.95 GHz

|

| rowspan="2" |2018

| rowspan="2" |ARMv8.2-A

|4-wide

|11–13|| {{Yes}}
8-wide dispatch

| || {{Yes}} || {{Yes|big}}

|8

|

| rowspan="2" |11 / 8 / 7

| rowspan="2" |No

| rowspan="2" |No

|64 + 64

|512 KiB/Gold Prime

256 KiB/Gold

| rowspan="2" |2 MiB

|2, 1+1, 4, 1+3 || {{dunno}} || 2.0–2.96 GHz

|

| rowspan="2" |2019

| rowspan="2" |ARMv8.2-A

|4-wide

|11–13|| {{Yes}}
8-wide dispatch

| || {{Yes}} || {{Yes|big}}

|

|

| rowspan="2" |8 / 7

| rowspan="2" |No

|?

|

|512 KiB/Gold Prime

256 KiB/Gold

| rowspan="2" |3 MiB

|2, 1+3

|{{dunno}}

|2.0–3.2 GHz

|

| rowspan="2" |2020

| rowspan="2" |ARMv8.4-A

|4-wide

|11–13|| {{Yes}}
8-wide dispatch

| || {{Yes}} || {{Yes|big}}

|

|

| rowspan="2" |6 / 5

| rowspan="2" |No

|?

|64 + 64

|1024 KiB/Gold Prime

512 KiB/Gold

| rowspan="2" |4 MiB

|2, 1+3

|{{dunno}}

|2.2–3.0 GHz

|

| 2017{{cite news|last1=Shrout|first1=Ryan|title=Qualcomm Centriq 2400 Arm-based Server Processor Begins Commercial Shipment|url=https://www.pcper.com/news/Processors/Qualcomm-Centriq-2400-Arm-based-Server-Processor-Begins-Commercial-Shipment|access-date=8 November 2017|publisher=PC Per|date=8 November 2017}}

| "ARMv8.1-A features"; AArch64 only (not 32-bit)|| 4-wide || 10–15 || {{yes|Yes
8-wide dispatch}}

| || {{Yes|Yes}} || {{dunno}} || 8

| || 10

|No

|24 KiB|| 88 + 32 || 500KiB || 1.25MiB || 40–48 || {{dunno}} || {{dunno}}

|

! M1{{cite web|url=http://www.anandtech.com/show/10590/hot-chips-2016-exynos-m1-architecture-disclosed|title=Hot Chips 2016: Exynos M1 Architecture Disclosed|first=Joshua|last=Ho}}{{cite web|url=http://www.anandtech.com/show/9781/samsung-announces-exynos-8890-with-cat1213-modem-and-custom-cpu|title=Samsung Announces Exynos 8890 with Cat.12/13 Modem and Custom CPU|first=Andrei|last=Frumusanu}}

| 2016

| ARMv8-A || 4-wide || 13{{cite news|last1=Frumusanu|first1=Andrei|title=The Samsung Exynos M3 – 6-wide Decode with 50%+ IPC Increase|url=https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture|access-date=25 January 2018|publisher=Anandtech|date=23 January 2018}}|| {{Yes}}
9-wide dispatch{{cite web|last1=Frumusanu|first1=Andrei|title=Hot Chips 2016: Exynos M1 Architecture Disclosed|url=http://www.anandtech.com/show/10590/hot-chips-2016-exynos-m1-architecture-disclosed|website=Anandtech|access-date=29 May 2017}}

|96

|| || {{Yes|big}} || 8

| || 14

|No

|No|| 64 + 32 || 2 MiB{{cite web|url=https://www.theregister.co.uk/2016/08/22/samsung_m1_core/|title='Neural network' spotted deep inside Samsung's Galaxy S7 silicon brain|website=The Register }}|| No || 4 || {{dunno}} || 2.6 GHz

|

|2019

|ARMv8.2-A

|6-wide

|15|| {{Yes}}
12-wide dispatch

|228|| {{Yes|Two-level}} || {{Yes|big}}

|12

|

|8 / 7

|No

|No

|64 + 64

|512 KiB per core

|3072KB

|2

|{{dunno}}

|2.73 GHz

|

|2020

|ARMv8.2-A

|6-wide

| || {{Yes}}
12-wide dispatch

|228|| {{Yes|Two-level}} || {{Yes|big}}

|

|

|7

|No

|No

|64 + 64

|512 KiB per core

|3072KB

|2

|{{dunno}}

|2.73 GHz

|

! A64FX{{citation|title=Fujitsu High Performance CPU for the Post-K Computer|url=https://www.fujitsu.com/global/documents/solutions/business-technology/tc/catalog/20180821hotchips30.pdf|access-date=16 September 2019|date=2018-07-21}}{{citation|title=Arm A64fx and Post-K: Game Changing CPU & Supercomputer for HPC and its Convergence of with Big Data / AI|url=https://www.hpcuserforum.com/presentations/april2019/Rikenmatsuoka.pdf|access-date=16 September 2019|date=2019-04-03}}

|2019

|ARMv8.2-A

|4/2-wide

|7+ || {{Yes}}
5-way?

| || {{Yes}} || n/a

|8+

|2*512b{{Cite web|title=Fujitsu Successfully Triples the Power Output of Gallium-Nitride Transistors – Fujitsu Global|url=https://www.fujitsu.com/global/about/resources/news/press-releases/2018/0822-02.html|access-date=2020-11-23|website=fujitsu.com}}

|7

|No

|No

|64 + 64

|8MiB per 12+1 cores

|No

|48+4

|{{dunno}}

|1.9 GHz+

|

! TaiShan V110{{Cite web|url=https://fuse.wikichip.org/news/2274/huawei-expands-kunpeng-server-cpus-plans-smt-sve-for-next-gen/|title=Huawei Expands Kunpeng Server CPUs, Plans SMT, SVE For Next Gen|last=Schor|first=David|date=2019-05-03|website=WikiChip Fuse|language=en-US|access-date=2019-12-13}}

|2019

|ARMv8.2-A

|4-wide

|?

|{{Yes}}

|

|

|n/a

|8

|7

|

|No

|No

|64 + 64

|512 KiB per core

|1 MiB per core

|{{dunno}}

|{{dunno}}

|{{dunno}}

|

! Core

! Released

! Revision

! Decode

!Pipeline
depth

! colspan="2" |Out-of-order
execution

!Branch
prediction

!big.LITTLE role

! Exec. ports

!SIMD

!Fab
(in nm)

!Simult. MT

!L0 cache

!L1 cache
Instr + Data
(in KiB)

! L2 cache

! L3 cache

! Core
configu-
rations

! Speed per core (DMIPS/
MHz{{refn|group=note|name=first|As Dhrystone (implied in "DMIPS") is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads{{snd}} use with caution.}})

!Clock rate

!ARM part number (in the main ID register)

!Entries