Flash memory#Memory wear

The origins of flash memory can be traced to the development of the floating-gate MOSFET (FGMOS), also known as the floating-gate transistor.{{Cite news |date=11 March 2006 |title=Not just a flash in the pan |agency=Reuters |url=https://www.economist.com/technology-quarterly/2006/03/11/not-just-a-flash-in-the-pan |url-status=live |url-access=limited |access-date=10 September 2019 |archive-url=https://web.archive.org/web/20231121163825/https://www.economist.com/technology-quarterly/2006/03/11/not-just-a-flash-in-the-pan |archive-date=21 November 2023 |newspaper=The Economist }}{{cite book |last1=Bez |first1=R. |last2=Pirovano |first2=A. |title=Advances in Non-Volatile Memory and Storage Technology |date=2019 |publisher=Woodhead Publishing |isbn=9780081025857}} The original MOSFET was invented at Bell Labs between 1955 and 1960, after Frosch and Derick discovered surface passivation and used their discovery to create the first planar transistors.{{Cite patent|number=US2802760A|title=Oxidation of semiconductive surfaces for controlled diffusion|gdate=1957-08-13|invent1=Lincoln|invent2=Frosch|inventor1-first=Derick|inventor2-first=Carl J.|url=https://patents.google.com/patent/US2802760A}}{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |pages=547 |doi=10.1149/1.2428650}}{{Cite journal |last=KAHNG |first=D. |date=1961 |title=Silicon-Silicon Dioxide Surface Device |url=https://doi.org/10.1142/9789814503464_0076 |journal=Technical Memorandum of Bell Laboratories|pages=583–596 |doi=10.1142/9789814503464_0076 |isbn=978-981-02-0209-5 }}{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}{{Cite journal |last1=Ligenza |first1=J.R. |last2=Spitzer |first2=W.G. |date=1960 |title=The mechanisms for silicon oxidation in steam and oxygen |url=https://linkinghub.elsevier.com/retrieve/pii/0022369760902195 |journal=Journal of Physics and Chemistry of Solids |language=en |volume=14 |pages=131–136 |doi=10.1016/0022-3697(60)90219-5|bibcode=1960JPCS...14..131L }}{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer Science & Business Media |isbn=9783540342588 |page=120}} Dawon Kahng went on to develop a variation, the floating-gate MOSFET, with Taiwanese-American engineer Simon Min Sze at Bell Labs in 1967.{{Cite web |date=11 June 2018 |title=1971: Reusable semiconductor ROM introduced |url=https://www.computerhistory.org/storageengine/reusable-semiconductor-rom-introduced/ |url-status=live |archive-url=https://web.archive.org/web/20230810204956/https://www.computerhistory.org/storageengine/reusable-semiconductor-rom-introduced/ |archive-date=10 August 2023 |access-date=19 June 2019 |website=The Storage Engine |publisher=Computer History Museum }} They proposed that it could be used as floating-gate memory cells for storing a form of programmable read-only memory (PROM) that is both non-volatile and re-programmable.

Early types of floating-gate memory included EPROM (erasable PROM) and EEPROM (electrically erasable PROM) in the 1970s. However, early floating-gate memory required engineers to build a memory cell for each bit of data, which proved to be cumbersome,{{cite web |last=Fulford |first=Adel |title=Unsung hero |work=Forbes |date=24 June 2002 |access-date=18 March 2008 |url=https://www.forbes.com/global/2002/0624/030.html |url-status=live |archive-url=https://web.archive.org/web/20080303205125/http://www.forbes.com/global/2002/0624/030.html |archive-date=3 March 2008}} slow,{{Cite web |last=Tyson |first=Jeff |date=29 August 2000 |title=How ROM Works |url=https://computer.howstuffworks.com/rom.htm#pt5 |url-status=live |archive-url=https://web.archive.org/web/20231202082951/https://computer.howstuffworks.com/rom.htm#pt5 |archive-date=2 December 2023 |access-date=10 September 2019 |website=HowStuffWorks }} and expensive, restricting floating-gate memory to niche applications in the 1970s, such as military equipment and the earliest experimental mobile phones.

Modern EEPROM based on Fowler-Nordheim tunnelling to erase data was invented by Bernward and patented by Siemens in 1974.{{Cite patent|number=GB1517925A|title=Storage field effect transistors|gdate=1978-07-19|url=https://patents.google.com/patent/GB1517925A/en}} It was further developed between 1976 and 1978 by Eliyahou Harari at Hughes Aircraft Company, as well as by George Perlegos and others at Intel.{{cite web |last1=Simko |first1=Richard T. |date=17 March 1977 |title=Electrically programmable and electrically erasable MOS memory cell |url=https://patents.google.com/patent/US4119995A/en}}{{cite web |last1=Frohman-Bentchkowsky |first1=Dov |last2=Mar |first2=Jerry |last3=Perlegos |first3=George |last4=Johnson |first4=William S. |date=15 December 1978 |title=Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same |url=https://patents.google.com/patent/US4203158A/en}} This led to Masuoka's invention of flash memory at Toshiba in 1980.{{patent|US|4531203|Fujio Masuoka}}{{US patent|4531203|Semiconductor memory device and method for manufacturing the same}} The improvement between EEPROM and flash being that flash is programmed in blocks while EEPROM is programmed in bytes. According to Toshiba, the name "flash" was suggested by Masuoka's colleague, Shōji Ariizumi, because the erasure process of the memory contents reminded him of the flash of a camera.{{cite web |url=http://www.eweek.com/c/a/Data-Storage/NAND-Flash-Memory-25-Years-of-Invention-Development-684048/ |archive-url=https://archive.today/20140818204913/http://www.eweek.com/c/a/Data-Storage/NAND-Flash-Memory-25-Years-of-Invention-Development-684048/ |url-status=dead |archive-date=18 August 2014 |title=NAND Flash Memory: 25 Years of Invention, Development – Data Storage – News & Reviews |work=eWeek.com |access-date=18 August 2014 }} Masuoka and colleagues presented the invention of NOR flash in 1984,{{Cite web |title=Toshiba: Inventor of Flash Memory |url=http://www.flash25.toshiba.com |url-status=dead |archive-url=https://web.archive.org/web/20190620160642/http://www.flash25.toshiba.com/ |archive-date=20 June 2019 |access-date=20 June 2019 |website=Toshiba }}{{Cite conference |last2=Asano |first2=M. |last3=Iwahashi |first3=H. |last4=Komuro |first4=T. |last5=Tanaka |first5=S. |date=December 1984 |title=A new flash E²PROM cell using triple polysilicon technology |conference=1984 International Electron Devices Meeting |location=San Francisco|pages=464–467 |doi=10.1109/IEDM.1984.190752 |s2cid=25967023 |first1=F. |last1=Masuoka }} and then NAND flash at the IEEE 1987 International Electron Devices Meeting (IEDM) held in San Francisco.{{cite conference |title=New ultra high density EPROM and flash EEPROM with NAND structure cell |last1=Masuoka |first1=F. |last2=Momodomi |first2=M. |last3=Iwata |first3=Y. |last4=Shirota |first4=R. |year=1987 |pages=552–555 |conference=IEDM 1987 |book-title=Electron Devices Meeting, 1987 International |publisher=IEEE|doi=10.1109/IEDM.1987.191485}}

Toshiba commercially launched NAND flash memory in 1987.{{cite web |title=1987: Toshiba Launches NAND Flash |url=https://www.eweek.com/storage/1987-toshiba-launches-nand-flash |website=eWeek |date=11 April 2012 |access-date=20 June 2019}} Intel Corporation introduced the first commercial NOR type flash chip in 1988.{{cite web |url=http://www2.electronicproducts.com/NAND_vs_NOR_flash_technology-article-FEBMSY1-FEB2002.aspx |title=NAND vs. NOR flash technology: The designer should weigh the options when using flash memory |last=Tal |first=Arie |date=February 2002 |access-date=31 July 2010 |url-status=dead |archive-url=https://web.archive.org/web/20100728210327/http://www2.electronicproducts.com/NAND_vs_NOR_flash_technology-article-FEBMSY1-FEB2002.aspx |archive-date=28 July 2010}} NOR-based flash has long erase and write times, but provides full address and data buses, allowing random access to any memory location. This makes it a suitable replacement for older read-only memory (ROM) chips, which are used to store program code that rarely needs to be updated, such as a computer's BIOS or the firmware of set-top boxes. Its endurance may be from as little as 100 erase cycles for an on-chip flash memory,{{Cite web |date=October 2004 |title=H8S/2357 Group, H8S/2357F-ZTATTM, H8S/2398F-ZTATTM Hardware Manual |url=https://www.renesas.com/us/en/document/mas/h8s2357-group-h8s2357f-ztattm-h8s2398f-ztattm-hardware-manual |url-status=live |archive-url=https://web.archive.org/web/20230109212444/https://www.renesas.com/us/en/document/mas/h8s2357-group-h8s2357f-ztattm-h8s2398f-ztattm-hardware-manual |archive-date=9 January 2023 |access-date=23 January 2012 |publisher=Renesas |page=574 |quote=The flash memory can be reprogrammed up to 100 times. }} to a more typical 10,000 or 100,000 erase cycles, up to 1,000,000 erase cycles.{{Cite web |date=July 2003 |title=AMD DL160 and DL320 Series Flash: New Densities, New Features |url=http://www.spansion.com/Support/Application%20Notes/AMD%20DL160%20and%20DL320%20Series%20Flash-%20New%20Densities,%20New%20Features.pdf |url-status=dead |archive-url=https://web.archive.org/web/20150924104223/http://www.spansion.com/Support/Application%20Notes/AMD%20DL160%20and%20DL320%20Series%20Flash-%20New%20Densities,%20New%20Features.pdf |archive-date=24 September 2015 |access-date=13 November 2014 |publisher=AMD |id=22271A |quote=The devices offer single-power-supply operation (2.7 V to 3.6 V), sector architecture, Embedded Algorithms, high performance, and a 1,000,000 program/erase cycle endurance guarantee. }} NOR-based flash was the basis of early flash-based removable media; CompactFlash was originally based on it, although later cards moved to less expensive NAND flash.

NAND flash has reduced erase and write times, and requires less chip area per cell, thus allowing greater storage density and lower cost per bit than NOR flash. However, the I/O interface of NAND flash does not provide a random-access external address bus. Rather, data must be read on a block-wise basis, with typical block sizes of hundreds to thousands of bits. This makes NAND flash unsuitable as a drop-in replacement for program ROM, since most microprocessors and microcontrollers require byte-level random access. In this regard, NAND flash is similar to other secondary data storage devices, such as hard disks and optical media, and is thus highly suitable for use in mass-storage devices, such as memory cards and solid-state drives (SSD). For example, SSDs store data using multiple NAND flash memory chips.

The first NAND-based removable memory card format was SmartMedia, released in 1995. Many others followed, including MultiMediaCard, Secure Digital, Memory Stick, and xD-Picture Card.

A new generation of memory card formats, including RS-MMC, miniSD and microSD, feature extremely small form factors. For example, the microSD card has an area of just over 1.5 cm², with a thickness of less than 1 mm.

NAND flash has achieved significant levels of memory density as a result of several major technologies that were commercialized during the late 2000s to early 2010s.{{Cite conference |date=May 2014 |title=3D ICs in the real world |url=https://www.researchgate.net/publication/271453642 |conference=25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014) |location=Saratoga Springs, NY |pages=113–119 |doi=10.1109/ASMC.2014.6846988 |isbn=978-1-4799-3944-2 |issn=2376-6697 |doi-access= |last1=James |first1=Dick |s2cid=42565898 |url-access=subscription }}

NOR flash was the most common type of Flash memory sold until 2005, when NAND flash overtook NOR flash in sales.{{Cite web|url=https://www.cnet.com/culture/nand-overtakes-nor-in-flash-memory/|title=NAND overtakes NOR in flash memory|website=CNET}}

Multi-level cell (MLC) technology stores more than one bit in each memory cell. NEC demonstrated multi-level cell (MLC) technology in 1998, with an 80{{nbsp}}Mb flash memory chip storing 2 bits per cell.{{Cite press release |last=Bridgman |first=Aston |date=28 October 1997 |title=NEC and SanDisk Develop 80Mb Flash Memory |url=http://www.nec.co.jp/press/en/9710/2801.html |url-status=dead |archive-url=https://web.archive.org/web/20201018114043/http://www.nec.co.jp/press/en/9710/2801.html |archive-date=18 October 2020 |publisher=NEC |id=97/10/28-01 }} STMicroelectronics also demonstrated MLC in 2000, with a 64{{nbsp}}MB NOR flash memory chip. In 2009, Toshiba and SanDisk introduced NAND flash chips with QLC technology storing 4 bits per cell and holding a capacity of 64{{nbsp}}Gb. Samsung Electronics introduced triple-level cell (TLC) technology storing 3-bits per cell, and began mass-producing NAND chips with TLC technology in 2010.

{{Main|Charge trap flash}}

Charge trap flash (CTF) technology replaces the polysilicon floating gate, which is sandwiched between a blocking gate oxide above and a tunneling oxide below it, with an electrically insulating silicon nitride layer; the silicon nitride layer traps electrons. In theory, CTF is less prone to electron leakage, providing improved data retention.{{Cite news |last=Wong |first=Bill |date=15 April 2013 |title=Interview: Spansion's CTO Talks About Embedded Charge Trap NOR Flash Technology |work=Electronic Design |url=https://www.electronicdesign.com/technologies/memory/article/21796009/interview-spansions-cto-talks-about-embedded-charge-trap-nor-flash-technology |url-status=live |archive-url=https://web.archive.org/web/20231204125719/https://www.electronicdesign.com/technologies/embedded/digital-ics/memory/article/21796009/interview-spansions-cto-talks-about-embedded-charge-trap-nor-flash-technology |archive-date=4 December 2023 }}{{Cite book |last1=Ito |first1=Takashi |title=Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations |last2=Taito |first2=Yasuhiko |date=9 September 2017 |publisher=Springer Publishing |isbn=978-3-319-55306-1 |editor-last=Hidaka |editor-first=Hideto |series=Integrated Circuits and Systems |pages=209–244 |chapter=SONOS Split-Gate eFlash Memory |doi=10.1007/978-3-319-55306-1_7 }}{{Cite journal |last1=Bez |first1=Roberto |last2=Camerlenghi |first2=E. |last3=Modelli |first3=Alberto |last4=Visconti |first4=Angelo |date=April 2003 |title=Introduction to flash memory |journal=Proceedings of the IEEE |publisher=Institute of Electrical and Electronics Engineers |volume=91 |issue=4 |pages=498–502 |doi=10.1109/JPROC.2003.811702 }}{{Cite journal |last=Lee |first=Jang-Sik |date=18 October 2011 |title=Review paper: Nano-floating gate memory devices |journal=Electronic Materials Letters |publisher=Korean Institute of Metals and Materials |volume=7 |issue=3 |pages=175–183 |doi=10.1007/s13391-011-0901-5 |bibcode=2011EML.....7..175L |s2cid=110503864 }}{{Cite web |last=Aravindan |first=Avinash |date=13 November 2018 |title=Flash 101: Types of NAND Flash |url=https://www.embedded.com/flash-101-types-of-nand-flash/ |url-status=live |archive-url=https://web.archive.org/web/20231106101540/https://www.embedded.com/flash-101-types-of-nand-flash/ |archive-date=6 November 2023 |website=embedded.com }}{{Cite journal |last1=Meena |first1=Jagan Singh |last2=Sze |first2=Simon Min |last3=Chand |first3=Umesh |last4=Tseng |first4=Tseung-Yuen |date=25 September 2014 |title=Overview of emerging nonvolatile memory technologies |journal=Nanoscale Research Letters |volume=9 |issue=1 |page=526 |doi=10.1186/1556-276x-9-526 |issn=1556-276X |id=526 |doi-access=free |pmid=25278820 |pmc=4182445 |bibcode=2014NRL.....9..526M }}

Because CTF replaces the polysilicon with an electrically insulating nitride, it allows for smaller cells and higher endurance (lower degradation or wear). However, electrons can become trapped and accumulate in the nitride, leading to degradation. Leakage is exacerbated at high temperatures since electrons become more excited with increasing temperatures. CTF technology, however, still uses a tunneling oxide and blocking layer, which are the weak points of the technology, since they can still be damaged in the usual ways (the tunnel oxide can be degraded due to extremely high electric fields and the blocking layer due to Anode Hot Hole Injection (AHHI).{{Cite web |last=Sheldon |first=Robert |date=19 June 2023 |title=Charge trap technology advantages for 3D NAND flash drives |url=https://www.techtarget.com/searchstorage/tip/Charge-trap-technology-advantages-for-3D-NAND-flash-drives |url-status=live |archive-url=https://web.archive.org/web/20230809223937/https://www.techtarget.com/searchstorage/tip/Charge-trap-technology-advantages-for-3D-NAND-flash-drives |archive-date=9 August 2023 |website=SearchStorage }}{{Cite book |last1=Grossi |first1=A. |title=3D Flash Memories |last2=Zambelli |first2=C. |last3=Olivo |first3=P. |date=7 June 2016 |publisher=Springer Science+Business Media |isbn=978-94-017-7512-0 |editor-last=Micheloni |editor-first=Rino |location=Dordrecht |pages=29–62 |chapter=Reliability of 3D NAND Flash Memories |doi=10.1007/978-94-017-7512-0_2 }}

Degradation or wear of the oxides is the reason why flash memory has limited endurance. Data retention goes down (the potential for data loss increases) with increasing degradation, since the oxides lose their electrically-insulating characteristics as they degrade. The oxides must insulate against electrons to prevent them from leaking, which would cause data loss.

In 1991, NEC researchers, including N. Kodama, K. Oyama and Hiroki Shirai, described a type of flash memory with a charge-trap method.{{Cite conference |last1=Kodama |first1=N. |last2=Oyama |first2=K. |last3=Shirai |first3=H. |last4=Saitoh |first4=K. |last5=Okazawa |first5=T. |last6=Hokari |first6=Y. |date=December 1991 |title=A symmetrical side wall (SSW)-DSA cell for a 64 Mbit flash memory |conference=International Electron Devices Meeting |location=Washington, DC |publisher=IEEE |pages=303–306 |doi=10.1109/IEDM.1991.235443 |isbn=0-7803-0243-5 |issn=0163-1918 |s2cid=111203629 }} In 1998, Boaz Eitan of Saifun Semiconductors (later acquired by Spansion) patented a flash memory technology named NROM that took advantage of a charge trapping layer to replace the conventional floating gate used in conventional flash memory designs.{{cite web|last=Eitan|first=Boaz|title=US Patent 5,768,192: Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping|url=http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=5,768,192.PN.&OS=PN/5,768,192&RS=PN/5,768,192|publisher=US Patent & Trademark Office|access-date=22 May 2012|archive-date=22 February 2020|archive-url=https://web.archive.org/web/20200222215754/http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=5%2C768%2C192.PN.&OS=PN%2F5%2C768%2C192&RS=PN%2F5%2C768%2C192|url-status=dead}} In 2000, an Advanced Micro Devices (AMD) research team led by Richard M. Fastow, Egyptian engineer Khaled Z. Ahmed and Jordanian engineer Sameer Haddad (who later joined Spansion) demonstrated a charge-trapping mechanism for NOR flash memory cells.{{Cite journal |last1=Fastow |first1=Richard M. |last2=Ahmed |first2=Khaled Z. |last3=Haddad |first3=Sameer |last4=Randolph |first4=Mark |last5=Huster |first5=C. |last6=Hom |first6=P. |date=April 2000 |title=Bake induced charge gain in NOR flash cells |url=https://www.researchgate.net/publication/3253902 |journal=IEEE Electron Device Letters |volume=21 |issue=4 |pages=184–186 |bibcode=2000IEDL...21..184F |doi=10.1109/55.830976 |issn=1558-0563 |s2cid=24724751 }} CTF was later commercialized by AMD and Fujitsu in 2002.{{Cite news |last=Hruska |first=Joel |date=6 August 2013 |title=Samsung produces first 3D NAND, aims to boost densities, drive lower cost per GB |work=ExtremeTech |url=https://www.extremetech.com/computing/163221-samsung-produces-first-3d-nand-aims-to-boost-densities-drive-lower-cost-per-gb |url-status=live |access-date=4 July 2019 |archive-url=https://web.archive.org/web/20231102133725/https://www.extremetech.com/computing/163221-samsung-produces-first-3d-nand-aims-to-boost-densities-drive-lower-cost-per-gb |archive-date=2 November 2023 }} 3D V-NAND (vertical NAND) technology stacks NAND flash memory cells vertically within a chip using 3D charge trap flash (CTP) technology. 3D V-NAND technology was first announced by Toshiba in 2007, and the first device, with 24 layers, was commercialized by Samsung Electronics in 2013.

3D integrated circuit (3D IC) technology stacks integrated circuit (IC) chips vertically into a single 3D IC package. Toshiba introduced 3D IC technology to NAND flash memory in April 2007, when they debuted a 16{{nbsp}}GB eMMC compliant (product number THGAM0G7D8DBAI6, often abbreviated THGAM on consumer websites) embedded NAND flash memory package, which was manufactured with eight stacked 2{{nbsp}}GB NAND flash chips. In September 2007, Hynix Semiconductor (now SK Hynix) introduced 24-layer 3D IC technology, with a 16{{nbsp}}GB flash memory package that was manufactured with 24 stacked NAND flash chips using a wafer bonding process. Toshiba also used an eight-layer 3D IC for their 32{{nbsp}}GB THGBM flash package and in 2008. In 2010, Toshiba used a 16-layer 3D IC for their 128{{nbsp}}GB THGBM2 flash package, which was manufactured with 16 stacked 8{{nbsp}}GB chips. In the 2010s, 3D ICs came into widespread commercial use for NAND flash memory in mobile devices.

In 2016, Micron and Intel introduced a technology known as CMOS Under the Array/CMOS Under Array (CUA), Core over Periphery (COP), Periphery Under Cell (PUA), or Xtacking,{{Cite web|url=https://www.theregister.com/2018/08/06/china_aims_to_build_dramspeed_flash/|title=NAND we'll send foreign tech packing, says China of Xtacking: DRAM-speed... but light on layer-stacking|first=Chris|last=Mellor|website=www.theregister.com}} in which the control circuitry for the flash memory is placed under or above the flash memory cell array. This has allowed for an increase in the number of planes or sections a flash memory chip has, increasing from two planes to four, without increasing the area dedicated to the control or periphery circuitry. This increases the number of IO operations per flash chip or die, but it also introduces challenges when building capacitors for charge pumps used to write to the flash memory.{{Cite web|url=https://www.anandtech.com/show/16491/flash-memory-at-isscc-2021|title=2021 NAND Flash Updates from ISSCC: The Leaning Towers of TLC and QLC|first=Billy|last=Tallis|website=www.anandtech.com}}{{Cite news|url=https://www.theregister.com/2018/11/05/sk_hynix_96_layer_flash_chip/|title=What the PUC: SK Hynix next to join big boys in 96-layer 3D NAND land|first=Chris|last=Mellor|website=www.theregister.com}}{{Cite news|url=https://www.theregister.com/2016/02/22/microns_journey_into_the_depths_of_nonvolatility/|title=Look who's avoided getting chatty about XPoint again. Micron... let's get non-volatile|first=Chris|last=Mellor|website=www.theregister.com}} Some flash dies have as many as 6 planes.{{Cite web |last=Alcorn |first=Paul |date=2022-07-26 |title=Micron Takes Lead With 232-Layer NAND Flash, up to 2TB per Chip Package |url=https://www.tomshardware.com/news/micron-takes-lead-with-232-layer-nand-up-to-2tb-per-chip-package |access-date=2024-05-31 |website=Tom's Hardware |language=en}}

As of August 2017, microSD cards with a capacity up to 400 GB (400 billion bytes) were available.{{Cite press release |date=31 August 2017 |title=Western Digital Breaks Boundaries with World's Highest-Capacity microSD Card |url=https://www.sandisk.com/about/media-center/press-releases/2017/western-digital-breaks-boundaries-with-worlds-highest-capacity-microsd-card |url-status=dead |archive-url=https://web.archive.org/web/20170901035345/https://www.sandisk.com/about/media-center/press-releases/2017/western-digital-breaks-boundaries-with-worlds-highest-capacity-microsd-card |archive-date=1 September 2017 |access-date=2 September 2017 |publisher=SanDisk |place=Berlin }}{{Cite magazine |last=Bradley |first=Tony |date=31 August 2017 |title=Expand Your Mobile Storage With New 400GB microSD Card From SanDisk |url=https://www.forbes.com/sites/tonybradley/2017/08/31/expand-your-mobile-storage-with-new-400gb-microsd-card-from-sandisk |url-status=live |magazine=Forbes |archive-url=https://web.archive.org/web/20170901064146/https://www.forbes.com/sites/tonybradley/2017/08/31/expand-your-mobile-storage-with-new-400gb-microsd-card-from-sandisk/ |archive-date=1 September 2017 |access-date=2 September 2017 }} Samsung combined 3D IC chip stacking with its 3D V-NAND and TLC technologies to manufacture its 512{{nbsp}}GB KLUFG8R1EM flash memory package with eight stacked 64-layer V-NAND chips. In 2019, Samsung produced a 1024{{nbsp}}GB flash package, with eight stacked 96-layer V-NAND package and with QLC technology.

In 2025, researchers announced experimental success with a device a 400-picosecond write time.{{Cite web |last=Shaikh |first=Kaif |title=China scientists develop flash memory 10,000× faster than current tech |url=https://interestingengineering.com/innovation/china-worlds-fastest-flash-memory-device?group=test_b |access-date=2025-04-20 |website=Interesting Engineering |language=en}}

File:Flash cell structure.svg

Flash memory stores information in an array of memory cells made from floating-gate transistors. In single-level cell (SLC) devices, each cell stores only one bit of information. Multi-level cell (MLC) devices, including triple-level cell (TLC) devices, can store more than one bit per cell.

The floating gate may be conductive (typically polysilicon in most kinds of flash memory) or non-conductive (as in SONOS flash memory).{{Citation |first=Matt |last=Basinger |title=PSoC Designer Device Selection Guide |date=18 January 2007 |id=AN2209 |url=http://www.psocdeveloper.com/uploads/tx_piapappnote/an2209_03.pdf |quote=The PSoC ... utilizes a unique Flash process: SONOS |url-status=usurped |archive-url=https://web.archive.org/web/20091031121330/http://www.psocdeveloper.com/uploads/tx_piapappnote/an2209_03.pdf |archive-date=31 October 2009}}

{{Main| Floating-gate MOSFET}}

In flash memory, each memory cell resembles a standard metal–oxide–semiconductor field-effect transistor (MOSFET) except that the transistor has two gates instead of one. The cells can be seen as an electrical switch in which current flows between two terminals (source and drain) and is controlled by a floating gate (FG) and a control gate (CG). The CG is similar to the gate in other MOS transistors, but below this is the FG, which is insulated all around by an oxide layer. The FG is interposed between the CG and the MOSFET channel. Because the FG is electrically isolated by its insulating layer, electrons placed on it are trapped. When the FG is charged with electrons, this charge screens the electric field from the CG, thus increasing the threshold voltage (V_T) of the cell. This means that the V_T of the cell can be changed between the uncharged FG threshold voltage (V_T1) and the higher charged FG threshold voltage (V_T2) by changing the FG charge. In order to read a value from the cell, an intermediate voltage (V_I) between V_T1 and V_T2 is applied to the CG. If the channel conducts at V_I, the FG must be uncharged (if it were charged, there would not be conduction because V_I is less than V_T2). If the channel does not conduct at the V_I, it indicates that the FG is charged. The binary value of the cell is sensed by determining whether there is current flowing through the transistor when V_I is asserted on the CG. In a multi-level cell device, which stores more than one bit per cell, the amount of current flow is sensed (rather than simply its presence or absence), in order to determine more precisely the level of charge on the FG.

Floating gate MOSFETs are so named because there is an electrically insulating tunnel oxide layer between the floating gate and the silicon, so the gate "floats" above the silicon. The oxide keeps the electrons confined to the floating gate. Degradation or wear (and the limited endurance of floating gate Flash memory) occurs due to the extremely high electric field (10 million volts per centimeter) experienced by the oxide. Such high voltage densities can break atomic bonds over time in the relatively thin oxide, gradually degrading its electrically insulating properties and allowing electrons to be trapped in and pass through freely (leak) from the floating gate into the oxide, increasing the likelihood of data loss since the electrons (the quantity of which is used to represent different charge levels, each assigned to a different combination of bits in MLC Flash) are normally in the floating gate. This is why data retention goes down and the risk of data loss increases with increasing degradation.{{Cite web |last=Windbacher |first=T. |title=2.1.1 Flash Memory |url=https://www.iue.tuwien.ac.at/phd/windbacher/node14.html |url-status=live |archive-url=https://web.archive.org/web/20231109113308/https://www.iue.tuwien.ac.at/phd/windbacher/node14.html |archive-date=9 November 2023 |website=Engineering Gate Stacks for Field-Effect Transistors }}{{Cite web |title=Floating Gate MOS Memory |url=http://www.princeton.edu/~chouweb/newproject/research/SEM/FloatMOSMem.html |url-status=dead |archive-url=https://web.archive.org/web/20220808223834/http://www.princeton.edu/~chouweb/newproject/research/SEM/FloatMOSMem.html |archive-date=8 August 2022 |publisher=University of Minnesota }}{{Cite web |title=Flash Memory Reliability, Life & Wear |url=https://www.electronics-notes.com/articles/electronic_components/semiconductor-ic-memory/flash-wear-levelling-reliability-lifetime.php |url-status=live |archive-url=https://web.archive.org/web/20231102133652/https://www.electronics-notes.com/articles/electronic_components/semiconductor-ic-memory/flash-wear-levelling-reliability-lifetime.php |archive-date=2 November 2023 |website=Electronics Notes }} The silicon oxide in a cell degrades with every erase operation. The degradation increases the amount of negative charge in the cell over time due to trapped electrons in the oxide and negates some of the control gate voltage. Over time, this also makes erasing the cell slower; to maintain the performance and reliability of the NAND chip, the cell must be retired from use. Endurance also decreases with the number of bits in a cell. With more bits in a cell, the number of possible states (each represented by a different voltage level) in a cell increases and is more sensitive to the voltages used for programming. Voltages may be adjusted to compensate for degradation of the silicon oxide, and as the number of bits increases, the number of possible states also increases and thus the cell is less tolerant of adjustments to programming voltages, because there is less space between the voltage levels that define each state in a cell.{{Cite news |last=Vättö |first=Kristian |date=23 February 2012 |title=Understanding TLC NAND |work=AnandTech |url=https://www.anandtech.com/show/5067/understanding-tlc-nand/2 |url-status=live |archive-url=https://web.archive.org/web/20231102131132/https://www.anandtech.com/show/5067/understanding-tlc-nand/2 |archive-date=2 November 2023 }}

{{Main|Fowler–Nordheim tunneling}}

The process of moving electrons from the control gate and into the floating gate is called Fowler–Nordheim tunneling, and it fundamentally changes the characteristics of the cell by increasing the MOSFET's threshold voltage. This, in turn, changes the drain-source current that flows through the transistor for a given gate voltage, which is ultimately used to encode a binary value. The Fowler-Nordheim tunneling effect is reversible, so electrons can be added to or removed from the floating gate, processes traditionally known as writing and erasing.{{Cite web |date=17 April 2018 |title=Solid State bit density, and the Flash Memory Controller |url=https://www.hyperstone.com/en/Solid-State-bit-density-and-the-Flash-Memory-Controller-1235,12728.html |url-status=live |archive-url=https://web.archive.org/web/20230609075731/https://www.hyperstone.com/en/Solid-State-bit-density-and-the-Flash-Memory-Controller-1235,12728.html |archive-date=9 June 2023 |access-date=29 May 2018 |website=hyperstone.com }}

Despite the need for relatively high programming and erasing voltages, virtually all flash chips today require only a single supply voltage and produce the high voltages that are required using on-chip charge pumps.

Over half the energy used by a 1.8 V-NAND flash chip is lost in the charge pump itself. Since boost converters are inherently more efficient than charge pumps, researchers developing low-power SSDs have proposed returning to the dual Vcc/Vpp supply voltages used on all early flash chips, driving the high Vpp voltage for all flash chips in an SSD with a single shared external boost converter.{{Citation |first1=Tadashi |title=Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design - ISLPED '09 |last1=Yasufuku |first2=Koichi |last2=Ishida |first3=Shinji |last3=Miyamoto |first4=Hiroto |last4=Nakai |first5=Makoto |last5=Takamiya |first6=Takayasu |last6=Sakurai |first7=Ken |last7=Takeuchi |journal=IEICE Transactions on Electronics |url=http://www.computer.org/csdl/proceedings/islped/2009/8684/00/86840087-abs.html |pages=87–92 |year=2009 |volume=93 |issue=3 |url-status=live |archive-url=https://web.archive.org/web/20160305135918/https://www.computer.org/csdl/proceedings/islped/2009/8684/00/86840087-abs.html |archive-date=5 March 2016|doi=10.1145/1594233.1594253 |isbn=9781605586847 |s2cid=6055676 |url-access=subscription |bibcode=2010IEITE..93..317Y}}{{citation |first1=Rino |last1=Micheloni |first2=Alessia |last2=Marelli |first3=Kam |last3=Eshghi |url=https://books.google.com/books?id=8LS3egzcBG4C&pg=PA188 |title=Inside Solid State Drives (SSDs) |year=2012 |publisher=Springer |url-status=live |archive-url=https://web.archive.org/web/20170209234319/https://books.google.com/books?id=8LS3egzcBG4C&pg=PA188&lpg=PA188 |archive-date=9 February 2017|isbn=9789400751460 |bibcode=2013issd.book.....M }}{{citation |first1=Rino |last1=Micheloni |first2=Luca |last2=Crippa |url=https://books.google.com/books?id=vaq11vKwo_kC&pg=PA530 |title=Inside NAND Flash Memories |year=2010 |publisher=Springer |url-status=live |archive-url=https://web.archive.org/web/20170209164808/https://books.google.com/books?id=vaq11vKwo_kC&pg=PA530&lpg=PA530 |archive-date=9 February 2017|isbn=9789048194315 }} In particular, {{cite book |doi=10.1007/978-90-481-9431-5_18 |chapter=Low power 3D-integrated SSD |title=Inside NAND Flash Memories |date=2010 |last1=Takeuchi |first1=K. |pages=515–536 |isbn=978-90-481-9430-8 }}{{citation |first1=Tracey |last1=Mozel |url=https://books.google.com/books?id=XlbOf-m8fdYC&pg=RA5-PA3 |title=CMOSET Fall 2009 Circuits and Memories Track Presentation Slides |year=2009 |publisher=CMOS Emerging Technologies |url-status=live |archive-url=https://web.archive.org/web/20170209213305/https://books.google.com/books?id=XlbOf-m8fdYC&pg=RA5-PA3&lpg=RA5-PA3 |archive-date=9 February 2017|isbn=9781927500217 }}{{Cite journal |last1=Yasufuku |first1=Tadashi |last2=Ishida |first2=Koichi |last3=Miyamoto |first3=Shinji |last4=Nakai |first4=Hiroto |last5=Takamiya |first5=Makoto |last6=Sakurai |first6=Takayasu |last7=Takeuchi |first7=Ken |date=March 2010 |title=Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories |pages=317–323 |url=https://www.researchgate.net/publication/220240029 |url-status=live |journal=IEICE Transactions on Electronics |publisher=IEICE |volume=E93-C |issue=3 |doi=10.1587/transele.E93.C.317 |archive-url=https://web.archive.org/web/20160204025034/https://www.researchgate.net/publication/220240029_Inductor_and_TSV_Design_of_20-V_Boost_Converter_for_Low_Power_3D_Solid_State_Drive_with_NAND_Flash_Memories |archive-date=4 February 2016 |doi-access= |bibcode=2010IEITE..93..317Y |url-access=subscription }}{{cite web | url=https://ieeexplore.ieee.org/document/5986104 | title=4-times faster rising VPASS (10V), 15% lower power VPGM (20V), wide output voltage range voltage generator system for 4-times faster 3D-integrated solid-state drives | date=June 2011 | pages=200–201 }}{{Cite conference |last=Takeuchi |first=Ken |date=May 2010 |title=Low power 3D-integrated Solid-State Drive (SSD) with adaptive voltage generator |conference=IEEE International Memory Workshop (IMW) |location=Seoul, Korea |doi=10.1109/IMW.2010.5488397 |isbn=978-1-4244-6721-1 |issn=2159-4864 }}{{Cite journal |last1=Ishida |first1=Koichi |last2=Yasufuku |first2=Tadashi |last3=Miyamoto |first3=Shinji |last4=Nakai |first4=Hiroto |last5=Takamiya |first5=Makoto |last6=Sakurai |first6=Takayasu |last7=Takeuchi |first7=Ken |date=May 2011 |title=1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD |journal=IEEE Journal of Solid-State Circuits |publisher=Institute of Electrical and Electronics Engineers |volume=46 |issue=6 |pages=1478–1487 |doi=10.1109/JSSC.2011.2131810 |bibcode=2011IJSSC..46.1478I |s2cid=13701601 |issn=1558-173X }}

In spacecraft and other high-radiation environments, the on-chip charge pump is the first part of the flash chip to fail, although flash memories will continue to work{{snd}} in read-only mode{{snd}} at much higher radiation levels.A. H. Johnston, [http://trs-new.jpl.nasa.gov/dspace/bitstream/2014/13431/1/01-2369.pdf "Space Radiation Effects in Advanced Flash Memories"] {{webarchive|url=https://web.archive.org/web/20160304220536/http://trs-new.jpl.nasa.gov/dspace/bitstream/2014/13431/1/01-2369.pdf |date=4 March 2016 }}.

NASA Electronic Parts and Packaging Program (NEPP). 2001. "... internal transistors used for the charge pump and erase/write control have much thicker oxides because of the requirement for high voltage. This causes flash devices to be considerably more sensitive to total dose damage compared to other ULSI technologies. It also implies that write and erase functions will be the first parameters to fail from total dose. ... Flash memories will work at much higher radiation levels in the read mode. ... The charge pumps that are required to generate the high voltage for erasing and writing are usually the most sensitive circuit functions, usually failing below 10 krad(SI)."

File:NOR flash layout.svg

In NOR flash, each cell has one end connected directly to ground, and the other end connected directly to a bit line. This arrangement is called "NOR flash" because it acts like a NOR gate; when one of the word lines (connected to the cell's CG) is brought high, the corresponding storage transistor acts to pull the output bit line low. NOR flash continues to be the technology of choice for embedded applications requiring a discrete non-volatile memory device.{{citation needed|date=May 2022}} The low read latencies characteristic of NOR devices allow for both direct code execution and data storage in a single memory product.{{Cite news |last=Zitlaw |first=Cliff |date=2 May 2011 |title=The Future of NOR Flash Memory |work=Memory Designline |publisher=UBM Media |url=https://www.eetimes.com/the-future-of-nor-flash-memory/ |url-status=live |access-date=3 May 2011 |archive-url=https://web.archive.org/web/20230601001439/https://www.eetimes.com/the-future-of-nor-flash-memory/ |archive-date=1 June 2023 }}

Image:Flash-Programming.svg

File:Flash erase.svg

A single-level NOR flash cell in its default state is logically equivalent to a binary "1" value, because current will flow through the channel under application of an appropriate voltage to the control gate, so that the bitline voltage is pulled down. A NOR flash cell can be programmed, or set to a binary "0" value, by the following procedure:

• an elevated on-voltage (typically >5 V) is applied to the CG
• the channel is now turned on, so electrons can flow from the source to the drain (assuming an NMOS transistor)
• the source-drain current is sufficiently high to cause some high energy electrons to jump through the insulating layer onto the FG, via a process called hot-electron injection.

To erase a NOR flash cell (resetting it to the "1" state), a large voltage of the opposite polarity is applied between the CG and source terminal, pulling the electrons off the FG through Fowler–Nordheim tunneling (FN tunneling).{{cite book | url=https://books.google.com/books?id=44mbEAAAQBAJ&dq=nor+flash+erase&pg=PA55 | isbn=978-3-030-79827-7 | title=Springer Handbook of Semiconductor Devices | date=10 November 2022 | publisher=Springer }} This is known as Negative gate source source erase. Newer NOR memories can erase using negative gate channel erase, which biases the wordline on a NOR memory cell block and the P-well of the memory cell block to allow FN tunneling to be carried out, erasing the cell block. Older memories used source erase, in which a high voltage was applied to the source and then electrons from the FG were moved to the source.{{cite book | url=https://books.google.com/books?id=2E0r6BRo2VkC&dq=nor+flash+erase&pg=PA212 | isbn=978-90-481-9216-8 | title=CMOS Processors and Memories | date=9 August 2010 | publisher=Springer }}{{cite journal | url=https://ieeexplore.ieee.org/document/1035946 | title= High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories| date= 2002| doi=10.1109/JSSC.2002.803045 | last1= Tanzawa| first1= T.| last2= Takano| first2= Y.| last3= Watanabe| first3= K.| last4= Atsumi| first4= S.| journal= IEEE Journal of Solid-State Circuits| volume= 37| issue= 10| pages= 1318–1325| bibcode= 2002IJSSC..37.1318T}} Modern NOR flash memory chips are divided into erase segments (often called blocks or sectors). The erase operation can be performed only on a block-wise basis; all the cells in an erase segment must be erased together.{{cite book | url=https://books.google.com/books?id=abfBAAAAQBAJ&dq=nor+erase+block&pg=PA41 | isbn=978-94-007-6082-0 | title=Flash Memories: Economic Principles of Performance, Cost and Reliability Optimization | date=12 September 2013 | publisher=Springer }} Programming of NOR cells, however, generally can be performed one byte or word at a time.

{{clear}}

File:Nand flash structure.svg

NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: several transistors are connected in series, and the bit line is pulled low only if all the word lines are pulled high (above the transistors' V_T). These groups are then connected via some additional transistors to a NOR-style bit line array in the same way that single transistors are linked in NOR flash.

Compared to NOR flash, replacing single transistors with serial-linked groups adds an extra level of addressing. Whereas NOR flash might address memory by page then word, NAND flash might address it by page, word and bit. Bit-level addressing suits bit-serial applications (such as hard disk emulation), which access only one bit at a time. {{nowrap|Execute-in-place}} applications, on the other hand, require every bit in a word to be accessed simultaneously. This requires word-level addressing. In any case, both bit and word addressing modes are possible with either NOR or NAND flash.

To read data, first the desired group is selected (in the same way that a single transistor is selected from a NOR array). Next, most of the word lines are pulled up above V_T2, while one of them is pulled up to V_I. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed.

Despite the additional transistors, the reduction in ground wires and bit lines allows a denser layout and greater storage capacity per chip. (The ground wires and bit lines are actually much wider than the lines in the diagrams.) In addition, NAND flash is typically permitted to contain a certain number of faults (NOR flash, as is used for a BIOS ROM, is expected to be fault-free). Manufacturers try to maximize the amount of usable storage by shrinking the size of the transistors or cells, however the industry can avoid this and achieve higher storage densities per die by using 3D NAND, which stacks cells on top of each other.

NAND flash cells are read by analysing their response to various voltages.{{Cite news |last=Shimpi |first=Anand Lal |date=30 September 2011 |title=The Intel SSD 710 (200GB) Review |work=AnandTech |url=https://www.anandtech.com/show/4902/intel-ssd-710-200gb-review |url-status=live |archive-url=https://web.archive.org/web/20231102131301/https://www.anandtech.com/show/4902/intel-ssd-710-200gb-review |archive-date=2 November 2023 }}

NAND flash uses tunnel injection for writing and tunnel release for erasing. NAND flash memory forms the core of the removable USB storage devices known as USB flash drives, as well as most memory card formats and solid-state drives available today.

The hierarchical structure of NAND flash starts at a cell level which establishes strings, then pages, blocks, planes and ultimately a die. A string is a series of connected NAND cells in which the source of one cell is connected to the drain of the next one. Depending on the NAND technology, a string typically consists of 32 to 128 NAND cells. Strings are organised into pages which are then organised into blocks in which each string is connected to a separate line called a bitline. All cells with the same position in the string are connected through the control gates by a wordline. A plane contains a certain number of blocks that are connected through the same bitline. A flash die consists of one or more planes, and the peripheral circuitry that is needed to perform all the read, write, and erase operations.

The architecture of NAND flash means that data can be read and programmed (written) in pages, typically between 4 KiB and 16 KiB in size, but can only be erased at the level of entire blocks consisting of multiple pages. When a block is erased, all the cells are logically set to 1. Data can only be programmed in one pass to a page in a block that was erased. The programming process is set one or more cells from 1 to 0. Any cells that have been set to 0 by programming can only be reset to 1 by erasing the entire block. This means that before new data can be programmed into a page that already contains data, the current contents of the page plus the new data must all be copied to a new, erased page. If a suitable erased page is available, the data can be written to it immediately. If no erased page is available, a block must be erased before copying the data to a page in that block. The old page is then marked as invalid and is available for erasing and reuse.{{Cite web |date=7 June 2018 |title=NAND Flash Controllers - The key to endurance and reliability |url=https://www.hyperstone.com/en/NAND-Flash-controllers-The-key-to-endurance-and-reliability-1256,12728.html |url-status=live |archive-url=https://web.archive.org/web/20230605095907/https://www.hyperstone.com/en/NAND-Flash-controllers-The-key-to-endurance-and-reliability-1256,12728.html |archive-date=5 June 2023 |access-date=1 June 2022 |work=hyperstone.com }} This is different from operating system LBA view, for example, if operating system writes 1100 0011 to the flash storage device (such as SSD), the data actually written to the flash memory may be 0011 1100.

File:NAND_Flash_Bit_Cost_from_2D_to_3D.png

Vertical NAND (V-NAND) or 3D NAND memory stacks memory cells vertically and uses a charge trap flash architecture. The vertical layers allow larger areal bit densities without requiring smaller individual cells.{{cite web |url=http://www.gizmag.com/samsung-v-nand-flash-chip-ssd/28655 |title=Samsung moves into mass production of 3D flash memory |publisher=Gizmag.com |access-date=2013-08-27 |url-status=live |archive-url=https://web.archive.org/web/20130827091835/http://www.gizmag.com/samsung-v-nand-flash-chip-ssd/28655/ |archive-date=27 August 2013|date=27 August 2013 }} It is also sold under the trademark BiCS Flash, which is a trademark of Kioxia Corporation (formerly Toshiba Memory Corporation). 3D NAND was first announced by Toshiba in 2007.{{Cite news |last=Melanson |first=Donald |date=12 June 2007 |title=Toshiba announces new "3D" NAND flash technology |work=Engadget |url=https://www.engadget.com/2007/06/12/toshiba-announces-new-3d-nand-flash-technology/ |url-status=live |access-date=10 July 2019 |archive-url=https://web.archive.org/web/20221217224115/https://www.engadget.com/2007-06-12-toshiba-announces-new-3d-nand-flash-technology.html |archive-date=17 December 2022 }} V-NAND was first commercially manufactured by Samsung Electronics in 2013.{{Cite press release |date=13 August 2013 |title=Samsung Introduces World's First 3D V-NAND Based SSD for Enterprise Applications |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-introduces-worlds-first-3d-v-nand-based-ssd-for-enterprise-applications/ |url-status=dead |archive-url=https://web.archive.org/web/20190414192036/https://www.samsung.com/semiconductor/insights/news-events/samsung-introduces-worlds-first-3d-v-nand-based-ssd-for-enterprise-applications/ |archive-date=14 April 2019 |publisher=Samsung }}{{Cite news |last=Clarke |first=Peter |date=8 August 2013 |title=Samsung Confirms 24 Layers in 3D NAND |work=EE Times |url=https://www.eetimes.com/samsung-confirms-24-layers-in-3d-nand/ |url-status=live |archive-url=https://web.archive.org/web/20200219151255/https://www.eetimes.com/samsung-confirms-24-layers-in-3d-nand/ |archive-date=19 February 2020 }}{{Cite press release |date=9 October 2014 |title=Samsung Electronics Starts Mass Production of Industry First 3-bit 3D V-NAND Flash Memory |url=https://news.samsung.com/global/samsung-electronics-starts-mass-production-of-industry-first-3-bit-3d-v-nand-flash-memory |url-status=live |archive-url=https://web.archive.org/web/20230330135736/https://news.samsung.com/global/samsung-electronics-starts-mass-production-of-industry-first-3-bit-3d-v-nand-flash-memory |archive-date=30 March 2023 |publisher=Samsung }}{{Cite web |date=September 2014 |title=Samsung V-NAND technology |url=http://www.samsung.com/us/business/oem-solutions/pdfs/V-NAND_technology_WP.pdf |url-status=dead |archive-url=https://web.archive.org/web/20160327194431/http://www.samsung.com/us/business/oem-solutions/pdfs/V-NAND_technology_WP.pdf |archive-date=27 March 2016 |access-date=27 March 2016 |publisher=Samsung }}

V-NAND uses a charge trap flash geometry (which was commercially introduced in 2002 by AMD and Fujitsu) that stores charge on an embedded silicon nitride film. Such a film is more robust against point defects and can be made thicker to hold larger numbers of electrons. V-NAND wraps a planar charge trap cell into a cylindrical form. As of 2020, 3D NAND flash memories by Micron and Intel instead use floating gates, however, Micron 128 layer and above 3D NAND memories use a conventional charge trap structure, due to the dissolution of the partnership between Micron and Intel. Charge trap 3D NAND flash is thinner than floating gate 3D NAND. In floating gate 3D NAND, the memory cells are completely separated from one another, whereas in charge trap 3D NAND, vertical groups of memory cells share the same silicon nitride material.{{Cite news |last=Tallis |first=Billy |date=9 November 2020 |title=Micron Announces 176-layer 3D NAND |work=AnandTech |url=https://www.anandtech.com/show/16230/micron-announces-176layer-3d-nand |url-status=live |archive-url=https://web.archive.org/web/20231102133017/https://www.anandtech.com/show/16230/micron-announces-176layer-3d-nand |archive-date=2 November 2023 }}

An individual memory cell is made up of one planar polysilicon layer containing a hole filled by multiple concentric vertical cylinders. The hole's polysilicon surface acts as the gate electrode. The outermost silicon dioxide cylinder acts as the gate dielectric, enclosing a silicon nitride cylinder that stores charge, in turn enclosing a silicon dioxide cylinder as the tunnel dielectric that surrounds a central rod of conducting polysilicon which acts as the conducting channel.

Memory cells in different vertical layers do not interfere with each other, as the charges cannot move vertically through the silicon nitride storage medium, and the electric fields associated with the gates are closely confined within each layer. The vertical collection is electrically identical to the serial-linked groups in which conventional NAND flash memory is configured. There is also string stacking, which builds several 3D NAND memory arrays or "plugs"{{Cite web|url=https://blocksandfiles.com/2023/08/18/samsung-has-300-layer-nand-coming-with-430-layers-after-that/|title=Samsung has 300-layer NAND coming, with 430 layers after that – report|first=Chris|last=Mellor|date=18 August 2023}} separately, but stacked together to create a product with a higher number of 3D NAND layers on a single die. Often, two or 3 arrays are stacked. The misalignment between plugs is in the order of 30 to 10nm.{{Cite book|chapter-url=https://ieeexplore.ieee.org/document/9282426|title=2020 China Semiconductor Technology International Conference (CSTIC)|doi=10.1109/CSTIC49141.2020.9282426 |chapter=Manufacturing Challenges and Cost Evaluation of New Generation 3D Memories |date=2020 |last1=Dube |first1=Belinda Langelihle |pages=1–3 |isbn=978-1-7281-6558-5 |s2cid=229376195 }}{{Cite web |last=Choe |first=Jeongdong |date=2019 |title=Comparison of Current 3D NAND Chip & Cell Architecture |url=https://files.futurememorystorage.com/proceedings/2019/08-07-Wednesday/20190807_FTEC-202-1_Choe.pdf |pages=21, 24}}

Growth of a group of V-NAND cells begins with an alternating stack of conducting (doped) polysilicon layers and insulating silicon dioxide layers.

The next step is to form a cylindrical hole through these layers. In practice, a 128 Gbit V-NAND chip with 24 layers of memory cells requires about 2.9 billion such holes. Next, the hole's inner surface receives multiple coatings, first silicon dioxide, then silicon nitride, then a second layer of silicon dioxide. Finally, the hole is filled with conducting (doped) polysilicon.

{{As of|2013|post=,}} V-NAND flash architecture allows read and write operations twice as fast as conventional NAND and can last up to 10 times as long, while consuming 50 percent less power. They offer comparable physical bit density using 10-nm lithography but may be able to increase bit density by up to two orders of magnitude, given V-NAND's use of up to several hundred layers. As of 2020, V-NAND chips with 160 layers are under development by Samsung.{{Cite news |last=Potoroaca |first=Adrian |date=20 April 2020 |title=Samsung said to be developing industry's first 160-layer NAND flash memory chip |work=TechSpot |url=https://www.techspot.com/news/84905-samsung-developing-industry-first-160-layer-nand-flash.html |url-status=live |archive-url=https://web.archive.org/web/20231102130037/https://www.techspot.com/news/84905-samsung-developing-industry-first-160-layer-nand-flash.html |archive-date=2 November 2023 }} As the number of layers increases, the capacity and endurance of flash memory may be increased.

File:3D NAND minimum cost example.png

The wafer cost of a 3D NAND is comparable with scaled down (32 nm or less) planar NAND flash.{{cite web|url=https://www.linkedin.com/pulse/toshibas-cost-model-3d-nand-frederick-chen|title=Toshiba's Cost Model for 3D NAND|website=www.linkedin.com}} However, with planar NAND scaling stopping at 16 nm, the cost per bit reduction can continue by 3D NAND starting with 16 layers. However, due to the non-vertical sidewall of the hole etched through the layers; even a slight deviation leads to a minimum bit cost, i.e., minimum equivalent design rule (or maximum density), for a given number of layers; this minimum bit cost layer number decreases for smaller hole diameter.{{cite web |title=Calculating the Maximum Density and Equivalent 2D Design Rule of 3D NAND Flash |url=https://www.linkedin.com/pulse/calculating-maximum-density-equivalent-2d-design-rule-frederick-chen |website=linkedin.com |access-date=1 June 2022}}; {{cite web |url=https://semiwiki.com/lithography/296121-calculating-the-maximum-density-and-equivalent-2d-design-rule-of-3d-nand-flash/ |title=Calculating the Maximum Density and Equivalent 2D Design Rule of 3D NAND Flash |website=semwiki.com |access-date=1 June 2022}}

One limitation of flash memory is that it can be erased only a block at a time. This generally sets all bits in the block to 1. Starting with a freshly erased block, any location within that block can be programmed. However, once a bit has been set to 0, only by erasing the entire block can it be changed back to 1. In other words, flash memory (specifically NOR flash) offers random-access read and programming operations but does not offer arbitrary random-access rewrite or erase operations. A location can, however, be rewritten as long as the new value's 0 bits are a superset of the over-written values. For example, a nibble value may be erased to 1111, then written as 1110. Successive writes to that nibble can change it to 1010, then 0010, and finally 0000. Essentially, erasure sets all bits to 1, and programming can only clear bits to 0.

[http://ww1.microchip.com/downloads/en/AppNotes/doc2546.pdf "AVR105: Power Efficient High Endurance Parameter Storage in Flash Memory"].

p. 3

Some file systems designed for flash devices make use of this rewrite capability, for example YAFFS1, to represent sector metadata. Other flash file systems, such as YAFFS2, never make use of this "rewrite" capability – they do a lot of extra work to meet a "write once rule".

Although data structures in flash memory cannot be updated in completely general ways, this allows members to be "removed" by marking them as invalid. This technique may need to be modified for multi-level cell devices, where one memory cell holds more than one bit.

Common flash devices such as USB flash drives and memory cards provide only a block-level interface, or flash translation layer (FTL), which writes to a different cell each time to wear-level the device. This prevents incremental writing within a block; however, it does help the device from being prematurely worn out by intensive write patterns.

File:Micron_45_nm_NOR_Flash_Data_Retention.png

Data stored on flash cells is steadily lost due to electron detrapping{{Definition needed|data detrapping is not a familiar concept to the average wikipedia reader.|date=December 2022}}. The rate of loss increases exponentially as the absolute temperature increases. For example: For a 45 nm NOR flash, at 1000 hours, the threshold voltage (Vt) loss at 25°C is about half that at 90°C.{{cite book

| last1 = Calabrese |first1 =Marcello|title =Proceedings of 2013 International Conference on IC Design & Technology (ICICDT)|chapter =Accelerated reliability testing of flash memory: Accuracy and issues on a 45nm NOR technology| date = May 2013 | chapter-url = https://ieeexplore.ieee.org/document/6563298 |pages =37–40| doi = 10.1109/ICICDT.2013.6563298 |isbn =978-1-4673-4743-3|s2cid =37127243| access-date = June 22, 2022}}

Another limitation is that flash memory has a finite number of program–erase cycles (typically written as P/E cycles).{{Cite tech report |url=https://www.snia.org/sites/default/files/SSSI_NAND_Reliability_White_Paper_0.pdf |title=NAND Flash Solid State Storage for the Enterprise, An In-depth Look at Reliability |last=Thatcher |first=Jonathan |last2=Coughlin |first2=Tom |date=April 2009 |publisher=Solid State Storage Initiative (SSSI) of the Storage Network Industry Association (SNIA) |last3=Handy |first3=Jim |last4=Ekker |first4=Neal |access-date=6 December 2011 |archive-url=https://web.archive.org/web/20111014033413/http://snia.org/sites/default/files/SSSI_NAND_Reliability_White_Paper_0.pdf |archive-date=14 October 2011 |url-status=live }}{{Cite web |date=February 2022 |title=Difference between SLC, MLC, TLC and 3D NAND in USB flash drives, SSDs and memory cards |url=https://www.kingston.com/en/blog/pc-performance/difference-between-slc-mlc-tlc-3d-nand |url-status=live |archive-url=https://web.archive.org/web/20231128154805/https://www.kingston.com/en/blog/pc-performance/difference-between-slc-mlc-tlc-3d-nand |archive-date=28 November 2023 |publisher=Kingston Technology }} Micron Technology and Sun Microsystems announced an SLC NAND flash memory chip rated for 1,000,000 P/E cycles on 17 December 2008.{{Cite press release |last=Bordner |first=Kirstin |date=17 December 2008 |title=Micron Collaborates with Sun Microsystems to Extend Lifespan of Flash-Based Storage, Achieves One Million Write Cycles |url=https://investors.micron.com/news-releases/news-release-details/micron-collaborates-sun-microsystems-extend-lifespan-flash-based |url-status=live |archive-url=https://web.archive.org/web/20220320082948/https://investors.micron.com/news-releases/news-release-details/micron-collaborates-sun-microsystems-extend-lifespan-flash-based |archive-date=20 March 2022 |publisher=Micron Technology |place=Boise, Idaho }}

The guaranteed cycle count may apply only to block zero (as is the case with TSOP NAND devices), or to all blocks (as in NOR). This effect is mitigated in some chip firmware or file system drivers by counting the writes and dynamically remapping blocks in order to spread write operations between sectors; this technique is called wear leveling. Another approach is to perform write verification and remapping to spare sectors in case of write failure, a technique called bad block management (BBM). For portable consumer devices, these wear out management techniques typically extend the life of the flash memory beyond the life of the device itself, and some data loss may be acceptable in these applications. For high-reliability data storage, however, it is not advisable to use flash memory that would have to go through a large number of programming cycles. This limitation also exists for "read-only" applications such as thin clients and routers, which are programmed only once or at most a few times during their lifetimes, due to read disturb (see below).

In December 2012, Taiwanese engineers from Macronix revealed their intention to announce at the 2012 IEEE International Electron Devices Meeting that they had figured out how to improve NAND flash storage read/write cycles from 10,000 to 100 million cycles using a "self-healing" process that used a flash chip with "onboard heaters that could anneal small groups of memory cells."{{Cite news |last=Owano |first=Nancy |date=2 December 2012 |title=Taiwan engineers defeat limits of flash memory |work=phys.org |url=https://phys.org/news/2012-12-taiwan-defeat-limits-memory.html |url-status=live |archive-url=https://web.archive.org/web/20160209010327/http://phys.org/news/2012-12-taiwan-defeat-limits-memory.html |archive-date=9 February 2016 }} The built-in thermal annealing was to replace the usual erase cycle with a local high temperature process that not only erased the stored charge, but also repaired the electron-induced stress in the chip, giving write cycles of at least 100 million.{{Cite news |last=Sharwood |first=Simon |date=3 December 2012 |title=Flash memory made immortal by fiery heat |work=The Register |url=https://www.theregister.co.uk/2012/12/03/macronix_thermal_annealing_extends_life_of_flash_memory/ |url-status=live |archive-url=https://web.archive.org/web/20170913183926/https://www.theregister.co.uk/2012/12/03/macronix_thermal_annealing_extends_life_of_flash_memory/ |archive-date=13 September 2017 }} The result was to be a chip that could be erased and rewritten over and over, even when it should theoretically break down. As promising as Macronix's breakthrough might have been for the mobile industry, however, there were no plans for a commercial product featuring this capability to be released any time in the near future.{{Cite news |last=Wong |first=Raymond |date=4 December 2012 |title=Flash memory breakthrough could lead to even more reliable data storage |work=Yahoo! News |url=https://news.yahoo.com/flash-memory-breakthrough-could-lead-even-more-reliable-124049340.html |url-status=live |archive-url=https://web.archive.org/web/20231102140438/https://news.yahoo.com/flash-memory-breakthrough-could-lead-even-more-reliable-124049340.html |archive-date=2 November 2023 }}

The method used to read NAND flash memory can cause nearby cells in the same memory block to change over time (become programmed). This is known as read disturb. The threshold number of reads is generally in the hundreds of thousands of reads between intervening erase operations. If reading continually from one cell, that cell will not fail but rather one of the surrounding cells will on a subsequent read. To avoid the read disturb problem the flash controller will typically count the total number of reads to a block since the last erase. When the count exceeds a target limit, the affected block is copied over to a new block, erased, then released to the block pool. The original block is as good as new after the erase. If the flash controller does not intervene in time, however, a read disturb error will occur with possible data loss if the errors are too numerous to correct with an error-correcting code.{{Cite web |date=April 2010 |title=NAND Flash Design and Use Considerations Introduction |url=https://media-www.micron.com/-/media/client/global/documents/products/technical-note/nand-flash/tn2917.pdf |url-status=live |archive-url=https://web.archive.org/web/20220303140013/https://media-www.micron.com/-/media/client/global/documents/products/technical-note/nand-flash/tn2917.pdf |archive-date=3 March 2022 |access-date=29 July 2011 |publisher=Micron Technology |id=TN-29-17 }}{{cite web |title=Technology For Managing NAND Flash |last=Kawamatus |first=Tatsuya |publisher=Hagiwara sys-com co., LTD |access-date=15 May 2018 |url=http://read.pudn.com/downloads151/ebook/654250/0808002.pdf |archive-url=https://web.archive.org/web/20180515164812/http://read.pudn.com/downloads151/ebook/654250/0808002.pdf |archive-date=2018-05-15 |url-status=dead }}{{Cite conference |date=August 2007 |title=The Inconvenient Truths of NAND Flash Memory |url=https://www.dslreports.com/r0/download/1507743~59e7b9dda2c0e0a0f7ff119a7611c641/flash_mem_summit_jcooke_inconvenient_truths_nand.pdf |conference=Flash Memory Summit 2007 |publisher=Micron Technology |archive-url=https://web.archive.org/web/20180215023326/http://www.dslreports.com/r0/download/1507743~59e7b9dda2c0e0a0f7ff119a7611c641/flash_mem_summit_jcooke_inconvenient_truths_nand.pdf |archive-date=15 February 2018 |last1=Cooke |url-status=live |first1=Jim }}

Most flash ICs come in ball grid array (BGA) packages, and even the ones that do not are often mounted on a PCB next to other BGA packages. After PCB Assembly, boards with BGA packages are often X-rayed to see if the balls are making proper connections to the proper pad, or if the BGA needs rework. These X-rays can erase programmed bits in a flash chip (convert programmed "0" bits into erased "1" bits). Erased bits ("1" bits) are not affected by X-rays.

Richard Blish.

[http://www.spansion.com/Support/Application%20Notes/Dose_Minimization_Xray_Inspect_AN.pdf "Dose Minimization During X-ray Inspection of Surface-Mounted Flash ICs"] {{webarchive|url=https://web.archive.org/web/20160220204227/http://www.spansion.com/Support/Application%20Notes/Dose_Minimization_Xray_Inspect_AN.pdf |date=20 February 2016 }}.

p. 1.

Richard Blish.

[http://www.spansion.com/Support/Application%20Notes/X-ray_inspection_on_flash_AN.pdf "Impact of X-Ray Inspection on Spansion Flash Memory"] {{webarchive|url=https://web.archive.org/web/20160304044211/http://www.spansion.com/Support/Application%20Notes/X-ray_inspection_on_flash_AN.pdf |date=4 March 2016 }}

Some manufacturers are now making X-ray proof SD{{cite web |url= https://www.sandisk.com/home/memory-cards/sd-cards/extremepro-sd-uhs-i |title= SanDisk Extreme PRO SDHC/SDXC UHS-I Memory Card |access-date= 2016-02-03 |url-status= live |archive-url= https://web.archive.org/web/20160127214859/https://www.sandisk.com/home/memory-cards/sd-cards/extremepro-sd-uhs-i |archive-date= 27 January 2016}} and USB{{cite web |url= http://www.samsung.com/us/computer/memory-storage-accessories/MUF-32BB/AM |title= Samsung 32GB USB 3.0 Flash Drive FIT MUF-32BB/AM |access-date= 2016-02-03 |url-status= live |archive-url= https://web.archive.org/web/20160203145010/http://www.samsung.com/us/computer/memory-storage-accessories/MUF-32BB/AM |archive-date= 3 February 2016}} memory devices.

The low-level interface to flash memory chips differs from those of other memory types such as DRAM, ROM, and EEPROM, which support bit-alterability (both zero to one and one to zero) and random access via externally accessible address buses.

NOR memory has an external address bus for reading and programming. For NOR memory, reading and programming are random-access, and unlocking and erasing are block-wise. For NAND memory, reading and programming are page-wise, and unlocking and erasing are block-wise.

File:IPhone 3G teardown - Intel 3050M0Y0CE -3303.jpg

Reading from NOR flash is similar to reading from random-access memory, provided the address and data bus are mapped correctly. Because of this, most microprocessors can use NOR flash memory as execute in place (XIP) memory,{{cite book | url=https://books.google.com/books?id=vaq11vKwo_kC&dq=nand+flash+xip&pg=PA12 | title=Inside NAND Flash Memories | isbn=978-90-481-9431-5 | last1=Micheloni | first1=Rino | last2=Crippa | first2=Luca | last3=Marelli | first3=Alessia | date=27 July 2010 | publisher=Springer }} meaning that programs stored in NOR flash can be executed directly from the NOR flash without needing to be copied into RAM first. NOR flash may be programmed in a random-access manner similar to reading. Programming changes bits from a logical one to a zero. Bits that are already zero are left unchanged. Erasure must happen a block at a time, and resets all the bits in the erased block back to one. Typical block sizes are 64, 128, or 256 KiB.

Bad block management is a relatively new feature in NOR chips. In older NOR devices not supporting bad block management, the software or device driver controlling the memory chip must correct for blocks that wear out, or the device will cease to work reliably.

The specific commands used to lock, unlock, program, or erase NOR memories differ for each manufacturer. To avoid needing unique driver software for every device made, special Common Flash Memory Interface (CFI) commands allow the device to identify itself and its critical operating parameters.

Besides its use as random-access ROM, NOR flash can also be used as a storage device, by taking advantage of random-access programming. Some devices offer read-while-write functionality so that code continues to execute even while a program or erase operation is occurring in the background. For sequential data writes, NOR flash chips typically have slow write speeds, compared with NAND flash.

Typical NOR flash does not need an error correcting code.

Spansion.

[http://www.spansion.com/Support/Application%20Notes/Types_of_ECC_Used_on_Flash_AN.pdf "What Types of ECC Should Be Used on Flash Memory?"] {{webarchive|url=https://web.archive.org/web/20160304044226/http://www.spansion.com/Support/Application%20Notes/Types_of_ECC_Used_on_Flash_AN.pdf |date=4 March 2016 }}.

2011.

===NAND memories===

NAND flash architecture was introduced by Toshiba in 1989. These memories are accessed much like block devices, such as hard disks. Each block consists of a number of pages. The pages are typically 512,

{{Cite news |last1=Kim |first1=Jesung |last2=Kim |first2=John Min |last3=Noh |first3=Sam H. |last4=Min |first4=Sang Lyul |last5=Cho |first5=Yookun |date=May 2002 |title=A Space-Efficient Flash Translation Layer for CompactFlash Systems |periodical=Proceedings of the IEEE |volume=48 |issue=2 |pages=366–375 |doi=10.1109/TCE.2002.1010143 }} 2,048, or 4,096 bytes in size. Associated with each page are a few bytes (typically 1/32 of the data size) that can be used for storage of an error correcting code (ECC) checksum.

Typical block sizes include:

• 32 pages of 512+16 bytes each for a block size (effective) of 16 KiB
• 64 pages of 2,048+64 bytes each for a block size of 128 KiB{{Cite web |title=Small-Block vs. Large-Block NAND flash Devices |url=https://www.micron.com/support/~/media/74C3F8B1250D4935898DB7FE79EB56E7.ashx |url-status=live |archive-url=https://web.archive.org/web/20231029033047/http://www.micron.com/support/~/media/74C3F8B1250D4935898DB7FE79EB56E7.ashx |archive-date=29 October 2023 |type=PDF |id=TN-29-07 }}
• 64 pages of 4,096+128 bytes each for a block size of 256 KiB{{Cite web |date=11 August 2009 |title=LPC313x NAND flash data and bad block management |url=https://www.nxp.com/docs/en/application-note/AN10860.pdf |url-status=live |archive-url=https://web.archive.org/web/20231208071652/https://www.nxp.com/docs/en/application-note/AN10860.pdf |archive-date=8 December 2023 |publisher=NXP Semiconductors |id=AN10860 }}
• 128 pages of 4,096+128 bytes each for a block size of 512 KiB.

Modern NAND flash may have erase block size between 1 MiB to 128 MiB. While reading and programming is performed on a page basis, erasure can only be performed on a block basis.{{cite web |url=https://www.snia.org/sites/default/education/tutorials/2009/spring/solid/JonathanThatcher_NandFlash_SSS_PerformanceV10-nc.pdf |title=NAND Flash Solid State Storage Performance and Capability – an In-depth Look |last=Thatcher |first=Jonathan |date=18 August 2009 |publisher=SNIA |access-date=2012-08-28 |url-status=live |archive-url=https://web.archive.org/web/20120907062956/http://www.snia.org/sites/default/education/tutorials/2009/spring/solid/JonathanThatcher_NandFlash_SSS_PerformanceV10-nc.pdf |archive-date=7 September 2012}} Because change a cell from 0 to 1 needs to erase entire block, not just modify some pages, so modify the data of a block may need a read-erase-write process, and the new data is actually moved to another block. In addition, on a NVM Express Zoned Namespaces SSD, it usually uses flash block size as the zone size.

NAND devices also require bad block management by the device driver software or by the flash memory controller chip. Some SD cards, for example, include controller circuitry to perform bad block management and wear leveling. When a logical block is accessed by high-level software, it is mapped to a physical block by the device driver or controller. A number of blocks on the flash chip may be set aside for storing mapping tables to deal with bad blocks, or the system may simply check each block at power-up to create a bad block map in RAM. The overall memory capacity gradually shrinks as more blocks are marked as bad.

NAND relies on ECC to compensate for bits that may spontaneously fail during normal device operation. A typical ECC will correct a one-bit error in each 2048 bits (256 bytes) using 22 bits of ECC, or a one-bit error in each 4096 bits (512 bytes) using 24 bits of ECC.{{cite web |url=http://www.elnec.com/sw/samsung_ecc_algorithm_for_256b.pdf |title=Samsung ECC algorithm |access-date=15 August 2008 |publisher=Samsung |date=June 2008 |url-status=live |archive-url=https://web.archive.org/web/20081012043739/http://www.elnec.com/sw/samsung_ecc_algorithm_for_256b.pdf |archive-date=12 October 2008}} If the ECC cannot correct the error during read, it may still detect the error. When doing erase or program operations, the device can detect blocks that fail to program or erase and mark them bad. The data is then written to a different, good block, and the bad block map is updated.

Hamming codes are the most commonly used ECC for SLC NAND flash. Reed–Solomon codes and BCH codes (Bose–Chaudhuri–Hocquenghem codes) are commonly used ECC for MLC NAND flash. Some MLC NAND flash chips internally generate the appropriate BCH error correction codes.

Most NAND devices are shipped from the factory with some bad blocks. These are typically marked according to a specified bad block marking strategy. By allowing some bad blocks, manufacturers achieve far higher yields than would be possible if all blocks had to be verified to be good. This significantly reduces NAND flash costs and only slightly decreases the storage capacity of the parts.

When executing software from NAND memories, virtual memory strategies are often used: memory contents must first be paged or copied into memory-mapped RAM and executed there (leading to the common combination of NAND + RAM). A memory management unit (MMU) in the system is helpful, but this can also be accomplished with overlays. For this reason, some systems will use a combination of NOR and NAND memories, where a smaller NOR memory is used as software ROM and a larger NAND memory is partitioned with a file system for use as a non-volatile data storage area.

NAND sacrifices the random-access and execute-in-place advantages of NOR. NAND is best suited to systems requiring high capacity data storage. It offers higher densities, larger capacities, and lower cost. It has faster erases, sequential writes, and sequential reads.

{{Further|topic=the NAND flash memory or SSD operation|Copyback}}

A group called the Open NAND Flash Interface Working Group (ONFI) has developed a standardized low-level interface for NAND flash chips. This allows interoperability between conforming NAND devices from different vendors. The ONFI specification version 1.0{{cite web |url=http://onfi.org/wp-content/uploads/2009/02/onfi_1_0_gold.pdf |title=Open NAND Flash Interface Specification |publisher=Open NAND Flash Interface |date=28 December 2006 |access-date=31 July 2010 |url-status=dead |archive-url=https://web.archive.org/web/20110727145313/http://onfi.org/wp-content/uploads/2009/02/onfi_1_0_gold.pdf |archive-date=27 July 2011}} was released on 28 December 2006. It specifies:

• A standard physical interface (pinout) for NAND flash in TSOP-48, WSOP-48, LGA-52, and BGA-63 packages
• A standard command set for reading, writing, and erasing NAND flash chips
• A mechanism for self-identification (comparable to the serial presence detection feature of SDRAM memory modules)

The ONFI group is supported by major NAND flash manufacturers, including Hynix, Intel, Micron Technology, and Numonyx, as well as by major manufacturers of devices incorporating NAND flash chips.A list of ONFi members is available at {{cite web |url=http://onfi.org/membership/ |title=Membership - ONFi |access-date=2009-09-21 |url-status=live |archive-url=https://web.archive.org/web/20090829141114/http://onfi.org/membership/ |archive-date=29 August 2009}}

Two major flash device manufacturers, Toshiba and Samsung, have chosen to use an interface of their own design known as Toggle Mode (and now Toggle). This interface isn't pin-to-pin compatible with the ONFI specification. The result is that a product designed for one vendor's devices may not be able to use another vendor's devices.{{Cite press release |date=11 August 2010 |title=Toshiba Introduces Double Data Rate Toggle Mode NAND in MLC And SLC Configurations |url=http://www.toshiba.com/taec/news/press_releases/2010/memy_10_599.jsp |url-status=dead |archive-url=https://web.archive.org/web/20151225111800/http://www.toshiba.com/taec/news/press_releases/2010/memy_10_599.jsp |archive-date=25 December 2015 |publisher=Toshiba |place=Irvine, Calif. }}

A group of vendors, including Intel, Dell, and Microsoft, formed a Non-Volatile Memory Host Controller Interface (NVMHCI) Working Group.{{Cite press release |date=30 May 2007 |title=Dell, Intel And Microsoft Join Forces To Increase Adoption of NAND-Based Flash Memory in PC Platforms |url=https://news.microsoft.com/2007/05/30/dell-intel-and-microsoft-join-forces-to-increase-adoption-of-nand-based-flash-memory-in-pc-platforms/ |url-status=live |archive-url=https://web.archive.org/web/20230603210924/https://news.microsoft.com/2007/05/30/dell-intel-and-microsoft-join-forces-to-increase-adoption-of-nand-based-flash-memory-in-pc-platforms/ |archive-date=3 June 2023 |access-date=12 August 2014 |publisher=Microsoft |location=Redmond, Wash }} The goal of the group is to provide standard software and hardware programming interfaces for nonvolatile memory subsystems, including the "flash cache" device connected to the PCI Express bus.

NOR and NAND flash differ in two important ways:

• The connections of the individual memory cells are different.{{Cite book|url=https://books.google.com/books?id=vaq11vKwo_kC&dq=nor+flash+nand+flash&pg=PA3|title=Inside NAND Flash Memories|first1=Rino|last1=Micheloni|first2=Luca|last2=Crippa|first3=Alessia|last3=Marelli|date=27 July 2010|publisher=Springer Science & Business Media|isbn=9789048194315 |via=Google Books}}
• The interface provided for reading and writing the memory is different; NOR allows random access{{cite book | url=https://books.google.com/books?id=abfBAAAAQBAJ&dq=nor+random+access&pg=PA35 | title=Flash Memories: Economic Principles of Performance, Cost and Reliability Optimization | isbn=978-94-007-6082-0 | last1=Richter | first1=Detlev | date=12 September 2013 | publisher=Springer }} as it can be either byte-addressable or word-addressable, with words being for example 32 bits long,{{Cite book |last1=Daintith |first1=John |last2=Wright |first2=Edmund |url=https://books.google.com/books?id=9Q9XNh716ikC&dq=nor+byte+addressable&pg=PA123 |title=The Facts on File Dictionary of Computer Science |date=14 May 2014 |publisher=Infobase Publishing |isbn=9781438109398 |via=Google Books }}{{Cite book|url=https://books.google.com/books?id=VDkPEAAAQBAJ&dq=nor+byte+addressable&pg=PR22|title=Silicon Based Unified Memory Devices and Technology|first=Arup|last=Bhattacharyya|date=6 July 2017|publisher=CRC Press|isbn=9781351798327 |via=Google Books}}{{Cite book|url=https://books.google.com/books?id=rGjkBQAAQBAJ&dq=nor+random+access+byte+addressable&pg=PA59|title=FUNDAMENTALS OF COMPUTERS|first1=V.|last1=RAJARAMAN|first2=NEEHARIKA|last2=ADABALA|date=15 December 2014|publisher=PHI Learning Pvt. Ltd.|isbn=9788120350670 |via=Google Books}} while NAND allows only page access.{{cite web|last=Aravindan|first=Avinash|date=2018-07-23|title=Flash 101: NAND Flash vs NOR Flash|url=https://www.embedded.com/flash-101-nand-flash-vs-nor-flash/|access-date=2020-12-23|website=Embedded.com|language=en-US}}

NOR{{cite book | url=https://books.google.com/books?id=7XhhDwAAQBAJ&dq=nor+random+access&pg=PA113 | title=Bits on Chips | isbn=978-3-319-76096-4 | last1=Veendrick | first1=Harry | date=21 June 2018 | publisher=Springer }} and NAND flash get their names from the structure of the interconnections between memory cells.{{Cite web |title=NAND and NOR Gates |url=https://bob.cs.sonoma.edu/testing/sec-nand.html |access-date=2024-11-03 |website=bob.cs.sonoma.edu}} In NOR flash, cells are connected in parallel to the bit lines, allowing cells to be read and programmed individually.{{Cite book|url=https://books.google.com/books?id=vaq11vKwo_kC&dq=nand+flash+xip&pg=PA12|title=Inside NAND Flash Memories|first1=Rino|last1=Micheloni|first2=Luca|last2=Crippa|first3=Alessia|last3=Marelli|date=27 July 2010|publisher=Springer Science & Business Media|isbn=9789048194315 |via=Google Books}} The parallel connection of cells resembles the parallel connection of transistors in a CMOS NOR gate.{{Cite book|url=https://books.google.com/books?id=44mbEAAAQBAJ&dq=nor+flash+nor+gate&pg=PA55|title=Springer Handbook of Semiconductor Devices|first1=Massimo|last1=Rudan|first2=Rossella|last2=Brunetti|first3=Susanna|last3=Reggiani|date=10 November 2022|publisher=Springer Nature|isbn=9783030798277 |via=Google Books}} In NAND flash, cells are connected in series, resembling a CMOS NAND gate. The series connections consume less space than parallel ones, reducing the cost of NAND flash. It does not, by itself, prevent NAND cells from being read and programmed individually.{{Citation needed|date=September 2020}}

Each NOR flash cell is larger than a NAND flash cell{{snd}} 10 F² vs 4 F²{{snd}}{{vague|date=October 2024}} even when using exactly the same semiconductor device fabrication and so each transistor, contact, etc. is exactly the same size{{snd}} because NOR flash cells require a separate metal contact for each cell.{{Citation |publisher=Micron |url=http://www.micron.com/~/media/Documents/Products/Technical%20Note/NAND%20Flash/tn2919_nand_101.pdf |id=TN-29-19 |title=NAND Flash 101: An Introduction to NAND Flash and How to Design It in to Your Next Product |pages=2–3 |url-status=dead |archive-url=https://web.archive.org/web/20160604054353/https://www.micron.com/~/media/Documents/Products/Technical%20Note/NAND%20Flash/tn2919_nand_101.pdf |archive-date=4 June 2016}}{{cite book | url=https://books.google.com/books?id=2E0r6BRo2VkC&dq=nor+flash+nand+flash&pg=PA200 | title=CMOS Processors and Memories | isbn=978-90-481-9216-8 | last1=Iniewski | first1=Krzysztof | date=9 August 2010 | publisher=Springer }}

Because of the series connection and removal of wordline contacts, a large grid of NAND flash memory cells will occupy perhaps only 60% of the area of equivalent NOR cells{{Cite news |last1=Pavan |first1=Paolo |last2=Bez |first2=Roberto |last3=Olivo |first3=Piero |last4=Zanoni |first4=Enrico |publication-date=August 1997 |title=Flash Memory Cells – An Overview |periodical=Proceedings of the IEEE |volume=85 |issue=8 |pages=1248–1271 |url= https://ieeexplore.ieee.org/document/622505 |access-date=15 August 2008 |doi=10.1109/5.622505 |year=1997}} (assuming the same CMOS process resolution, for example, 130 nm, 90 nm, or 65 nm). NAND flash's designers realized that the area of a NAND chip, and thus the cost, could be further reduced by removing the external address and data bus circuitry. Instead, external devices could communicate with NAND flash via sequential-accessed command and data registers, which would internally retrieve and output the necessary data. This design choice made random-access of NAND flash memory impossible, but the goal of NAND flash was to replace mechanical hard disks, not to replace ROMs.

The first GSM phones and many feature phones had NOR flash memory, from which processor instructions could be executed directly in an execute-in-place architecture and allowed for short boot times. With smartphones, NAND flash memory was adopted as it has larger storage capacities and lower costs, but causes longer boot times because instructions cannot be executed from it directly, and must be copied to RAM memory first before execution.{{cite book | url=https://books.google.com/books?id=vaq11vKwo_kC&dq=nand+flash+copy+sram&pg=PA12 | title=Inside NAND Flash Memories | isbn=978-90-481-9431-5 | last1=Micheloni | first1=Rino | last2=Crippa | first2=Luca | last3=Marelli | first3=Alessia | date=27 July 2010 | publisher=Springer }}

The write endurance of SLC floating-gate NOR flash is typically equal to or greater than that of NAND flash, while MLC NOR and NAND flash have similar endurance capabilities. Examples of endurance cycle ratings listed in datasheets for NAND and NOR flash, as well as in storage devices using flash memory, are provided.{{cite web |url=http://electronicdesign.com/memory/fundamentals-flash-memory-storage |title=The Fundamentals of Flash Memory Storage |access-date=2017-01-03 |url-status=live |archive-url=https://web.archive.org/web/20170104163357/http://electronicdesign.com/memory/fundamentals-flash-memory-storage |archive-date=4 January 2017|date=2012-03-20 }}

However, by applying certain algorithms and design paradigms such as wear leveling and memory over-provisioning, the endurance of a storage system can be tuned to serve specific requirements.{{cite web |url=http://www.wdc.com/WDProducts/SSD/whitepapers/en/NAND_Evolution_0812.pdf |title=NAND Evolution and its Effects on Solid State Drive Useable Life |publisher=Western Digital |year=2009 |access-date=22 April 2012 |url-status=dead |archive-url=https://web.archive.org/web/20111112000643/http://www.wdc.com/WDProducts/SSD/whitepapers/en/NAND_Evolution_0812.pdf |archive-date=12 November 2011}}

In order to compute the longevity of the NAND flash, one must account for the size of the memory chip, the type of memory (e.g. SLC/MLC/TLC), and use pattern. Industrial NAND and server NAND are in demand due to their capacity, longer endurance and reliability in sensitive environments.

As the number of bits per cell increases, performance and life of NAND flash may degrade, increasing random read times to 100μs for TLC NAND which is 4 times the time required in SLC NAND, and twice the time required in MLC NAND, for random reads.

{{Main|Flash file system}}

Because of the particular characteristics of flash memory, it is best used with either a controller to perform wear leveling and error correction or specifically designed flash file systems, which spread writes over the media and deal with the long erase times of NOR flash blocks. The basic concept behind flash file systems is the following: when the flash store is to be updated, the file system will write a new copy of the changed data to a fresh block, remap the file pointers, then erase the old block later when it has time.

In practice, flash file systems are used only for memory technology devices (MTDs), which are embedded flash memories that do not have a controller. Removable flash memory cards, SSDs, eMMC/eUFS chips and USB flash drives have built-in controllers to perform wear leveling and error correction so use of a specific flash file system may not add benefit.

Multiple chips are often arrayed or die stacked to achieve higher capacities{{cite news |url=http://www.dailycircuitry.com/2012/04/as-follow-up-to-our-flash-vs-dram.html |title=Flash vs DRAM follow-up: chip stacking |publisher=The Daily Circuit |date=22 April 2012 |access-date=22 April 2012 |url-status=usurped |archive-url=https://web.archive.org/web/20121124042741/http://www.dailycircuitry.com/2012/04/as-follow-up-to-our-flash-vs-dram.html |archive-date=24 November 2012}} for use in consumer electronic devices such as multimedia players or GPSs. The capacity scaling (increase) of flash chips used to follow Moore's law because they are manufactured with many of the same integrated circuits techniques and equipment. Since the introduction of 3D NAND, scaling is no longer necessarily associated with Moore's law since ever smaller transistors (cells) are no longer used.

Consumer flash storage devices typically are advertised with usable sizes expressed as a small integer power of two (2, 4, 8, etc.) and a conventional designation of megabytes (MB) or gigabytes (GB); e.g., 512 MB, 8 GB. This includes SSDs marketed as hard drive replacements, in accordance with traditional hard drives, which use decimal prefixes.{{cite web |url=http://www.convertunits.com/type/computer+data+storage |title=Computer data storage unit conversion - non-SI quantity |access-date=2015-05-20 |url-status=live |archive-url=https://web.archive.org/web/20150508070909/http://www.convertunits.com/type/computer+data+storage |archive-date=8 May 2015}} Thus, an SSD marked as "64 GB" is at least {{nowrap|64 × 1000³}} bytes (64 GB). Most users will have slightly less capacity than this available for their files, due to the space taken by file system metadata and because some operating systems report SSD capacity using binary prefixes which are somewhat larger than conventional prefixes .

The flash memory chips inside them are sized in strict binary multiples, but the actual total capacity of the chips is not usable at the drive interface. It is considerably larger than the advertised capacity in order to allow for distribution of writes (wear leveling), for sparing, for error correction codes, and for other metadata needed by the device's internal firmware.

In 2005, Toshiba and SanDisk developed a NAND flash chip capable of storing 1 GB of data using multi-level cell (MLC) technology, capable of storing two bits of data per cell. In September 2005, Samsung Electronics announced that it had developed the world's first 2 GB chip.{{cite news |first=Anton |last=Shilov |url=http://www.xbitlabs.com/news/memory/display/20050912212649.html |title=Samsung Unveils 2GB Flash Memory Chip |publisher=X-bit labs |date=12 September 2005 |access-date=30 November 2008 |url-status=dead |archive-url=https://web.archive.org/web/20081224220204/http://www.xbitlabs.com/news/memory/display/20050912212649.html |archive-date=24 December 2008}}

In March 2006, Samsung announced flash hard drives with capacity of 4 GB, essentially the same order of magnitude as smaller laptop hard drives, and in September 2006, Samsung announced an 8 GB chip produced using a 40 nm manufacturing process.{{cite news |first=Wolfgang |last=Gruener |url=http://www.tgdaily.com/content/view/28504/135/ |archive-url=https://web.archive.org/web/20080323070752/http://www.tgdaily.com/content/view/28504/135/ |url-status=dead |archive-date=23 March 2008 |title=Samsung announces 40 nm Flash, predicts 20 nm devices |publisher=TG Daily |date=11 September 2006 |access-date=30 November 2008 }}

In January 2008, SanDisk announced availability of their 16 GB MicroSDHC and 32 GB SDHC Plus cards.{{Cite press release |date=7 January 2008 |title=SanDisk Announces the 12-Gigabyte microSDHC Card - the World's Largest Capacity Card for Mobile Phones |url=http://www.sandisk.com/Corporate/PressRoom/PressReleases/PressRelease.aspx?ID=4079 |url-status=dead |archive-url=https://web.archive.org/web/20081219084116/http://www.sandisk.com/Corporate/PressRoom/PressReleases/PressRelease.aspx?ID=4079 |archive-date=19 December 2008 |publisher=SanDisk |place=Las Vegas, Nevada |id=4079 }}{{Cite press release |date=31 January 2008 |title=SanDisk UltraII Line Picks Up Speed and Boosts Capacity with New 32- AND 16-Gigabyte SDHC and 8GB SDHC Plus Cards |url=http://www.sandisk.com/Corporate/PressRoom/PressReleases/PressRelease.aspx?ID=4091 |url-status=dead |archive-url=https://web.archive.org/web/20081219084247/http://www.sandisk.com/Corporate/PressRoom/PressReleases/PressRelease.aspx?ID=4091 |archive-date=19 December 2008 |publisher=SanDisk |place=Las Vegas, Nevada |id=4091 }}

More recent flash drives (as of 2012) have much greater capacities, holding 64, 128, and 256 GB.https://www.pcworld.com/article/225370/look_out_for_the_256gb_thumb_drive_and_the_128gb_tablet.html{{dead link|date=June 2022}}; {{cite web |url=https://techcrunch.com/2009/07/20/kingston-outs-the-first-256gb-flash-drive/ |title=Kingston outs the first 256GB flash drive |date=20 July 2009 |access-date=2017-08-28 |url-status=live |archive-url=https://web.archive.org/web/20170708012814/https://techcrunch.com/2009/07/20/kingston-outs-the-first-256gb-flash-drive/ |archive-date=8 July 2017}} 20 July 2009, Kingston DataTraveler 300 is 256 GB.

A joint development at Intel and Micron will allow the production of 32-layer 3.5 terabyte (TB{{clarify|3500 GB or 3.5 * 1024 GB?|date=February 2020}}) NAND flash sticks and 10 TB standard-sized SSDs. The device includes 5 packages of 16 × 48 GB TLC dies, using a floating gate cell design.{{Cite news |url = http://www.gizmag.com/high-capacity-3d-flash-memory/36782 |title = 3D flash technology moves forward with 10 TB SSDs and the first 48-layer memory cells |last = Borghino |first = Dario |date = 31 March 2015 |work = Gizmag |access-date = 31 March 2015 |url-status = live |archive-url = https://web.archive.org/web/20150518115212/http://www.gizmag.com/high-capacity-3d-flash-memory/36782/ |archive-date = 18 May 2015}}

Flash chips continue to be manufactured with capacities under or around 1 MB (e.g. for BIOS-ROMs and embedded applications).

In July 2016, Samsung announced the 4 TB {{clarify|4000 GB or 4 * 1024 GB?|date=February 2020}} Samsung 850 EVO which utilizes their 256 Gbit 48-layer TLC 3D V-NAND.{{Cite news|url=https://www.custompcreview.com/news/samsung-launches-4tb-850-evo-ssd-priced-1499/30838/|title=Samsung Launches Monster 4TB 850 EVO SSD Priced at $1,499 {{!}} Custom PC Review|date=2016-07-13|newspaper=Custom PC Review |access-date=2016-10-08|url-status=live|archive-url=https://web.archive.org/web/20161009172049/https://www.custompcreview.com/news/samsung-launches-4tb-850-evo-ssd-priced-1499/30838/|archive-date=9 October 2016}} In August 2016, Samsung announced a 32 TB 2.5-inch SAS SSD based on their 512 Gbit 64-layer TLC 3D V-NAND. Further, Samsung expects to unveil SSDs with up to 100 TB of storage by 2020.{{Cite news|url=https://www.custompcreview.com/news/samsung-unveils-32tb-ssd-leveraging-4th-gen-64-layer-3d-v-nand/31651/|title=Samsung Unveils 32TB SSD Leveraging 4th Gen 64-Layer 3D V-NAND {{!}} Custom PC Review|date=2016-08-11|newspaper=Custom PC Review |access-date=2016-10-08|url-status=live|archive-url=https://web.archive.org/web/20161009170533/https://www.custompcreview.com/news/samsung-unveils-32tb-ssd-leveraging-4th-gen-64-layer-3d-v-nand/31651/|archive-date=9 October 2016}}

Flash memory devices are typically much faster at reading than writing.{{cite journal |last1=Master |first1=Neal |last2=Andrews |first2=Mathew |last3=Hick |first3=Jason |last4=Canon |first4=Shane |last5=Wright |first5=Nicholas |title=Performance analysis of commodity and enterprise class flash devices |journal=IEEE Petascale Data Storage Workshop |date=2010 |url=http://www.pdsw.org/pdsw10/resources/papers/master.pdf |url-status=live |archive-url=https://web.archive.org/web/20160506160509/http://www.pdsw.org/pdsw10/resources/papers/master.pdf |archive-date=6 May 2016}} Performance also depends on the quality of storage controllers, which become more critical when devices are partially full.{{vague|date=December 2020}} Even when the only change to manufacturing is die-shrink, the absence of an appropriate controller can result in degraded speeds.{{Cite news |last=Ng |first=Jansen |title=Samsung Confirms 32nm Flash Problems, Working on New SSD Controller |work=dailytech.com |url=http://www.dailytech.com/article.aspx?newsid=16407 |url-status=dead |access-date=3 October 2009 |archive-url=https://web.archive.org/web/20160304003356/http://www.dailytech.com/article.aspx?newsid=16407 |archive-date=4 March 2016 }}

File:IPhone 3G teardown - Silicon Storage Tech SST25VF080B-3309.jpg

Serial flash is a small, low-power flash memory that provides only serial access to the data - rather than addressing individual bytes, the user reads or writes large contiguous groups of bytes in the address space serially. Serial Peripheral Interface Bus (SPI) is a typical protocol for accessing the device.

When incorporated into an embedded system, serial flash requires fewer wires on the PCB than parallel flash memories, since it transmits and receives data one bit at a time. This may permit a reduction in board space, power consumption, and total system cost.

There are several reasons why a serial device, with fewer external pins than a parallel device, can significantly reduce overall cost:

• Many ASICs are pad-limited, meaning that the size of the die is constrained by the number of wire bond pads, rather than the complexity and number of gates used for the device logic. Eliminating bond pads thus permits a more compact integrated circuit, on a smaller die; this increases the number of dies that may be fabricated on a wafer, and thus reduces the cost per die.
• Reducing the number of external pins also reduces assembly and packaging costs. A serial device may be packaged in a smaller and simpler package than a parallel device.
• Smaller and lower pin-count packages occupy less PCB area.
• Lower pin-count devices simplify PCB routing.

There are two major SPI flash types. The first type is characterized by small blocks and one internal SRAM block buffer allowing a complete block to be read to the buffer, partially modified, and then written back (for example, the Atmel AT45 DataFlash or the Micron Technology Page Erase NOR Flash). The second type has larger sectors where the smallest sectors typically found in this type of SPI flash are 4 KB, but they can be as large as 64 KB. Since this type of SPI flash lacks an internal SRAM buffer, the complete block must be read out and modified before being written back, making it slow to manage. However, the second type is cheaper than the first and is therefore a good choice when the application is code shadowing.

The two types are not easily exchangeable, since they do not have the same pinout, and the command sets are incompatible.

Most FPGAs are based on SRAM configuration cells and require an external configuration device, often a serial flash chip, to reload the configuration bitstream every power cycle.

Clive Maxfield.

[https://books.google.com/books?id=u0xyEuXF3l4C "Bebop to the Boolean Boogie: An Unconventional Guide to Electronics"].

p. 232.

With the increasing speed of modern CPUs, parallel flash devices are often much slower than the memory bus of the computer they are connected to. Conversely, modern SRAM offers access times below 10 ns, while DDR2 SDRAM offers access times below 20 ns. Because of this, it is often desirable to shadow code stored in flash into RAM; that is, the code is copied from flash into RAM before execution, so that the CPU may access it at full speed. Device firmware may be stored in a serial flash chip, and then copied into SDRAM or SRAM when the device is powered-up.Many serial flash devices implement a bulk read mode and incorporate an internal address counter, so that it is trivial to configure them to transfer their entire contents to RAM on power-up. When clocked at 50 MHz, for example, a serial flash could transfer a 64 Mbit firmware image in less than two seconds. Using an external serial flash device rather than on-chip flash removes the need for significant process compromise (a manufacturing process that is good for high-speed logic is generally not good for flash and vice versa). Once it is decided to read the firmware in as one big block it is common to add compression to allow a smaller flash chip to be used. Since 2005, many devices use serial NOR flash to deprecate parallel NOR flash for firmware storage. Typical applications for serial NOR flash include storing firmware for hard drives, BIOS, Option ROM of expansion cards, DSL modems, etc.

{{Main|Solid-state drive}}

File:Intel 525 mSATA SSD.jpg

One more recent application for flash memory is as a replacement for hard disks. Flash memory does not have the mechanical limitations and latencies of hard drives, so a solid-state drive (SSD) is attractive in terms of speed, noise, power consumption, and reliability. Flash drives are gaining traction as mobile device secondary storage devices; they are also used as substitutes for hard drives in high-performance desktop computers and some servers with RAID and SAN architectures.

There remain some aspects of flash-based SSDs that make them unattractive. The cost per gigabyte of flash memory remains significantly higher than that of hard disks.{{Cite web |date=17 March 2011 |title=SSD vs. HDD |url=http://elitepcbuilding.com/ssd-vs-hdd |url-status=dead |archive-url=https://web.archive.org/web/20110820095531/http://elitepcbuilding.com/ssd-vs-hdd |archive-date=20 August 2011 |access-date=11 July 2011 |website=elitepcbuilding.com |author=((Lyth0s)) }} Also, flash memory has a finite number of P/E (program/erase) cycles, but this seems to be currently under control since warranties on flash-based SSDs are approaching those of current hard drives.{{cite web |url=http://www.storagesearch.com/bitmicro-art1.html |title=Flash Solid State Disks – Inferior Technology or Closet Superstar? |publisher=STORAGEsearch |access-date=30 November 2008 |url-status=live |archive-url=https://web.archive.org/web/20081224215032/http://www.storagesearch.com/bitmicro-art1.html |archive-date=24 December 2008}} In addition, deleted files on SSDs can remain for an indefinite period of time before being overwritten by fresh data; erasure or shred techniques or software that work well on magnetic hard disk drives have no effect on SSDs, compromising security and forensic examination. However, due to the so-called TRIM command employed by most solid state drives, which marks the logical block addresses occupied by the deleted file as unused to enable garbage collection, data recovery software is not able to restore files deleted from such.

For relational databases or other systems that require ACID transactions, even a modest amount of flash storage can offer vast speedups over arrays of disk drives.{{Cite web |last=Matsunobu |first=Yoshinori |date=15 April 2010 |title=SSD Deployment Strategies for MySQL |url=http://www.slideshare.net/matsunobu/ssd-deployment-strategies-for-mysql |url-status=dead |archive-url=https://web.archive.org/web/20160303224013/http://www.slideshare.net/matsunobu/ssd-deployment-strategies-for-mysql |archive-date=3 March 2016 }}

In May 2006, Samsung Electronics announced two flash-memory based PCs, the Q1-SSD and Q30-SSD were expected to become available in June 2006, both of which used 32 GB SSDs, and were at least initially available only in South Korea.{{cite web |url=http://www.samsung.com/he/presscenter/pressrelease/pressrelease_20060524_0000257996.asp |title=Samsung Electronics Launches the World's First PCs with NAND Flash-based Solid State Disk |work=Press Release |publisher=Samsung |date=24 May 2006 |access-date=30 November 2008 |url-status=live |archive-url=https://web.archive.org/web/20081220094813/http://www.samsung.com/he/presscenter/pressrelease/pressrelease_20060524_0000257996.asp |archive-date=20 December 2008}} The Q1-SSD and Q30-SSD launch was delayed and finally was shipped in late August 2006.{{cite web| url=https://news.softpedia.com/news/Samsung-s-SSD-Notebook-33475.shtml| title=Samsung's SSD Notebook| date=22 August 2006| access-date=15 October 2018| archive-date=15 October 2018| archive-url=https://web.archive.org/web/20181015192607/https://news.softpedia.com/news/Samsung-s-SSD-Notebook-33475.shtml| url-status=dead}}

The first flash-memory based PC to become available was the Sony Vaio UX90, announced for pre-order on 27 June 2006 and began to be shipped in Japan on 3 July 2006 with a 16 GB flash memory hard drive.{{Cite press release |date=27 June 2006 |title=文庫本サイズの「VAIO type U」 フラッシュメモリー搭載モデル発売 |trans-title=Release of the "VAIO type U" paperback-sized model with flash memory |url=https://www.sony.jp/CorporateCruise/Press/200606/06-0627/ |url-status=live |archive-url=https://web.archive.org/web/20230510003927/https://www.sony.jp/CorporateCruise/Press/200606/06-0627/ |archive-date=10 May 2023 |publisher=Sony |language=ja }} In late September 2006 Sony upgraded the flash-memory in the Vaio UX90 to 32 GB.{{cite web | url=http://nbnews.info/en/news/397 | title=Sony Vaio UX UMPC – now with 32 GB Flash memory | NBnews.info. Laptop and notebook news, reviews, test, specs, price | Каталог ноутбуков, ультрабуков и планшетов, новости, обзоры | access-date=7 November 2018 | archive-date=28 June 2022 | archive-url=https://web.archive.org/web/20220628004451/https://nbnews.info/en/news/397 | url-status=dead }}

A solid-state drive was offered as an option with the first MacBook Air introduced in 2008, and from 2010 onwards, all models were shipped with an SSD. Starting in late 2011, as part of Intel's Ultrabook initiative, an increasing number of ultra-thin laptops are being shipped with SSDs standard.

There are also hybrid techniques such as hybrid drive and ReadyBoost that attempt to combine the advantages of both technologies, using flash as a high-speed non-volatile cache for files on the disk that are often referenced, but rarely modified, such as application and operating system executable files.

On smartphones, the NAND flash products are used as file storage device, for example, eMMC and eUFS.

{{As of|2012|post=,}} there are attempts to use flash memory as the main computer memory, DRAM.{{Cite news |last=Perry |first=Douglas |date=July 25, 2012 |title=Princeton: Replacing RAM with Flash Can Save Massive Power |work=Tom's Hardware |url=https://www.tomshardware.com/news/fusio-io-flash-ssdalloc-memory-ram,16352.html |url-status=live |archive-url=https://web.archive.org/web/20231106092024/https://www.tomshardware.com/news/fusio-io-flash-ssdalloc-memory-ram,16352.html |archive-date=6 November 2023 }}

Floating-gate transistors in the flash storage device hold charge which represents data. This charge gradually leaks over time, leading to an accumulation of logical errors, also known as "bit rot" or "bit fading".

It is unclear how long data on flash memory will persist under archival conditions (i.e., benign temperature and humidity with infrequent access with or without prophylactic rewrite). Datasheets of Atmel's flash-based "ATmega" microcontrollers typically promise retention times of 20 years at 85 °C (185 °F) and 100 years at 25 °C (77 °F).{{cite web |title=8-Bit AVR Microcontroller ATmega32A Datasheet Complete |date=2016-02-19 |access-date=2016-05-29 |page=18 |url=https://www.atmel.com/images/atmel-8155-8-bit-microcontroller-avr-atmega32a_datasheet.pdf |quote=Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85 °C or 100 years at 25 °C |url-status=dead |archive-url=https://web.archive.org/web/20160409120244/http://www.atmel.com/Images/Atmel-8155-8-bit-Microcontroller-AVR-ATmega32A_Datasheet.pdf |archive-date=9 April 2016}}

The retention span varies among types and models of flash storage. When supplied with power and idle, the charge of the transistors holding the data is routinely refreshed by the firmware of the flash storage.{{Cite web |date=23 July 2020 |title=Understanding Life Expectancy of Flash Storage |url=https://www.ni.com/en-us/support/documentation/supplemental/12/understanding-life-expectancy-of-flash-storage.html |url-status=live |archive-url=https://web.archive.org/web/20231201202529/https://www.ni.com/en/support/documentation/supplemental/12/understanding-life-expectancy-of-flash-storage.html |archive-date=1 December 2023 |access-date=19 December 2020 |website=www.ni.com }} The ability to retain data varies among flash storage devices due to differences in firmware, data redundancy, and error correction algorithms.{{Cite web |date=29 December 2013 |title=On Hacking MicroSD Cards |url=https://www.bunniestudios.com/blog/?p=3554 |url-status=live |archive-url=https://web.archive.org/web/20231102105433/https://www.bunniestudios.com/blog/?p=3554 |archive-date=2 November 2023 |website=bunnie's blog }}

An article from CMU in 2015 states "Today's flash devices, which do not require flash refresh, have a typical retention age of 1 year at room temperature." And that retention time decreases exponentially with increasing temperature. The phenomenon can be modeled by the Arrhenius equation.{{cite web

|title = Data Retention in MLC NAND Flash Memory: Characterization, Optimization, and Recovery

|date = 2015-01-27

|access-date = 2016-04-27

|page = 10

|url = https://users.ece.cmu.edu/~omutlu/pub/flash-memory-data-retention_hpca15.pdf

|url-status = live

|archive-url = https://web.archive.org/web/20161007000927/https://users.ece.cmu.edu/~omutlu/pub/flash-memory-data-retention_hpca15.pdf

|archive-date = 7 October 2016}}{{cite web

|title = JEDEC SSD Specifications Explained

|url = https://www.jedec.org/sites/default/files/Alvin_Cox%20%5BCompatibility%20Mode%5D_0.pdf

|at = p. 27

}}

Some FPGAs are based on flash configuration cells that are used directly as (programmable) switches to connect internal elements together, using the same kind of floating-gate transistor as the flash data storage cells in data storage devices.

{{See also|Semiconductor industry}}

One source states that, in 2008, the flash memory industry includes about US$9.1 billion in production and sales. Other sources put the flash memory market at a size of more than US$20 billion in 2006, accounting for more than eight percent of the overall semiconductor market and more than 34 percent of the total semiconductor memory market.{{cite journal|last=Yinug |first=Christopher Falan |date=July 2007 |title=The Rise of the Flash Memory Market: Its Impact on Firm Behavior and Global Semiconductor Trade Patterns |journal=Journal of International Commerce and Economics |url=http://www.usitc.gov/journal/Final_falan_article1.pdf |access-date=19 April 2008 |archive-url=https://web.archive.org/web/20080529180622/http://www.usitc.gov/journal/Final_falan_article1.pdf |archive-date=29 May 2008 |url-status=dead}}

In 2012, the market was estimated at $26.8 billion.{{Cite news |last=Hajdarbegovic |first=Nermin |date=17 April 2013 |title=NAND memory market rockets |work=TG Daily |url=http://www.tgdaily.com/hardware-brief/71015-nand-memory-market-rockets |url-status=dead |access-date=18 April 2013 |archive-url=https://web.archive.org/web/20160208114459/http://www.tgdaily.com/hardware-brief/71015-nand-memory-market-rockets |archive-date=8 February 2016 }} It can take up to 10 weeks to produce a flash memory chip.{{Cite news |last=Owen |first=Malcolm |title=Power outage may have ruined 15 exabytes of WD and Toshiba flash storage |work=AppleInsider |url=https://appleinsider.com/articles/19/07/01/power-outage-may-have-ruined-15-exabytes-of-wd-and-toshiba-memory |url-status=live |archive-url=https://web.archive.org/web/20231102134950/https://appleinsider.com/articles/19/07/01/power-outage-may-have-ruined-15-exabytes-of-wd-and-toshiba-memory |archive-date=2 November 2023 }}

{{Main|List of flash memory controller manufacturers|List of solid-state drive manufacturers}}

The following were the largest NAND flash memory manufacturers, as of the second quarter of 2023.{{cite web |title=NAND Flash manufacturers' market share 2019 |url=https://www.statista.com/statistics/275886/market-share-held-by-leading-nand-flash-memory-manufacturers-worldwide/ |website=Statista |access-date=3 July 2019}}

1. Samsung Electronics {{ndash}} 31.4%
2. Kioxia {{ndash}} 20.6%
3. Western Digital Corporation {{ndash}} 12.6%
4. SK Hynix {{ndash}} 18.5%
5. Micron Technology {{ndash}} 12.3%
6. Others {{ndash}} 8.7%

Notes: Samsung remains the largest NAND flash memory manufacturer as of Q1 2022.{{cite web |title=NAND Revenue by Manufacturers Worldwide (2014-2022) |date=26 May 2020 |url= https://businessquant.com/nand-revenue-by-manufacturer-worldwide#:~:text=NAND%20manufacturers%20collectively%20generated%20%2417.91,third%20and%20fourth%20positions%2C%20respectively. |access-date=June 27, 2022}}

Kioxia spun out and got renamed of Toshiba in 2018/2019.{{Cite news |last=Kwan |first=Campbell |title=Former Toshiba memory business to rebrand as Kioxia |publisher=ZDNet |url= https://www.zdnet.com/article/former-toshiba-memory-business-to-rebrand-as-kioxia/ |url-status=live |access-date=12 July 2023 |archive-url= https://web.archive.org/web/20231004074304/https://www.zdnet.com/article/former-toshiba-memory-business-to-rebrand-as-kioxia/ |archive-date=4 October 2023}}

SK Hynix acquired Intel's NAND business at the end of 2021.{{cite news |title=SK Hynix completes first phase of $9 bln Intel NAND business buy |newspaper=Reuters |date=29 December 2021 |url= https://www.reuters.com/technology/sk-hynix-completes-first-phase-9-bln-intel-nand-business-buy-2021-12-29/ |access-date=June 27, 2022}}

{{See also|Electronics industry|Transistor count}}

{{See also|List of semiconductor scale examples|Moore's law}}

Due to its relatively simple structure and high demand for higher capacity, NAND flash memory is the most aggressively scaled technology among electronic devices. The heavy competition among the top few manufacturers only adds to the aggressiveness in shrinking the floating-gate MOSFET design rule or process technology node. While the expected shrink timeline is a factor of two every three years per the original version of Moore's law, this has recently been accelerated in the case of NAND flash to a factor of two every two years.

{{clear}}

As the MOSFET feature size of flash memory cells reaches the 15–16 nm minimum limit, further flash density increases will be driven by TLC (3 bits/cell) combined with vertical stacking of NAND memory planes. The decrease in endurance and increase in uncorrectable bit error rates that accompany feature size shrinking can be compensated by improved error correction mechanisms.{{Cite news |last=Shimpi |first=Anand Lal |date=2 December 2010 |title=Micron's ClearNAND: 25nm + ECC, Combats Increasing Error Rates |work=AnandTech |url=https://www.anandtech.com/show/4043/micron-announces-clearnand-25nm-with-ecc |url-status=live |access-date=2 December 2010 |archive-url=https://web.archive.org/web/20101203082325/http://www.anandtech.com/show/4043/micron-announces-clearnand-25nm-with-ecc |archive-date=3 December 2010 }} Even with these advances, it may be impossible to economically scale flash to smaller and smaller dimensions as the number of electron holding capacity reduces. Many promising new technologies (such as FeRAM, MRAM, PMC, PCM, ReRAM, and others) are under investigation and development as possible more scalable replacements for flash.{{Cite conference |last1=Kim |first1=Kinam |last2=Koh |first2=Gwan-Hyeob |date=16 May 2004 |title=Future memory technology including emerging new memories |conference=24th International Conference on Microelectronics |location=Niš, Serbia |publisher=Institute of Electrical and Electronics Engineers |pages=377–384 |doi=10.1109/ICMEL.2004.1314646 |isbn=978-0-7803-8166-7 |s2cid=40985239 }}

{{See also|Read-only memory#Timeline|Random-access memory#Timeline|Transistor count#Memory}}

• eMMC
• Flash memory controller
• Intel hex file format
• List of flash file systems
• List of flash memory controller manufacturers
• microSDXC (up to 2 TB), and the successor format Secure Digital Ultra Capacity (SDUC) supporting cards up to 128 TiB
• NOR flash replacement
• Open NAND Flash Interface Working Group
• Read-mostly memory (RMM)
• Universal Flash Storage
• USB flash drive security
• Write amplification

{{Notelist|30em}}

{{reflist|colwidth=30em}}

{{Commons category}}

• [http://news.thomasnet.com/fullstory/547012 Semiconductor Characterization System has diverse functions] {{Webarchive|url=https://web.archive.org/web/20181022073504/https://news.thomasnet.com/fullstory/547012 |date=22 October 2018 }}
• [http://www.eetimes.com/design/memory-design/4211387/Understanding-and-selecting-higher-performance-NAND-architectures?Ecosystem=memory-design Understanding and selecting higher performance NAND architectures] {{Webarchive|url=https://web.archive.org/web/20121031081837/http://www.eetimes.com/design/memory-design/4211387/Understanding-and-selecting-higher-performance-NAND-architectures?Ecosystem=memory-design |date=31 October 2012 }}
• [http://www.slideshare.net/ennael/dwmw2-kr201209 How flash storage works, presentation by David Woodhouse from Intel]
• [http://hypnocube.com/2014/11/flash-endurance-testing/ Flash endurance testing]
• [http://adreca.net/NAND-Flash-Data-Recovery-Cookbook.pdf NAND Flash Data Recovery Cookbook]
• [https://openwrt.org/docs/techref/flash.layout#types_of_flash_memory Type of Flash Memory] by OpenWrt

{{Solid-state drive|state=collapsed}}

{{Authority control}}

Category:20th-century inventions

Category:Computer memory

Category:Japanese inventions

Category:Non-volatile memory

Category:Solid-state computer storage media