Ice Lake (microprocessor)#Ice Lake-D

Ice Lake was designed by Intel Israel's processor design team in Haifa, Israel.{{Cite news|url=https://en.globes.co.il/en/article-intel-launches-10th-gen-core-processor-developed-in-israel-1001287483|title=Intel launches 10th gen core processor developed in Israel|date=2019-05-28|newspaper=Globes|language=he|access-date=2019-10-06}}{{Cite web |last=Solomon |first=Shoshanna |date=May 28, 2019 |title=Intel launches new processors that bring AI to the PC, sired by Haifa team |url=https://www.timesofisrael.com/intel-launches-new-processors-that-bring-ai-to-the-pc-sired-by-haifa-team/ |website=The Times of Israel |language=en-US |access-date=October 6, 2019}}

Ice Lake is built on the Sunny Cove microarchitecture.{{Cite web|url=https://www.intel.com/content/www/us/en/content-details/671442/5-level-paging-and-5-level-ept-white-paper.html|title=5-Level Paging and 5-Level EPT|publisher=Intel Corporation|date=May 2017}} Intel released details of Ice Lake during Intel Architecture Day in December 2018, stating that the Sunny Cove core Ice Lake would be focusing on single-thread performance, new instructions, and scalability improvements. Intel stated that the performance improvements would be achieved by making the core "deeper, wider, and smarter".{{Cite web |last=Cutress |first=Ian |date=December 12, 2018 |title=Intel's Architecture Day 2018: The Future of Core, Intel GPUs, 10nm, and Hybrid x86 |url=https://www.anandtech.com/show/13699/intel-architecture-day-2018-core-future-hybrid-x86 |website=AnandTech |language=en-US |access-date=January 14, 2019}}

Ice Lake features Intel's Gen11 graphics, increasing the number of execution units to 64, from 24 or 48 in Gen9.5 graphics, achieving over 1 TFLOPS of compute performance.{{citation needed|date=February 2020}} Each execution unit supports 7 threads, meaning that the design has 512 concurrent pipelines. Feeding these execution units is a 3 megabyte L3 cache, a four-fold increase from Gen9.5, alongside the increased memory bandwidth enabled by LPDDR4X on low-power mobile platforms. Gen11 graphics also introduces tile-based rendering and Coarse Pixel Shading (CPS), Intel's implementation of variable-rate shading (VRS). The architecture also includes an all-new HEVC encoder design. On August 1, 2019, Intel released the specifications of Ice Lake -U and -Y CPUs.{{Cite web|url=https://newsroom.intel.com/news/intel-launches-first-10th-gen-intel-core-processors-redefining-next-era-laptop-experiences/|title=Intel Launches First 10th Gen Intel Core Processors: Redefining the Next Era of Laptop Experiences|website=Intel Newsroom|language=en-US|access-date=2019-08-01}} The Y-series CPUs lost their -Y suffix and m3 naming. Instead, Intel uses a trailing number before the GPU type to indicate their package power; "0" corresponds to 9{{nbsp}}W, "5" to 15{{nbsp}}W, and "8" to 28{{nbsp}}W. Furthermore, the first two numbers in the model number correspond to the generation of the chip, while the third number dictates the family the CPU belongs to (i3, i5, etc.); thus, a 1035G7 would be a 10th generation Core i5 with a package power of 15 watts and a G7 GPU.

Pre-orders for laptops featuring Ice Lake CPUs started in August 2019, followed by shipments in September.{{Cite web|url=https://www.techspot.com/news/81389-dell-taking-orders-xps-13-2-1-featuring.html|title=Dell taking orders for XPS 13 2-in-1 featuring Intel's 10nm Ice Lake|website=TechSpot|date=August 11, 2019 |language=en-US|access-date=2019-08-12}}

{{Further|Sunny Cove (microarchitecture)}}

• Intel Sunny Cove CPU cores{{Cite web|title=Sunny Cove - Microarchitectures - Intel - WikiChip|url=https://en.wikichip.org/wiki/intel/microarchitectures/sunny_cove|access-date=2021-02-08|website=en.wikichip.org|language=en}}
• On average 18% increase in IPC in comparison to 2015 Skylake running at the same frequency and memory configuration{{Cite web|url=https://fuse.wikichip.org/news/2371/intel-sunny-cove-core-to-deliver-a-major-improvement-in-single-thread-performance-bigger-improvements-to-follow/|title=Intel Sunny Cove Core To Deliver A Major Improvement In Single-Thread Performance, Bigger Improvements To Follow|last=Schor|first=David|date=2019-05-28|website=WikiChip Fuse|language=en-US|access-date=2019-05-28}}{{Cite web|url=https://fuse.wikichip.org/news/2370/intel-announces-10th-gen-core-processors-based-on-10nm-ice-lake-now-shipping/|title=Intel Announces 10th Gen Core Processors Based On 10nm Ice Lake, Now Shipping|last=Schor|first=David|date=2019-05-28|website=WikiChip Fuse|language=en-US|access-date=2019-05-28}}
• Dynamic Tuning 2.0 which allows the CPU to stay at turbo frequencies for longer{{Cite web|url=https://en.wikichip.org/wiki/intel/dynamic_tuning|title=Dynamic Tuning - Intel - WikiChip|website=en.wikichip.org|language=en|access-date=2019-05-28}}{{Cite web|url=https://www.anandtech.com/show/14514/examining-intels-ice-lake-microarchitecture-and-sunny-cove|title=Examining Intel's Ice Lake Processors: Taking a Bite of the Sunny Cove Microarchitecture|last=Cutress|first=Ian|website=AnandTech|access-date=2019-08-01}}
• TAGE-like directional branch predictor (with a global history size of 194 taken branches){{Cite conference |last1=Yavarzadeh |first1=Hosein |last2=Taram |first2=Mohammadkazem |last3=Narayan |first3=Shravan |last4=Stefan |first4=Deian |last5=Tullsen |first5=Dean |conference=2023 IEEE Symposium on Security and Privacy (SP) |title=Half&Half: Demystifying Intel's Directional Branch Predictors for Fast, Secure Partitioned Execution |date=May 2023 |url=https://ieeexplore.ieee.org/document/10179415 |publisher=IEEE |pages=1220–1237 |doi=10.1109/SP46215.2023.10179415 |isbn=978-1-6654-9336-9|s2cid=259255212 }}
• Hardware acceleration for SHA operations (Secure Hash Algorithms)
• Intel Deep Learning Boost, used for machine learning/artificial intelligence inference acceleration{{Cite web|url=https://www.intel.ai/intel-deep-learning-boost/|title=Intel® Deep Learning Boost|website=Intel AI|language=en-US|access-date=2019-08-01}}
• PCI Express 4.0 on Ice Lake-SP

• Gen 11 GPU with up to 64 execution units (From 24 and 48 EU){{cite web |url=https://software.intel.com/sites/default/files/managed/db/88/The-Architecture-of-Intel-Processor-Graphics-Gen11_R1new.pdf |title=Intel Processor Graphics Gen11 Architecture |publisher=Intel}}{{Cite web|url=https://software.intel.com/en-us/articles/developer-and-optimization-guide-for-intel-processor-graphics-gen11-api|title = Developer and Optimization Guide for Intel® Processor Graphics Gen11}}
• 4K at 120 Hz, 5K, 8K display output{{Cite news|url=https://hothardware.com/news/intel-ice-lake-10nm-dual-core-cpu-benchmarks-leak|title=Intel Ice Lake 10nm CPU Benchmark Leak Shows More Cache, Higher Performance|date=2018-10-23|work=HotHardware|access-date=2018-11-09|others=HotHardware|language=en-us}}
• Variable Rate Shading{{Cite web|url=https://www.anandtech.com/show/14664/testing-intel-ice-lake-10nm|title=The Ice Lake Benchmark Preview: Inside Intel's 10nm|last=Cutress|first=Dr Ian|website=www.anandtech.com|access-date=2019-08-01}}
• DisplayPort 1.4a with Display Stream Compression; HDMI 2.0b
• Up to 1.15 TFLOPS of computational performance{{citation needed|date=February 2020}}
• Two HEVC 10-bit encode pipelines, either two 4K 60{{nbsp}}Hz RGB/{{YCbCr}} 4:4:4 streams simultaneously or one 8K 30{{nbsp}}Hz {{YCbCr}} 4:2:2
• VP9 8-bit and 10-bit hardware encoding for all supported platforms as part of Intel Quick Sync Video{{Cite web|url=https://github.com/Intel-Media-SDK/MediaSDK/releases/tag/intel-mediasdk-20.2.1|title=Release Media SDK 20.2.1 · Intel-Media-SDK/MediaSDK|website=GitHub}}{{Cite web|url=https://github.com/intel/media-driver/issues/630|title=VP9 encode support from Kaby Lake+ · Issue #630 · intel/media-driver|website=GitHub}}{{Cite web|url=https://github.com/intel/media-driver/issues/771|title=Feature request: Expose VP9 encode support on Kabylake+ with the iHD driver · Issue #771 · intel/media-driver|website=GitHub}}
• Integer and nearest neighbor image scaling{{cite tweet|number=1167622125412392960|user=IntelGraphics|title=Our community suggested it and we are...|date=August 31, 2019}}{{Cite web|url=https://www.intel.com/content/www/us/en/developer/articles/technical/integer-scaling-support-on-intel-graphics.html|title = Integer Scaling Support on Intel® Graphics}}
• 4th Gen IPU{{Cite web|title=Ice Lake (client) - Microarchitectures - Intel - WikiChip|url=https://en.wikichip.org/wiki/intel/microarchitectures/ice_lake_(client)|access-date=2021-02-08|website=en.wikichip.org|language=en}}

• 10 nm transistors (originally called 10 nm+ transistors in older naming scheme){{Cite web|last=Sag|first=Anshel|date=Jun 19, 2019|title=Intel Charts A New Course With 10th Gen Core And Project Athena|url=https://moorinsightsstrategy.com/intel-charts-a-new-course-with-10th-gen-core-and-project-athena/}}
• New memory controller with DDR4 3200 and LPDDR4X 3733 support
• Integrated support for Wi-Fi 6 (802.11ax)
• Thunderbolt 3 support{{Cite web|url=https://newsroom.intel.com/news/intel-takes-steps-enable-thunderbolt-3-everywhere-releases-protocol/#gs.19wo3z|title = Intel Takes Steps to Enable Thunderbolt 3 Everywhere, Releases Protocol}}

{{Row hover highlight}}

{{cpulist|lake-e|head}}

{{cpulist|lake-e|icelake_e|model = Xeon Platinum 8351N|ark = 212288|cores = 36|threads = 72|turbo = {{frequency|3.5|GHz}}|mult = 24|l3 = 54|vmin =|vmax =|upi = 11.2|tdp = 225|mem = 8×DDR4-2933|date = 6 April 2021|sock = 4189|price = {{US$|3466|2021|long = no}}|links = 1|sspec1 = SRKJ3|step1 = D2|part1 = CD8068904582702 }}

{{cpulist|lake-e|icelake_e|model = Xeon Platinum 8352S|ark = 212307|cores = 32|threads = 64|turbo = {{frequency|3.4|GHz}}|mult = 22|l3 = 48|vmin =|vmax =|tdp = 205|upi = 11.2|mem = 8×DDR4-3200|date = 6 April 2021|sock = 4189|price = {{US$|4632|2021|long = no}}|links = 1|sspec1 = SRKJ8|step1 = D2|part1 = CD8068904642802 }}

{{cpulist|lake-e|icelake_e|model = Xeon Platinum 8352V|ark = 212454|cores = 36|threads = 72|turbo = {{frequency|3.5|GHz}}|mult = 21|l3 = 54|vmin =|vmax =|upi = 11.2|tdp = 195|mem = 8×DDR4-2933|date = 6 April 2021|sock = 4189|price = {{US$|3993|2021|long = no}}|links = 1|sspec1 = SRKJ2|step1 = D2|part1 = CD8068904571501 }}

{{cpulist|lake-e|icelake_e|model = Xeon Platinum 8352Y|ark = 212284|cores = 32|threads = 64|turbo = {{frequency|3.4|GHz}}|mult = 22|l3 = 48|vmin =|vmax =|tdp = 205|upi = 11.2|mem = 8×DDR4-3200|date = 6 April 2021|sock = 4189|price = {{US$|3995|2021|long = no}}|links = 1|sspec1 = SRKHG|step1 = D2|part1 = CD8068904572401 }}

{{cpulist|lake-e|icelake_e|model = Xeon Platinum 8358|ark = 212282|cores = 32|threads = 64|turbo = {{frequency|3.4|GHz}}|mult = 26|l3 = 48|vmin =|vmax =|upi = 11.2|tdp = 250|mem = 8×DDR4-3200|date = 6 April 2021|sock = 4189|price = {{US$|4607|2021|long = no}}|links = 1|sspec1 = SRKJ1|step1 = D2|part1 = CD8068904572302}}

{{cpulist|lake-e|icelake_e|model = Xeon Platinum 8358P|ark = 212308|cores = 32|threads = 64|turbo = {{frequency|3.4|GHz}}|mult = 26|l3 = 48|vmin =|vmax =|upi = 11.2|tdp = 240|mem = 8×DDR4-3200|date = 6 April 2021|sock = 4189|price = {{US$|4523|2021|long = no}}|links = 1|sspec1 = SRKJ0|step1 = D2|part1 = CD8068904599101}}

{{cpulist|lake-e|icelake_e|model = Xeon Platinum 8360Y|ark = 212459|cores = 36|threads = 72|turbo = {{frequency|3.5|GHz}}|mult = 24|l3 = 54|vmin =|vmax =|tdp = 250|upi = 11.2|mem = 8×DDR4-3200|date = 6 April 2021|sock = 4189|price = {{US$|5383|2021|long = no}}|links = 1|sspec1 = SRKHF|step1 = D2|part1 = CD8068904571901 }}

{{cpulist|lake-e|icelake_e|model = Xeon Platinum 8362|ark = 217216|cores = 32|threads = 64|turbo = {{frequency|3.6|GHz}}|mult = 28|l3 = 48|vmin =|vmax =|tdp = 265|upi = 11.2|mem = 8×DDR4-3200|date = 6 April 2021|sock = 4189|price = {{US$|6236|2021|long = no}}|links = 1|sspec1 = SRKY3|step1 = D2|part1 = CD8068904722404}}

{{cpulist|lake-e|icelake_e|model = Xeon Platinum 8368|ark = 212455|cores = 38|threads = 76|turbo = {{frequency|3.4|GHz}}|mult = 24|l3 = 57|vmin =|vmax =|tdp = 270|upi = 11.2|mem = 8×DDR4-3200|date = 6 April 2021|sock = 4189|price = {{US$|7214|2021|long = no}}|links = 1|sspec1 = SRKH8|step1 = D2|part1 = CD8068904572001}}

{{cpulist|lake-e|icelake_e|model = Xeon Platinum 8368Q|ark = 212289|cores = 38|threads = 76|turbo = {{frequency|3.7|GHz}}|mult = 26|l3 = 57|vmin =|vmax =|tdp = 270|upi = 11.2|mem = 8×DDR4-3200|date = 6 April 2021|sock = 4189|price = {{US$|7719|2021|long = no}}|links = 1|sspec1 = SRKHX|step1 = D2|part1 = CD8068904582803}}

{{cpulist|lake-e|icelake_e|model = Xeon Platinum 8380|ark = 212287|cores = 40|threads = 80|turbo = {{frequency|3.4|GHz}}|mult = 23|l3 = 60|vmin =|vmax =|tdp = 270|upi = 11.2|mem = 8×DDR4-3200|date = 6 April 2021|sock = 4189|price = {{US$|9359|2021|long = no}}|links = 1|sspec1 = SRKHR|step1 = D2|part1 = CD8068904572601 }}

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{{Expand section|date=July 2024}}

Intel announced the next generation of Xeon D, codenamed Ice Lake-D in April 2021.{{Cite web|url=https://newsroom.intel.com/news/new-intel-processors-accelerate-5g-network-transformation/|title=New Intel Processors Accelerate 5G Network Transformation}} Intel official launched the Xeon D D-2700 series and D-1700 series CPUs at MWC 2022.{{cite web | url=https://www.intel.com/content/www/us/en/newsroom/news/intel-launches-new-processor-built-edge.html | title=Intel Launches Xeon D Processor Built for the Network and Edge }} Xeon D D-2800 series and D-1800 series were announced on Dec 14, 2023.{{Cite web |title=Intel Announces Xeon E-2400 & Xeon D-1800/D-2800 CPUs |url=https://www.phoronix.com/news/Intel-Xeon-E-2400-D-2800 |access-date=2023-12-16 |website=www.phoronix.com |language=en}}

{{anchor|Ice Lake-W(uniprocessor)}} "Ice Lake-W3300" (10 nm)

• PCI Express lanes: 64
• Supports up to 16 DIMMs of DDR4 memory, maximum 4 TB.{{Cite web | url = https://www.anandtech.com/show/16822/intel-launches-xeon-w-3300-3365-ice-lake-workstations-38-core | title = Intel Launches Xeon W-3300: Ice Lake for Workstations, up to 38 Cores | first1 = Ian | last1 = Cutress | website = AnandTech |date = 2021-07-29 | language = en | archive-url = https://web.archive.org/web/20230510153259/https://www.anandtech.com/show/16822/intel-launches-xeon-w-3300-3365-ice-lake-workstations-38-core | archive-date = 2023-05-10 | url-status = live | access-date = 2023-05-17 | quote = All the processors will support 64 lanes of PCIe 4.0, 8-channel DDR4-3200 memory (up from 6-channel), and with 256 GB LRDIMMs up to 4 TB per socket (16 modules). | df = dmy-all }}