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List of ARM processors#Designed by third parties

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{{Use dmy dates|date=February 2015}}

This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.{{Cite web | url = http://infocenter.arm.com/help/topic/com.arm.doc.faqs/attached/6745/0141_5linecard.pdf | title = ARM Powered Standard Products | year = 2005 | access-date = 23 December 2017 | archive-url = https://web.archive.org/web/20171020195635/http://infocenter.arm.com/help/topic/com.arm.doc.faqs/attached/6745/0141_5linecard.pdf | archive-date = 20 October 2017 | url-status = dead }} Keil also provides a somewhat newer summary of vendors of ARM based processors.{{Cite web |author= ARM Ltd and ARM Germany GmbH |url= http://www.keil.com/dd/parms/arm.htm |title= Device Database |publisher= Keil |access-date= 6 January 2011 |archive-url= https://web.archive.org/web/20110110215343/http://www.keil.com/dd/parms/arm.htm |archive-date= 10 January 2011 |url-status= live }} ARM further provides a chart{{Cite web |url=http://www.arm.com/products/processors/ |title=Processors |publisher=ARM |year=2011 |access-date=6 January 2011 |archive-url=https://web.archive.org/web/20110117025703/http://www.arm.com/products/processors/ |archive-date=17 January 2011 |url-status=live }} displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM core families.

Processors

=Designed by ARM=

{{sticky header}}

class="wikitable sticky-header" style="text-align: center"
Product family

! ARM architecture

! Processor

! Feature

! Cache (I / D), MMU

! Typical MIPS @ MHz

! Reference

ARM1

| ARMv1

| ARM1

| First implementation

| None

|

|

ARM2

| ARMv2

| ARM2

| ARMv2 added the MUL (multiply) instruction

| None

| 0.33 DMIPS/MHz

|

rowspan=2 | ARM2aS

|rowspan=2 | ARMv2a

| ARM250

| Integrated MEMC (MMU), graphics and I/O processor. ARMv2a added the SWP and SWPB (swap) instructions

| None, MEMC1a

|

|

ARM3

| First integrated memory cache

| 4 KB unified

| 0.50 DMIPS/MHz

|

rowspan=3 | ARM6

| rowspan=3 | ARMv3

| ARM60

| ARMv3 first to support 32-bit memory address space (previously 26-bit).
ARMv3M first added long multiply instructions (32x32=64).

| None

| 10 MIPS @ 12 MHz

|

ARM600

| As ARM60, cache and coprocessor bus (for FPA10 floating-point unit)

| 4 KB unified

| 28 MIPS @ 33 MHz

|

ARM610

| As ARM60, cache, no coprocessor bus

| 4 KB unified

| 17 MIPS @ 20 MHz
0.65 DMIPS/MHz

|{{cite web |title=ARM610 Datasheet |url=http://bitsavers.org/pdf/acorn/ARM_DDI_0004D_ARM610_Data_Sheet_Aug93.pdf |date=August 1993 |website=ARM Holdings |access-date=January 29, 2019}}

rowspan=3 | ARM7

|rowspan=3 | ARMv3

| ARM700

| coprocessor bus (for FPA11 floating-point unit)

| 8 KB unified

| 40 MHz

|

ARM710

| As ARM700, no coprocessor bus

| 8 KB unified

| 40 MHz

|{{cite web |title=ARM710 Datasheet |url=http://bitsavers.org/pdf/acorn/ARM_DDI_0024C_ARM710_Data_Sheet_Jul94.pdf |date=July 1994 |website=ARM Holdings |access-date=January 29, 2019}}

ARM710a

| As ARM710, also used as core of ARM7100

| 8 KB unified

| 40 MHz
0.68 DMIPS/MHz

|

rowspan=4 | ARM7T

| rowspan=4 | ARMv4T

|ARM7TDMI(-S)

| 3-stage pipeline, Thumb, ARMv4 first to drop legacy ARM 26-bit addressing

| None

| 15 MIPS @ 16.8 MHz
63 DMIPS @ 70 MHz

|

ARM710T

| As ARM7TDMI, cache

| 8 KB unified, MMU

| 36 MIPS @ 40 MHz

|

ARM720T

| As ARM7TDMI, cache

| 8 KB unified, MMU with FCSE (Fast Context Switch Extension)

| 60 MIPS @ 59.8 MHz

|

ARM740T

| As ARM7TDMI, cache

|MPU

|

|

ARM7EJ

| ARMv5TEJ

| ARM7EJ-S

| 5-stage pipeline, Thumb, Jazelle DBX, enhanced DSP instructions

| None

|

|

ARM8

| ARMv4

| ARM810

| 5-stage pipeline, static branch prediction, double-bandwidth memory

| 8 KB unified, MMU

| 84 MIPS @ 72 MHz
1.16 DMIPS/MHz

|{{cite web | url = https://www.hotchips.org/wp-content/uploads/hc_archives/hc08/2_Mon/HC8.S4/HC8.4.1.pdf | title = ARM810 – Dancing to the Beat of a Different Drum | author = ARM Holdings | publisher = Hot Chips | date = 7 August 1996 | access-date = 14 November 2018 | archive-url = https://web.archive.org/web/20181224080542/https://www.hotchips.org/wp-content/uploads/hc_archives/hc08/2_Mon/HC8.S4/HC8.4.1.pdf | archive-date = 24 December 2018 | url-status = live }}{{cite news | url=http://www.eetimes.com/document.asp?doc_id=1208831 | title=VLSI Technology Now Shipping ARM810 | work=EE Times | date=26 August 1996 | access-date=21 September 2013 | archive-url=https://web.archive.org/web/20130926155924/http://www.eetimes.com/document.asp?doc_id=1208831 | archive-date=26 September 2013 | url-status=live }}

rowspan=4 | ARM9T

| rowspan=4 | ARMv4T

| ARM9TDMI

| 5-stage pipeline, Thumb

|None

|

|

ARM920T

| As ARM9TDMI, cache

| 16 KB / 16 KB, MMU with FCSE (Fast Context Switch Extension)

| 200 MIPS @ 180 MHz

|[http://infocenter.arm.com/help/topic/com.arm.doc.ddi0151c/I47491.html Register 13, FCSE PID register] {{Webarchive|url=https://web.archive.org/web/20110707164527/http://infocenter.arm.com/help/topic/com.arm.doc.ddi0151c/I47491.html |date=7 July 2011 }} ARM920T Technical Reference Manual

ARM922T

| As ARM9TDMI, caches

| 8 KB / 8 KB, MMU

|

|

ARM940T

| As ARM9TDMI, caches

| 4 KB / 4 KB, MPU

|

|

rowspan=5 | ARM9E

| rowspan=3 | ARMv5TE

| ARM946E-S

| Thumb, enhanced DSP instructions, caches

| Variable, tightly coupled memories, MPU

|

|

ARM966E-S

| Thumb, enhanced DSP instructions

| No cache, TCMs

|

|

ARM968E-S

| As ARM966E-S

| No cache, TCMs

|

|

ARMv5TEJ

| ARM926EJ-S

| Thumb, Jazelle DBX, enhanced DSP instructions

| Variable, TCMs, MMU

| 220 MIPS @ 200 MHz

|

ARMv5TE

| ARM996HS

| Clockless processor, as ARM966E-S

| No caches, TCMs, MPU

|

|

rowspan=3 | ARM10E

| rowspan=2 | ARMv5TE

| ARM1020E

| 6-stage pipeline, Thumb, enhanced DSP instructions, (VFP)

| 32 KB / 32 KB, MMU

|

|

ARM1022E

| As ARM1020E

| 16 KB / 16 KB, MMU

|

|

ARMv5TEJ

| ARM1026EJ-S

| Thumb, Jazelle DBX, enhanced DSP instructions, (VFP)

| Variable, MMU or MPU

|

|

rowspan=4 | ARM11

| ARMv6

| ARM1136J(F)-S

| 8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), enhanced DSP instructions, unaligned memory access

| Variable, MMU

| 740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz

|{{Cite web|url=http://www.arm.com/products/CPUs/ARM1136JF-S.html |title=ARM1136J(F)-S – ARM Processor |publisher=Arm.com |access-date=18 April 2009 |archive-url=https://web.archive.org/web/20090321200633/http://www.arm.com/products/CPUs/ARM1136JF-S.html |archive-date=21 March 2009}}

ARMv6T2

| ARM1156T2(F)-S

| 9-stage pipeline, SIMD, Thumb-2, (VFP), enhanced DSP instructions

| Variable, MPU

|

|{{cite web|url=https://www.arm.com/products/processors/classic/arm11/arm1156.php|title=ARM1156 Processor|website=Arm Holdings|archive-url=https://web.archive.org/web/20100213205149/https://www.arm.com/products/processors/classic/arm11/arm1156.php|archive-date=13 February 2010}}

ARMv6Z

| ARM1176JZ(F)-S

| As ARM1136EJ(F)-S

| Variable, MMU + TrustZone

| 965 DMIPS @ 772 MHz, up to 2,600 DMIPS with four processors

|{{Cite web |url = http://www.arm.com/products/processors/classic/arm11/ |title = ARM11 Processor Family |publisher = ARM |access-date = 12 December 2010 |archive-url = https://web.archive.org/web/20110115045355/http://www.arm.com/products/processors/classic/arm11/ |archive-date = 15 January 2011 |url-status = live }}

ARMv6K

| ARM11MPCore

| As ARM1136EJ(F)-S, 1–4 core SMP

| Variable, MMU

|

|

rowspan=3 | SecurCore

| ARMv6-M

| SC000

| As Cortex-M0

|

| 0.9 DMIPS/MHz

|

ARMv4T

| SC100

| As ARM7TDMI

|

|

|

ARMv7-M

| SC300

| As Cortex-M3

|

| 1.25 DMIPS/MHz

|

rowspan=12 | Cortex-M

| rowspan=3 | ARMv6-M

| Cortex-M0

| Microcontroller profile, most Thumb + some Thumb-2,{{cite web|url=http://archive.electronicdesign.com/files/29/20719/fig_01.gif|title=Cortex-M0/M0+/M1 Instruction set; ARM Holding.|archive-url=https://archive.today/20130418234149/http://archive.electronicdesign.com/files/29/20719/fig_01.gif|archive-date=18 April 2013}} hardware multiply instruction (optional small), optional system timer, optional bit-banding memory

| Optional cache, no TCM, no MPU

| 0.84 DMIPS/MHz

|{{Cite web |url=https://developer.arm.com/ip-products/processors/cortex-m/cortex-m0 |title=Cortex-M0 |website=Arm Developer |access-date=23 September 2020}}

Cortex-M0+

| Microcontroller profile, most Thumb + some Thumb-2, hardware multiply instruction (optional small), optional system timer, optional bit-banding memory

| Optional cache, no TCM, optional MPU with 8 regions

| 0.93 DMIPS/MHz

|{{cite web|url=https://developer.arm.com/ip-products/processors/cortex-m/cortex-m0-plus|title=Cortex-M0+|website=Arm Developer|access-date=23 September 2020}}

Cortex-M1

| Microcontroller profile, most Thumb + some Thumb-2, hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memory

| Optional cache, 0–1024 KB I-TCM, 0–1024 KB D-TCM, no MPU

| 136 DMIPS @ 170 MHz,{{cite press release |url=http://www.arm.com/news/17017.html |title=ARM Extends Cortex Family with First Processor Optimized for FPGA |publisher=ARM Holdings |date=19 March 2007 |access-date=11 April 2007 |archive-url=https://web.archive.org/web/20070505180243/http://www.arm.com/news/17017.html |archive-date=5 May 2007 |url-status=live }} (0.8 DMIPS/MHz FPGA-dependent){{cite web |url=http://www.arm.com/products/CPUs/ARM_Cortex-M1.html |title=ARM Cortex-M1 |publisher=ARM product website |access-date=11 April 2007 |archive-url=https://web.archive.org/web/20070401051142/http://www.arm.com/products/CPUs/ARM_Cortex-M1.html |archive-date=1 April 2007 |url-status=live }}

|{{Cite web |url=https://developer.arm.com/ip-products/processors/cortex-m/cortex-m1 |title=Cortex-M1 |website=Arm Developer |access-date=23 September 2020}}

ARMv7-M

| Cortex-M3

| Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memory

| Optional cache, no TCM, optional MPU with 8 regions

| 1.25 DMIPS/MHz

|{{Cite web |url=https://developer.arm.com/ip-products/processors/cortex-m/cortex-m3 |title=Cortex-M3 |website=Arm Developer |access-date=23 September 2020}}

rowspan=2 |ARMv7E-M

| Cortex-M4

| Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv4-SP single-precision FPU, hardware multiply and divide instructions, optional bit-banding memory

| Optional cache, no TCM, optional MPU with 8 regions

| 1.25 DMIPS/MHz (1.27 w/FPU)

|{{Cite web |url=https://developer.arm.com/ip-products/processors/cortex-m/cortex-m4 |title=Cortex-M4 |website=Arm Developer |access-date=23 September 2020}}

Cortex-M7

| Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv5 single and double precision FPU, hardware multiply and divide instructions

| 0−64 KB I-cache, 0−64 KB D-cache, 0–16 MB I-TCM, 0–16 MB D-TCM (all these w/optional ECC), optional MPU with 8 or 16 regions

| 2.14 DMIPS/MHz

|{{Cite web |url=https://developer.arm.com/ip-products/processors/cortex-m/cortex-m7 |title=Cortex-M7 |website=Arm Developer |access-date=23 September 2020}}

rowspan=1 |ARMv8-M Baseline

| Cortex-M23

| Microcontroller profile, Thumb-1 (most), Thumb-2 (some), Divide, TrustZone

| Optional cache, no TCM, optional MPU with 16 regions

| 1.03 DMIPS/MHz

|{{cite web |url=https://developer.arm.com/ip-products/processors/cortex-m/cortex-m23 |title=Cortex-M23 |website=Arm Developer |access-date=23 September 2020}}

rowspan=2 |ARMv8-M Mainline

| Cortex-M33

| Microcontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processor

| Optional cache, no TCM, optional MPU with 16 regions

| 1.50 DMIPS/MHz

|{{cite web |url=https://developer.arm.com/ip-products/processors/cortex-m/cortex-m33 |title=Cortex-M33 |website=Arm Developer |access-date=23 September 2020}}

Cortex-M35P

| Microcontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processor

| Built-in cache (with option 2–16 KB), I-cache, no TCM, optional MPU with 16 regions

| 1.50 DMIPS/MHz

|{{Cite web |url=https://developer.arm.com/ip-products/processors/cortex-m/cortex-m35p |title=Cortex-M35P |website=Arm Developer |access-date=29 April 2019 |archive-url=https://web.archive.org/web/20190508155414/https://developer.arm.com/ip-products/processors/cortex-m/cortex-m35p |archive-date=8 May 2019 |url-status=live }}

rowspan=3 |ARMv8.1-M Mainline

| Cortex-M52

|

|

| 1.60 DMIPS/MHz

|{{Cite web |url=https://developer.arm.com/ip-products/processors/cortex-m/cortex-m52 |title=Cortex-M52 |website=Arm Developer |access-date=23 November 2023}}

Cortex-M55

|

|

| 1.69 DMIPS/MHz

|{{Cite web |url=https://developer.arm.com/ip-products/processors/cortex-m/cortex-m55 |title=Cortex-M55 |website=Arm Developer |access-date=28 September 2020}}

Cortex-M85

|

|

| 3.13 DMIPS/MHz

|{{Cite web |url=https://developer.arm.com/Processors/Cortex-M85 |title=Cortex-M85 |website=Arm Developer |access-date=7 July 2022}}

rowspan="7" | Cortex-R

| rowspan=4 | ARMv7-R

| Cortex-R4

| Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstep with fault logic

| 0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt. MPU with 8/12 regions

| 1.67 DMIPS/MHz{{Cite web|url=https://developer.arm.com/products/processors/cortex-r|title=Cortex-R – Arm Developer|publisher=Arm Ltd.|website=ARM Developer|language=en|access-date=2018-03-29|archive-url=https://web.archive.org/web/20180330080449/https://developer.arm.com/products/processors/cortex-r|archive-date=30 March 2018|url-status=live}}

|{{Cite web |url=https://developer.arm.com/ip-products/processors/cortex-r/cortex-r4 |title=Cortex-R4 |website=Arm Developer |access-date=23 September 2020}}

Cortex-R5

| Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP){{Cite web |url=http://arm.com/products/arm-expands-unmatched-real-time-cortex-processor-portfolio.php |title=Cortex-R5 & Cortex-R7 Press Release; ARM Holdings; 31 January 2011. |access-date=13 June 2011 |archive-url=https://web.archive.org/web/20110707163818/http://arm.com/products/arm-expands-unmatched-real-time-cortex-processor-portfolio.php |archive-date=7 July 2011 |url-status=live }}

| 0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt. MPU with 12/16 regions

| 1.67 DMIPS/MHz

|{{Cite web |url=https://developer.arm.com/ip-products/processors/cortex-r/cortex-r5 |title=Cortex-R5 |website=Arm Developer |access-date=23 September 2020}}

Cortex-R7

| Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic / out-of-order execution / dynamic register renaming / optional as 2 independent cores, low-latency peripheral port (LLPP), ACP

| 0–64 KB / 0–64 KB, ? of 0–128 KB TCM, opt. MPU with 16 regions

| 2.50 DMIPS/MHz

|{{Cite web |url=https://developer.arm.com/ip-products/processors/cortex-r/cortex-r7 |title=Cortex-R7 |website=Arm Developer |access-date=23 September 2020}}

Cortex-R8

| TBD

| 0–64 KB / 0–64 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24 regions

| 2.50 DMIPS/MHz

|{{Cite web |url=https://developer.arm.com/ip-products/processors/cortex-r/cortex-r8 |title=Cortex-R8 |website=Arm Developer |access-date=23 September 2020}}

rowspan="3" |ARMv8-R

| Cortex-R52

| TBD

| 0–32 KB / 0–32 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24+24 regions

| 2.09 DMIPS/MHz

|{{Cite web|url=https://developer.arm.com/Processors/Cortex-R52|title=Cortex-R52|website=Arm Developer|access-date=23 November 2023|archive-url=https://web.archive.org/web/20231123232126/https://developer.arm.com/Processors/Cortex-R52|archive-date=23 November 2023|url-status=live}}

Cortex-R52+

| TBD

| 0–32 KB / 0–32 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24+24 regions

| 2.09 DMIPS/MHz

|{{Cite web|url=https://developer.arm.com/Processors/Cortex-R52%20Plus|title=Cortex-R52|website=Arm Developer|access-date=23 November 2023|archive-url=https://web.archive.org/web/20231123231818/https://developer.arm.com/Processors/Cortex-R52%20Plus|archive-date=23 November 2023|url-status=live}}

Cortex-R82

| TBD

| 16–128 KB /16–64 KB L1, 64K–1MB L2, 0.16–1 / 0.16–1 MB TCM,

opt MPU with 32+32 regions

| 3.41 DMIPS/MHz{{Cite web|title=Cortex-R82|url=https://developer.arm.com/ip-products/processors/cortex-r/cortex-r82|access-date=2020-09-30|website=Arm Developer|language=en}}

|{{Cite web|date=2020|title=Arm Cortex-R comparison Table_v2|url=https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Cortex-A%20R%20M%20datasheets/Arm%20Cortex-R%20Comparison%20Table_v2.pdf|access-date=2020-09-30|website=ARM Developer}}

rowspan=8 | Cortex-A
(32-bit)

| rowspan=7 | ARMv7-A

| Cortex-A5

| Application profile, ARM / Thumb / Thumb-2 / DSP / SIMD / Optional VFPv4-D16 FPU / Optional NEON / Jazelle RCT and DBX, 1–4 cores / optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)

| 4−64 KB / 4−64 KB L1, MMU + TrustZone

| 1.57 DMIPS/MHz per core

|{{Cite web |url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a5 |title=Cortex-A5 |website=Arm Developer |access-date=23 September 2020}}

Cortex-A7Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Jazelle RCT and DBX / Hardware virtualization, in-order execution, superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), architecture and feature set are identical to A15, 8–10 stage pipeline, low-power design{{cite news |url=https://www.theregister.co.uk/2011/10/20/details_on_big_little_processing/ |title=Deep inside ARM's new Intel killer |publisher=The Register |date=20 October 2011 |access-date=10 August 2017 |archive-url=https://web.archive.org/web/20170810205937/https://www.theregister.co.uk/2011/10/20/details_on_big_little_processing/ |archive-date=10 August 2017 |url-status=live }}

| 8−64 KB / 8−64 KB L1, 0–1 MB L2, MMU + TrustZone

| 1.9 DMIPS/MHz per core

|{{Cite web |url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a7 |title=Cortex-A7 |website=Arm Developer |access-date=23 September 2020}}

Cortex-A8

| Application profile, ARM / Thumb / Thumb-2 / VFPv3 FPU / NEON / Jazelle RCT and DAC, 13-stage superscalar pipeline

| 16–32 KB / 16–32 KB L1, 0–1 MB L2 opt. ECC, MMU + TrustZone

| Up to 2000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1 GHz)

|{{Cite web |url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a8 |title=Cortex-A8 |website=Arm Developer |access-date=23 September 2020}}

Cortex-A9Application profile, ARM / Thumb / Thumb-2 / DSP / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)

| 16–64 KB / 16–64 KB L1, 0–8 MB L2 opt. parity, MMU + TrustZone

| 2.5 DMIPS/MHz per core, 10,000 DMIPS @ 2 GHz on Performance Optimized TSMC 40G (dual-core)

|{{Cite web |url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a9 |title=Cortex-A9 |website=Arm Developer |access-date=23 September 2020}}

Cortex-A12Application profile, ARM / Thumb-2 / DSP / VFPv4 FPU / NEON / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)

| 32−64 KB

| 3.0 DMIPS/MHz per core

|{{Cite web |url=http://www.arm.com/products/processors/cortex-a/cortex-a12-processor.php |title=Cortex-A12 Summary; ARM Holdings. |access-date=3 June 2013 |archive-url=https://web.archive.org/web/20130607135127/http://www.arm.com/products/processors/cortex-a/cortex-a12-processor.php |archive-date=7 June 2013 |url-status=dead }}

Cortex-A15Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, 15-24 stage pipeline

| 32 KB w/parity / 32 KB w/ECC L1, 0–4 MB L2, L2 has ECC, MMU + TrustZone

| At least 3.5 DMIPS/MHz per core (up to 4.01 DMIPS/MHz depending on implementation){{Cite web |url=http://www.itproportal.com/2011/03/14/exclusive-arm-cortex-a15-40-cent-faster-cortex-a9/ |title=Exclusive : ARM Cortex-A15 "40 Per Cent" Faster Than Cortex-A9 {{!}} ITProPortal.com |access-date=13 June 2011 |archive-url=https://web.archive.org/web/20110721081000/http://www.itproportal.com/2011/03/14/exclusive-arm-cortex-a15-40-cent-faster-cortex-a9/ |archive-date=21 July 2011 |url-status=dead }}

|{{Cite web |url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a15 |title=Cortex-A15 |website=Arm Developer |access-date=23 September 2020}}

Cortex-A17Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP

| 32 KB L1, 256 KB–8 MB L2 w/optional ECC

| 2.8 DMIPS/MHz

|{{Cite web |url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a17 |title=Cortex-A17 |website=Arm Developer |access-date=23 September 2020}}

rowspan=1 | ARMv8-A

| Cortex-A32

| Application profile, AArch32, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline

| 8–64 KB w/optional parity / 8−64 KB w/optional ECC L1 per core, 128 KB–1 MB L2 w/optional ECC shared

|

|{{cite web | url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a32 | title=Cortex-A32 | website=Arm Developer | access-date=23 September 2020}}

rowspan="23" |Cortex-A
(64-bit)

| rowspan="6" |ARMv8-A

| Cortex-A34

| Application profile, AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline

| 8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–1 MB L2 shared, 40-bit physical addresses

|

|{{Cite web|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a34|title=Cortex-A34|website=Arm Developer|access-date=11 October 2019}}

Cortex-A35

| Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline

| 8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–1 MB L2 shared, 40-bit physical addresses

| 1.78 DMIPS/MHz

|{{cite web | url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a35 | title=Cortex-A35 | website=Arm Developer | access-date=23 September 2020}}

Cortex-A53

| Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline

| 8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–2 MB L2 shared, 40-bit physical addresses

| 2.3 DMIPS/MHz

|{{cite web | url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a53 | title=Cortex-A53 | website=Arm Developer | access-date=23 September 2020}}

Cortex-A57

| Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width decode superscalar, deeply out-of-order pipeline

| 48 KB w/DED parity / 32 KB w/ECC L1 per core; 512 KB–2 MB L2 shared w/ECC; 44-bit physical addresses

| 4.1–4.8 DMIPS/MHz{{cite web | url=http://www.bitkistl.com/2015/03/cortex-ax-vs-performnace.html | title=Cortex-Ax vs performance | access-date=5 May 2017 | archive-url=https://web.archive.org/web/20170615001530/http://www.bitkistl.com/2015/03/cortex-ax-vs-performnace.html | archive-date=15 June 2017 | url-status=live }}{{cite web | url=http://www.cnx-software.com/2015/04/09/relative-performance-of-arm-cortex-a-32-bit-and-64-bit-cores | title=Relative Performance of ARM Cortex-A 32-bit and 64-bit Cores | date=9 April 2015 | access-date=5 May 2017 | archive-url=https://web.archive.org/web/20170501055942/http://www.cnx-software.com/2015/04/09/relative-performance-of-arm-cortex-a-32-bit-and-64-bit-cores/ | archive-date=1 May 2017 | url-status=live }}

|{{cite web | url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a57 | title=Cortex-A57 | website=Arm Developer | access-date=23 September 2020}}

Cortex-A72

| Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width superscalar, deeply out-of-order pipeline

| 48 KB w/DED parity / 32 KB w/ECC L1 per core; 512 KB–2 MB L2 shared w/ECC; 44-bit physical addresses

|6.3-7.3 DMIPS/MHz{{Cite web |last=Sima |first=Dezső |date=November 2018 |title=ARM's processor lines |url=https://users.nik.uni-obuda.hu/sima/letoltes/Processor_families_Knowledge_Base_2019/ARM_processors_lecture_2018_12_02.pdf |access-date=26 May 2022 |website=University of Óbuda, Neumann Faculty}}

|{{cite web | url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a72 | title=Cortex-A72 | website=Arm Developer | access-date=23 September 2020}}

Cortex-A73

| Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width superscalar, deeply out-of-order pipeline

| 64 KB / 32−64 KB L1 per core, 256 KB–8 MB L2 shared w/ optional ECC, 44-bit physical addresses

| 7.4-8.5 DMIPS/MHz

|{{cite web | url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a73 | title=Cortex-A73 | website=Arm Developer | access-date=23 September 2020}}

rowspan="10" |ARMv8.2-A

| Cortex-A55

| Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline{{Cite web|url=https://nl.hardware.info/reviews/7394/4/preview-arms-nieuwe-cpu--en-gpu-architecturen-cortex-a55-efficientie|title=Hardware.Info Nederland|website=nl.hardware.info|language=nl|access-date=2017-11-27|archive-url=https://web.archive.org/web/20181224080550/https://nl.hardware.info/reviews/7394/4/preview-arms-nieuwe-cpu--en-gpu-architecturen-cortex-a55-efficientie|archive-date=24 December 2018|url-status=live}}

| 16−64 KB / 16−64 KB L1, 256 KB L2 per core, 4 MB L3 shared

| 3 DMIPS/MHz

|{{Cite web|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55|title=Cortex-A55|website=Arm Developer|access-date=23 September 2020}}

Cortex-A65

| Application profile, AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-wide decode superscalar, 3-width issue, out-of-order pipeline, SMT

|

|

|{{Cite web|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65|title=Cortex-A65|website=Arm Developer|access-date=3 October 2020}}

Cortex-A65AE

| As ARM Cortex-A65, adds dual core lockstep for safety applications

| 64 / 64 KB L1, 256 KB L2 per core, 4 MB L3 shared

|

|{{Cite web|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65ae|title=Cortex-A65AE|website=Arm Developer|access-date=11 October 2019}}

Cortex-A75

| Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width decode superscalar, deeply out-of-order pipeline{{Cite web|url=https://nl.hardware.info/reviews/7394/5/preview-arms-nieuwe-cpu--en-gpu-architecturen-cortex-a75-high-performancen|title=Hardware.Info Nederland|website=nl.hardware.info|language=nl|access-date=2017-11-27|archive-url=https://web.archive.org/web/20181224080458/https://nl.hardware.info/reviews/7394/5/preview-arms-nieuwe-cpu--en-gpu-architecturen-cortex-a75-high-performancen|archive-date=24 December 2018|url-status=live}}

| 64 / 64 KB L1, 512 KB L2 per core, 4 MB L3 shared

| 8.2-9.5 DMIPS/MHz

|{{Cite web|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a75|title=Cortex-A75|website=Arm Developer|access-date=23 September 2020}}

Cortex-A76

| Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 8-way issue, 13 stage pipeline, deeply out-of-order pipeline{{Cite web|url=https://anandtech.com/show/12785/arm-cortex-a76-cpu-unveiled-7nm-powerhouse/2|title=Arm's Cortex-A76 CPU Unveiled: Taking Aim at the Top for 7nm|website=AnandTech|access-date=2018-11-15|archive-url=https://web.archive.org/web/20181116000840/https://www.anandtech.com/show/12785/arm-cortex-a76-cpu-unveiled-7nm-powerhouse/2|archive-date=16 November 2018|url-status=live}}

| 64 / 64 KB L1, 256−512 KB L2 per core, 512 KB−4 MB L3 shared

| 10.7-12.4 DMIPS/MHz

|{{Cite web|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a76|title=Cortex-A76|website=Arm Developer|access-date=23 September 2020}}

Cortex-A76AE

| As ARM Cortex-A76, adds dual core lockstep for safety applications

|

|

|{{Cite web|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a76ae|title=Cortex-A76AE|website=Arm Developer|access-date=29 September 2020}}

Cortex-A77

| Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 6-width instruction fetch, 12-way issue, 13 stage pipeline, deeply out-of-order pipeline

| 1.5K L0 MOPs cache, 64 / 64 KB L1, 256−512 KB L2 per core, 512 KB−4 MB L3 shared

| 13-16 DMIPS/MHzAccording to ARM, the Cortex-A77 has a 20% IPC single-thread performance improvement over its predecessor in Geekbench 4, 23% in SPECint2006, 35% in SPECfp2006, 20% in SPECint2017, and 25% in SPECfp2017

|{{Cite web|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a77|title=Cortex-A77|website=Arm Developer|access-date=16 June 2019}}

Cortex-A78

|

|

|

|{{Cite web|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a78|title=Cortex-A78|website=Arm Developer|access-date=29 September 2020}}

Cortex-A78AE

| As ARM Cortex-A78, adds dual core lockstep for safety applications

|

|

|{{Cite web|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a78ae|title=Cortex-A78AE|website=Arm Developer|access-date=30 September 2020}}

Cortex-A78C

|

|

|

|{{Cite web|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a78c|title=Cortex-A78C|website=Arm Developer|access-date=26 November 2020}}

rowspan="3" |ARMv9-A

| Cortex-A510

|

|

|

|{{Cite web |title=Cortex-A510|url=https://developer.arm.com/Processors/Cortex-A510 |access-date=2024-10-11 |website=developer.arm.com}}

Cortex-A710

|

|

|

|{{Cite web|title=First Armv9 Cortex CPUs for Consumer Compute|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/first-armv9-cpu-cores|access-date=2021-08-24|website=community.arm.com|language=en}}

Cortex-A715

|

|

|

|{{Cite web |title=Cortex-A715|url=https://developer.arm.com/Processors/Cortex-A715 |access-date=2024-10-11 |website=developer.arm.com}}

rowspan="4" |ARMv9.2-A

| Cortex-A320

|

|

|

|{{Cite web |title=Cortex-A320|url=https://developer.arm.com/Processors/Cortex-A320 |access-date=2025-02-26 |website=developer.arm.com}}

Cortex-A520

|

|

|

|{{Cite web |title=Cortex-A520|url=https://developer.arm.com/Processors/Cortex-A520 |access-date=2024-10-11 |website=developer.arm.com}}

Cortex-A720

|

|

|

|{{Cite web |title=Cortex-A720|url=https://developer.arm.com/Processors/Cortex-A720 |access-date=2024-10-11 |website=developer.arm.com}}

Cortex-A725

|

|

|

|{{Cite web |title=Cortex-A725|url=https://developer.arm.com/Processors/Cortex-A725 |access-date=2024-10-11 |website=developer.arm.com}}

rowspan="5" |Cortex-X

| ARMv8.2-A

| Cortex-X1

| Performance-tuned variant of Cortex-A78

|

|

|

rowspan="2" |ARMv9-A

| Cortex-X2

|

|64 / 64 KB L1, 512–1024 KiB L2 per core, 512 KiB–8 MiB L3 shared

|

|{{Cite web |title=Cortex-X2|url=https://developer.arm.com/documentation/101803/0201/ |access-date=2024-10-11 |website=developer.arm.com}}

Cortex-X3

|

|64 / 64 KB L1, 512–2048 KiB L2 per core, 512 KiB–16 MiB L3 shared

|

|{{Cite web |title=Cortex-X3|url=https://developer.arm.com/documentation/101593/0102 |access-date=2024-10-11 |website=developer.arm.com}}

rowspan="2" |ARMv9.2-A

| Cortex-X4

|

|64 / 64 KB L1, 512–2048 KiB L2 per core, 512 KiB–32 MiB L3 shared

|

|{{Cite web |title=Cortex-X4|url=https://developer.arm.com/documentation/102484/0002/ |access-date=2024-10-11 |website=developer.arm.com}}

Cortex-X925

|

|

|

|{{Cite web |title=Cortex-X925|url=https://developer.arm.com/documentation/102807/0001/ |access-date=2024-10-11 |website=developer.arm.com}}

rowspan="7" |Neoverse

| rowspan="2" |ARMv8.2-A

| Neoverse N1

| Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 8-way dispatch/issue, 13 stage pipeline, deeply out-of-order pipeline

| 64 / 64 KB L1, 512−1024 KB L2 per core, 2−128 MB L3 shared, 128 MB system level cache

|

|{{Cite web|url=https://developer.arm.com/ip-products/processors/neoverse/neoverse-n1|title=Neoverse N1|website=Arm Developer|access-date=16 June 2019}}

Neoverse E1

| Application profile, AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-wide decode superscalar, 3-width issue, 10 stage pipeline, out-of-order pipeline, SMT

| 32−64 KB / 32−64 KB L1, 256 KB L2 per core, 4 MB L3 shared

|

|{{Cite web|url=https://developer.arm.com/ip-products/processors/neoverse/neoverse-e1|title=Neoverse E1|website=Arm Developer|access-date=3 October 2020}}

ARMv8.4-A

| Neoverse V1

|

|

|

|{{Cite web |title=Neoverse V1 |url=https://developer.arm.com/Processors/Neoverse%20V1 |access-date=2022-08-30 |website=developer.arm.com}}

rowspan="2" |ARMv9-A

| Neoverse N2

|

|

|

|{{Cite web |title=Neoverse N2 |url=https://developer.arm.com/Processors/Neoverse%20N2 |access-date=2022-08-30 |website=developer.arm.com}}

Neoverse V2

|

|

|

|{{Cite web |title=Neoverse V2 |url=https://developer.arm.com/Processors/Neoverse%20V2 |access-date=2022-05-08 |website=developer.arm.com}}

rowspan="2" |ARMv9.2-A

| Neoverse N3

|

|

|

|{{Cite web |title=Neoverse N3|url=https://developer.arm.com/Processors/Neoverse%20N3 |access-date=2024-05-08 |website=developer.arm.com}}

Neoverse V3

|

|

|

|{{Cite web |title=Neoverse V3 |url=https://developer.arm.com/Processors/Neoverse%20V3 |access-date=2022-05-08 |website=developer.arm.com}}

ARM family

! ARM architecture

! ARM core

! Feature

! Cache (I / D), MMU

! Typical MIPS @ MHz

! Reference

=Designed by third parties=

These cores implement the ARM instruction set, and were developed independently by companies with an architectural license from ARM.

{{sticky header}}

class="wikitable sticky-header" style="text-align: center"
Product family

! ARM architecture

! Processor

! Feature

! Cache (I / D), MMU

! Typical MIPS @ MHz

rowspan=2 | StrongARM
(Digital)

| rowspan=2 | ARMv4

| SA-110

| 5-stage pipeline

| 16 KB / 16 KB, MMU

| 100–233 MHz
1.0 DMIPS/MHz

SA-1100

| derivative of the SA-110

| 16 KB / 8 KB, MMU

|

rowspan=7 | Faraday{{cite web|url=http://www.faraday-tech.com/html/Product/IPProduct/ProcessorCores/index.htm|title=Processor Cores|publisher=Faraday Technology|access-date=19 February 2015|archive-url=https://web.archive.org/web/20150219233845/http://www.faraday-tech.com/html/Product/IPProduct/ProcessorCores/index.htm|archive-date=19 February 2015|url-status=dead}}
(Faraday Technology)

| rowspan=3 | ARMv4 || FA510 || rowspan=2 | 6-stage pipeline || Up to 32 KB / 32 KB cache, MPU || 1.26 DMIPS/MHz
100–200 MHz

FA526Up to 32 KB / 32 KB cache, MMU1.26 MIPS/MHz
166–300 MHz
FA6268-stage pipeline32 KB / 32 KB cache, MMU1.35 DMIPS/MHz
500 MHz
rowspan=4 | ARMv5TEFA606TE5-stage pipelineNo cache, no MMU1.22 DMIPS/MHz
200 MHz
FA626TE8-stage pipelinerowspan=3 |32 KB / 32 KB cache, MMU1.43 MIPS/MHz
800 MHz
FMP626TE8-stage pipeline, SMP1.43 MIPS/MHz
500 MHz
FA726TE13 stage pipeline, dual issue2.4 DMIPS/MHz
1000 MHz
rowspan=3 | XScale
(Intel / Marvell)

| rowspan=3 | ARMv5TE

| XScale

| 7-stage pipeline, Thumb, enhanced DSP instructions

| 32 KB / 32 KB, MMU

| 133–400 MHz

Bulverde

| Wireless MMX, wireless SpeedStep added

| 32 KB / 32 KB, MMU

| 312–624 MHz

Monahans{{Cite web|title=3rd Generation Intel XScale Microarchitecture: Developer's Manual|url=http://download.intel.com/design/intelxscale/31628302.pdf|work=download.intel.com|publisher=Intel|access-date=2 December 2010|date=May 2007|archive-url=https://web.archive.org/web/20080225120503/http://download.intel.com/design/intelxscale/31628302.pdf|archive-date=25 February 2008|url-status=live}}

| Wireless MMX2 added

| 32 KB / 32 KB L1, optional L2 cache up to 512 KB, MMU

| Up to 1.25 GHz

rowspan=4 | Sheeva
(Marvell)

| rowspan=3 | ARMv5 || Feroceon || 5–8 stage pipeline, single-issue || 16 KB / 16 KB, MMU || rowspan=2|600–2000 MHz

Jolteon5–8 stage pipeline, dual-issue32 KB / 32 KB, MMU
PJ1 (Mohawk)5–8 stage pipeline, single-issue, Wireless MMX232 KB / 32 KB, MMU1.46 DMIPS/MHz
1.06 GHz
ARMv6 / ARMv7-APJ46–9 stage pipeline, dual-issue, Wireless MMX2, SMP32 KB / 32 KB, MMU2.41 DMIPS/MHz
1.6 GHz
rowspan=3 | Snapdragon
(Qualcomm)

| rowspan=2 | ARMv7-A

| Scorpion{{Cite web |url=https://www.anandtech.com/show/4940/qualcomm-new-snapdragon-s4-msm8960-krait-architecture |title=Qualcomm's New Snapdragon S4: MSM8960 & Krait Architecture Explored |website=AnandTech |access-date=23 September 2020}}

| 1 or 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv3 FPU / NEON (128-bit wide)

|256 KB L2 per core

|2.1 DMIPS/MHz per core

Krait

| 1, 2, or 4 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON (128-bit wide)

|4 KB / 4 KB L0, 16 KB / 16 KB L1, 512 KB L2 per core

|3.3 DMIPS/MHz per core

rowspan=1 | ARMv8-A

| Kryo{{cite web |url=https://www.qualcomm.com/news/snapdragon/2015/09/02/snapdragon-820-and-kryo-cpu-heterogeneous-computing-and-role-custom |title=Snapdragon 820 and Kryo CPU: heterogeneous computing and the role of custom compute |publisher=Qualcomm |date=2015-09-02 |access-date=2015-09-06 |archive-url=https://web.archive.org/web/20150905203003/https://www.qualcomm.com/news/snapdragon/2015/09/02/snapdragon-820-and-kryo-cpu-heterogeneous-computing-and-role-custom |archive-date=5 September 2015 |url-status=live }}

| 4 cores.

?Up to 2.2 GHz

(6.3 DMIPS/MHz)

rowspan=12 | A series
(Apple)

| rowspan=1 | ARMv7-A

| Swift{{cite web|url=http://www.anandtech.com/show/6292/iphone-5-a6-not-a15-custom-core|title=The iPhone 5's A6 SoC: Not A15 or A9, a Custom Apple Core Instead|publisher=AnandTech|date=15 September 2012|access-date=15 September 2012|first=Anand|last=Lal Shimpi|archive-url=https://web.archive.org/web/20120915203513/http://www.anandtech.com/show/6292/iphone-5-a6-not-a15-custom-core|archive-date=15 September 2012|url-status=live}}

| 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON

|L1: 32 KB / 32 KB, L2: 1 MB shared

|3.5 DMIPS/MHz per core

ARMv8-ACyclone{{cite web|url=http://www.anandtech.com/show/8716/apple-a8xs-gpu-gxa6850-even-better-than-i-thought|title=Apple A8X's GPU - GAX6850, Even Better Than I Thought|first=Ryan|last=Smith|date=November 11, 2014|website=AnandTech|access-date=29 November 2014|archive-url=https://web.archive.org/web/20141130014356/http://www.anandtech.com/show/8716/apple-a8xs-gpu-gxa6850-even-better-than-i-thought|archive-date=30 November 2014|url-status=live}}2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64. Out-of-order, superscalar.L1: 64 KB / 64 KB, L2: 1 MB shared
SLC: 4 MB		1.3 or 1.4 GHz
ARMv8-ATyphoon{{cite web |url=http://www.anandtech.com/show/9443/apple-refreshes-the-ipod-touch-with-a8-soc-and-new-camera |title=Apple Refreshes The iPod Touch With A8 SoC And New Cameras |first=Brandon |last=Chester |date=July 15, 2015 |website=AnandTech |access-date=September 11, 2015 |archive-url=https://web.archive.org/web/20150905232041/http://anandtech.com/show/9443/apple-refreshes-the-ipod-touch-with-a8-soc-and-new-camera |archive-date=5 September 2015 |url-status=live }}2 or 3 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64L1: 64 KB / 64 KB, L2: 1 MB or 2 MB shared
SLC: 4 MB		1.4 or 1.5 GHz
ARMv8-ATwister{{cite web |url=http://www.anandtech.com/show/9662/iphone-6s-and-iphone-6s-plus-preliminary-results |title=iPhone 6s and iPhone 6s Plus Preliminary Results |first=Joshua |last=Ho |date=September 28, 2015 |website=AnandTech |access-date=December 18, 2015 |archive-url=https://web.archive.org/web/20160526001956/http://www.anandtech.com/show/9662/iphone-6s-and-iphone-6s-plus-preliminary-results |archive-date=26 May 2016 |url-status=live }}2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64L1: 64 KB / 64 KB, L2: 2 MB shared
SLC: 4 MB or 0 MB		1.85 or 2.26 GHz
ARMv8-AHurricane and Zephyr{{cite web |url=http://www.anandtech.com/show/10685/the-iphone-7-and-iphone-7-plus-review |title=The iPhone 7 and iPhone 7 Plus Review |first=Joshua |last=Ho |date=September 28, 2015 |website=AnandTech |access-date=September 14, 2017 |archive-url=https://web.archive.org/web/20170914220425/http://www.anandtech.com/show/10685/the-iphone-7-and-iphone-7-plus-review |archive-date=14 September 2017 |url-status=live }}Hurricane: 2 or 3 cores. AArch64, out-of-order, superscalar, 6-decode, 6-issue, 9-wide
Zephyr: 2 or 3 cores. AArch64, out-of-order, superscalar.		L1: 64 KB / 64 KB, L2: 3 MB or 8 MB shared
L1: 32 KB / 32 KB. L2: none
SLC: 4 MB or 0 MB		2.34 or 2.38 GHz
1.05 GHz
ARMv8.2-AMonsoon and Mistral{{cite web |url=https://en.wikichip.org/wiki/apple/ax/a11 |title=A11 Bionic - Apple |publisher=WikiChip |access-date=February 1, 2019}}Monsoon: 2 cores. AArch64, out-of-order, superscalar, 7-decode, ?-issue, 11-wide
Mistral: 4 cores. AArch64, out-of-order, superscalar. Based on Swift.		L1I: 128 KB, L1D: 64 KB, L2: 8 MB shared
L1: 32 KB / 32 KB, L2: 1 MB shared
SLC: 4 MB		2.39 GHz
1.70 GHz
ARMv8.3-AVortex and Tempest{{cite web |url=https://www.anandtech.com/show/13392/the-iphone-xs-xs-max-review-unveiling-the-silicon-secrets/ |title=The iPhone XS & XS Max Review: Unveiling the Silicon Secrets |website=AnandTech |access-date=February 11, 2019 |archive-url=https://web.archive.org/web/20190212070449/https://www.anandtech.com/show/13392/the-iphone-xs-xs-max-review-unveiling-the-silicon-secrets/ |archive-date=12 February 2019 |url-status=live }}Vortex: 2 or 4 cores. AArch64, out-of-order, superscalar, 7-decode, ?-issue, 11-wide
Tempest: 4 cores. AArch64, out-of-order, superscalar, 3-decode. Based on Swift.		L1: 128 KB / 128 KB, L2: 8 MB shared
L1: 32 KB / 32 KB, L2: 2 MB shared
SLC: 8 MB		2.49 GHz
1.59 GHz
ARMv8.4-ALightning and Thunder{{Cite web|url=https://www.anandtech.com/show/14892/the-apple-iphone-11-pro-and-max-review|title=The Apple iPhone 11, 11 Pro & 11 Pro Max Review: Performance, Battery, & Camera Elevated|last=Frumusanu|first=Andrei|website=AnandTech|access-date=2019-10-20}}Lightning: 2 cores. AArch64, out-of-order, superscalar, 7-decode, ?-issue, 11-wide
Thunder: 4 cores. AArch64, out-of-order, superscalar.		L1: 128 KB / 128 KB, L2: 8 MB shared
L1: 32 KB / 48 KB, L2: 4 MB shared
SLC: 16 MB		2.66 GHz
1.73 GHz
ARMv8.5-AFirestorm and Icestorm{{Cite web|url=https://www.anandtech.com/show/16192/the-iphone-12-review|title= The iPhone 12 & 12 Pro Review: New Design and Diminishing Returns |last=Frumusanu|first=Andrei|website=AnandTech|access-date=2021-04-05}}Firestorm: 2 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Icestorm: 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 7-wide.		L1: 192 KB / 128 KB, L2: 8 MB shared
L1: 128 KB / 64 KB, L2: 4 MB shared
SLC: 16 MB		3.0 GHz
1.82 GHz
ARMv8.6-AAvalanche and BlizzardAvalanche: 2 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Blizzard: 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.		L1: 192 KB / 128 KB, L2: 12 MB shared
L1: 128 KB / 64 KB, L2: 4 MB shared
SLC: 32 MB		2.93 or 3.23 GHz
2.02 GHz
ARMv8.6-AEverest and SawtoothEverest: 2 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Sawtooth: 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.		L1: 192 KB / 128 KB, L2: 16 MB shared
L1: 128 KB / 64 KB, L2: 4 MB shared
SLC: 24 MB		3.46 GHz
2.02 GHz
ARMv8.6-AApple A17 ProApple A17 Pro (P-cores): 2 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Apple A17 Pro (E-cores): 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.		L1: 192 KB / 128 KB, L2: 16 MB shared
L1: 128 KB / 64 KB, L2: 4 MB shared
SLC: 24 MB		3.78 GHz
2.11 GHz
rowspan=4 | M series
(Apple)

| ARMv8.5-A || Firestorm and Icestorm || Firestorm: 4, 6, 8 or 16 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Icestorm: 2 or 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 7-wide.|| L1: 192 KB / 128 KB, L2: 12, 24 or 48 MB shared
L1: 128 KB / 64 KB, L2: 4 or 8 MB shared
SLC: 8, 24, 48 or 96 MB || 3.2-3.23 GHz
2.06 GHz

ARMv8.6-AAvalanche and BlizzardAvalanche: 4, 6, 8 or 16 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Blizzard: 4 or 8 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.		L1: 192 KB / 128 KB, L2: 16, 32 or 64 MB shared
L1: 128 KB / 64 KB, L2: 4 or 8 MB shared
SLC: 8, 24, 48 or 96 MB		3.49 GHz
2.42 GHz
ARMv8.6-AApple M3Apple M3 (P-cores): 4, 5, 6, 10, 12 or 16 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Apple M3 (E-cores): 4 or 6 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.		L1: 192 KB / 128 KB, L2: 16, 32 or 64 MB shared
L1: 128 KB / 64 KB, L2: 4 or 8 MB shared
SLC: 8, 24, 48 or 96 MB		4.05 GHz
2.75 GHz
ARMv9.2-AApple M4Apple M4 (P-cores): 3 or 4 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Apple M4 (E-cores): 6 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.		L1: 192 KB / 128 KB, L2: 16, 32 or 64 MB shared
L1: 128 KB / 64 KB, L2: 4 or 8 MB shared
SLC: 8, 24, 48 or 96 MB		4.40 GHz
2.85 GHz
X-Gene
(Applied Micro)

| ARMv8-A ||X-Gene || 64-bit, quad issue, SMP, 64 cores{{Cite web |url=http://www.pcworld.com/article/2464600/appliedmicros-64core-chip-could-spark-off-arm-core-war.html |title=AppliedMicro's 64-core chip could spark off ARM core war copy |date=12 August 2014 |access-date=21 August 2014 |archive-url=https://web.archive.org/web/20140821175759/http://www.pcworld.com/article/2464600/appliedmicros-64core-chip-could-spark-off-arm-core-war.html |archive-date=21 August 2014 |url-status=live }} || Cache, MMU, virtualization || 3 GHz (4.2 DMIPS/MHz per core)

Denver
(Nvidia)

| ARMv8-A || Denver{{Cite web |url=http://www.anandtech.com/Gallery/Album/3847 |title=NVIDIA Denver Hot Chips Disclosure |access-date=29 November 2014 |archive-url=https://web.archive.org/web/20141205022933/http://www.anandtech.com/Gallery/Album/3847 |archive-date=5 December 2014 |url-status=live }}{{Cite web |url=http://blogs.nvidia.com/blog/2014/08/11/tegra-k1-denver-64-bit-for-android/ |title=Mile High Milestone: Tegra K1 "Denver" Will Be First 64-bit ARM Processor for Android |access-date=29 November 2014 |archive-url=https://web.archive.org/web/20140812090907/http://blogs.nvidia.com/blog/2014/08/11/tegra-k1-denver-64-bit-for-android/ |archive-date=12 August 2014 |url-status=live }} || 2 cores. AArch64, 7-wide superscalar, in-order, dynamic code optimization, 128 MB optimization cache,
Denver1: 28 nm, Denver2:16 nm || 128 KB I-cache / 64 KB D-cache || Up to 2.5 GHz

Carmel
(Nvidia)

| ARMv8.2-A || Carmel{{Cite web |url=https://www.golem.de/news/nvidia-drive-xavier-fuer-autonome-autos-wird-ausgeliefert-1801-132035.html |title=Drive Xavier für autonome Autos wird ausgeliefert |language=de |access-date=5 March 2018 |archive-url=https://web.archive.org/web/20180305202753/https://www.golem.de/news/nvidia-drive-xavier-fuer-autonome-autos-wird-ausgeliefert-1801-132035.html |archive-date=5 March 2018 |url-status=live }}{{Cite web |url=https://wccftech.com/nvidia-drive-xavier-soc-detailed/ |title=NVIDIA Drive Xavier SOC Detailed – A Marvel of Engineering, Biggest and Most Complex SOC Design To Date With 9 Billion Transistors |date=8 January 2018 |access-date=5 March 2018 |archive-url=https://web.archive.org/web/20180224191519/https://wccftech.com/nvidia-drive-xavier-soc-detailed/ |archive-date=24 February 2018 |url-status=live }} || 2 cores. AArch64, 10-wide superscalar, in-order, dynamic code optimization, ? MB optimization cache,
functional safety, dual execution, parity & ECC || ? KB I-cache / ? KB D-cache || Up to ? GHz

ThunderX
(Cavium)

| ARMv8-A || ThunderX || 64-bit, with two models with 8–16 or 24–48 cores (×2 w/two chips) || ? || Up to 2.2 GHz

K12
(AMD)

| ARMv8-A || K12{{Cite web |url=http://www.anandtech.com/show/7990/amd-announces-k12-core-custom-64bit-arm-design-in-2016 |title=AMD Announces K12 Core: Custom 64-bit ARM Design in 2016 |access-date=26 June 2015 |archive-url=https://web.archive.org/web/20150626102331/http://www.anandtech.com/show/7990/amd-announces-k12-core-custom-64bit-arm-design-in-2016 |archive-date=26 June 2015 |url-status=live }} || ? || ? || ?

rowspan="5" | Exynos
(Samsung)

| ARMv8-A || M1 ("Mongoose"){{cite web|url=https://www.anandtech.com/show/9781/samsung-announces-exynos-8890-with-cat1213-modem-and-custom-cpu|title=Samsung Announces Exynos 8890 with Cat.12/13 Modem and Custom CPU|website=AnandTech|access-date=23 September 2020}} || 4 cores. AArch64, 4-wide, quad-issue, superscalar, out-of-order || 64 KB I-cache / 32 KB D-cache, L2: 16-way shared 2 MB || 5.1 DMIPS/MHz

(2.6 GHz)

ARMv8-AM2 ("Mongoose")4 cores. AArch64, 4-wide, quad-issue, superscalar, out-of-order64 KB I-cache / 32 KB D-cache, L2: 16-way shared 2 MB2.3 GHz
ARMv8-A

| M3 ("Meerkat"){{cite web|url=https://www.anandtech.com/show/13199/hot-chips-2018-samsungs-exynosm3-cpu-architecture-deep-dive|title=Hot Chips 2018: Samsung's Exynos-M3 CPU Architecture Deep Dive|work=AnandTech|access-date=20 August 2018|archive-url=https://web.archive.org/web/20180820203929/https://www.anandtech.com/show/13199/hot-chips-2018-samsungs-exynosm3-cpu-architecture-deep-dive|archive-date=20 August 2018|url-status=live}}

| 4 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order

64 KB I-cache / 64 KB D-cache, L2: 8-way private 512 KB, L3: 16-way shared 4 MB2.7 GHz
ARMv8.2-A

| M4 ("Cheetah"){{cite web|url=https://www.anandtech.com/show/15826/isca-2020-evolution-of-the-samsung-exynos-cpu-microarchitecture|title=ISCA 2020: Evolution of the Samsung Exynos CPU Microarchitecture|work=AnandTech|date=3 June 2020|access-date=27 December 2021}}

| 2 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order

| 64 KB I-cache / 64 KB D-cache, L2: 8-way private 1 MB, L3: 16-way shared 3 MB

| 2.73 GHz

ARMv8.2-A

| M5 ("Lion")

| 2 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order

| 64 KB I-cache / 64 KB D-cache, L2: 8-way shared 2 MB, L3: 12-way shared 3 MB

| 2.73 GHz

Timeline

The following table lists each core by the year it was announced.{{Cite web |url=http://www.arm.com/about/company-profile/milestones.php |title=ARM Company Milestones. |access-date=6 April 2014 |archive-url=https://web.archive.org/web/20140328171411/http://www.arm.com/about/company-profile/milestones.php |archive-date=28 March 2014 |url-status=live }}{{Cite web |url=http://www.arm.com/about/newsroom/index.php |title=ARM Press Releases. |access-date=6 April 2014 |archive-url=https://web.archive.org/web/20140409172237/http://arm.com/about/newsroom/index.php |archive-date=9 April 2014 |url-status=live }}

:;ARM Classic

{{sticky header}}

class="wikitable sortable sticky-header-multi" border="1"
rowspan=2 | Year

! colspan=7 | Classic cores

ARM1-3ARM6ARM7ARM8ARM9ARM10ARM11
1985

| ARM1 || || || || || ||

1986

| ARM2 || || || || || ||

1989

| ARM3 || || || || || ||

1992

| ARM250 || || || || || ||

1993

| || ARM60
ARM610 || ARM700 || || || ||

1994

| || || ARM710
ARM7DI
ARM7TDMI || || || ||

1995

| || || ARM710a || || || ||

1996

| || || || ARM810 || || ||

1997

| || || ARM710T
ARM720T
ARM740T || || || ||

1998

| || || || || ARM9TDMI
ARM940T || ||

1999

| || || || || ARM9E-S
ARM966E-S || ||

2000

| || || || || ARM920T
ARM922T
ARM946E-S || ARM1020T ||

2001

| || || ARM7EJ-S
ARM7TDMI-S || || ARM9EJ-S
ARM926EJ-S || ARM1020E
ARM1022E ||

2002

| || || || || || ARM1026EJ-S || ARM1136J(F)-S

2003

| || || || || ARM968E-S || || ARM1156T2(F)-S
ARM1176JZ(F)-S

2004

| || || || || || ||

2005

| || || || || || || ARM11MPCore

2006

| || || || || ARM996HS || ||

:;ARM Cortex / Neoverse

{{sticky header}}

class="wikitable sortable sticky-header-multi" border="1"
rowspan=2 | Year

! colspan=5 | Cortex cores

! Neoverse cores

Microcontroller
(Cortex-M)		Real-time
(Cortex-R)		Application
(Cortex-A)
(32-bit)		Application
(Cortex-A)
(64-bit)		Application
(Cortex-X)
(64-bit)		Application
(Neoverse)
(64-bit)
2004

| Cortex-M3 || || || || ||

2005

| || || Cortex-A8 || || ||

2006

| || || || || ||

2007

| Cortex-M1 || || Cortex-A9 || || ||

2008

| || || || || ||

2009

| Cortex-M0 || || Cortex-A5 || || ||

2010

| Cortex-M4(F) || || Cortex-A15 || || ||

2011

| || Cortex-R4(F)
Cortex-R5(F)
Cortex-R7(F) || Cortex-A7 || || ||

2012

| Cortex-M0+ || || || Cortex-A53
Cortex-A57 || ||

2013

| || || Cortex-A12 || || ||

2014

| Cortex-M7(F) || || Cortex-A17 || || ||

2015

| || || || Cortex-A35
Cortex-A72 || ||

2016

| Cortex-M23
Cortex-M33(F) || Cortex-R8(F)
Cortex-R52(F) || Cortex-A32 || Cortex-A73 || ||

2017

| || || || Cortex-A55
Cortex-A75 || ||

2018

| Cortex-M35P(F) || || || Cortex-A65
Cortex-A65AE
Cortex-A76
Cortex-A76AE || ||

2019

| || || Cortex-A34 || Cortex-A77 || || Neoverse E1
Neoverse N1

2020

| Cortex-M55(F) || Cortex-R82(F) || || Cortex-A78
Cortex-A78AE
Cortex-A78C || Cortex-X1
{{Cite web |url=https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging |title=Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence |access-date=2021-04-15 |website=Anandtech}} || Neoverse V1
{{Cite web |date=2020-09-22 |title=Arm Announces Neoverse V1 & N2 Infrastructure CPUs: +50% IPC, SVE Server Cores|url=https://www.anandtech.com/show/16073/arm-announces-neoverse-v1-n2 |access-date=2021-04-15 |website=Anandtech}}

2021

| || || || Cortex-A510
Cortex-A710 || Cortex-X2 || Neoverse E2
Neoverse N2

2022

| Cortex-M85(F) || Cortex-R52+(F) || || Cortex-A715 || Cortex-X3 || Neoverse V2

2023

| Cortex-M52(F) || || || Cortex-A520
Cortex-A720 || Cortex-X4 || Neoverse E3
Neoverse N3

2024

| || Cortex-R82AE || || Cortex-A520AE
Cortex-A720AE
Cortex-A725 || Cortex-X925 || Neoverse V3
Neoverse V3AE
Neoverse VN

2025

| || || || Cortex-A320
Cortex-A530
Cortex-A730 || Cortex-X930 || Neoverse E4
Neoverse N4
Neoverse V4

See also

{{Portal|Electronics}}

References

{{Reflist}}

Further reading

{{See also|ARM Cortex-M#Further reading|l1=List of books about ARM Cortex-M}}

{{Application ARM-based chips}}

{{Embedded ARM-based chips}}

{{Classic ARM-based chips}}

{{DEFAULTSORT:ARM microarchitectures}}

Category:Lists of microprocessors