Pentium (original)#MMX

The P5 Pentium is the first superscalar x86 processor, meaning it was often able to execute two instructions at the same time.Rant, Jon, "Pentium Processor: Previewing Desktop Computing's Next Step", Intel Corporation, Microcomputer Solutions, March/April 1993, page 1 Some techniques used to implement this were based on the earlier superscalar Intel i960 CA (1989), while other details were invented exclusively for the P5 design. Large parts were also copied from the i386 or i486, especially the strategies used to cope with the complicated x86 encodings in a pipelined fashion.as compared to a simple RISC processor like the i960. Just like the i486, the Pentium used both an optimized microcode system and RISC-like techniques, depending on the particular instruction, or part of instruction. The dual integer pipeline design is something that had been argued being impossible to implement for a CISC instruction set, by certain academics and RISC competitors.{{Who|date=March 2024}}

Other central features include a redesigned and significantly faster floating-point unit, a wide 64-bit burst-mode data bus (external as well as internal), separate code and data caches, and many other techniques and features to enhance performance. It contains 256-bit internal data buses and write-back caches.Rant, Jon, "Pentium Processor: Previewing Desktop Computing's Next Step", Intel Corporation, Microcomputer Solutions, March/April 1993, page 1

The 66-MHz Pentium processor operates at 112 V1.1 Dhrystone MIPS and has SPECint92 rating of 64.5, a SPECfp92 rating of 56.9 and an iCOMP index rating of 567. The performance difference between 60- and 66-MHz version is about 10%.Rant, Jon, "Pentium Processor: Previewing Desktop Computing's Next Step", Intel Corporation, Microcomputer Solutions, March/April 1993, page 1

The P5 also has better support for multiprocessing compared to the i486, and is the first x86 CPU with hardware support for it similar to IBM mainframe computers. Intel worked with IBM to define this ability and also designed it into the P5 microarchitecture. This ability was absent in prior x86 generations and x86 processors from competitors.

In order to employ the dual pipelines at their full potential, certain compilers were optimized to better exploit instruction level parallelism, although not all applications would substantially gain from being recompiled. The faster FPU always enhanced floating point performance significantly though, compared to the i486 or i387. Intel spent resources working with development tool vendors, ISVs and operating system (OS) companies to optimize their products.

File:Intel Pentium A80501 66 SX950.JPG

Competitors included the superscalar PowerPC 601 (1993), SuperSPARC (1992), DEC Alpha 21064 (1992), AMD 29050 (1990), Motorola MC88110 (1991) and Motorola 68060 (1994), most of which also used a superscalar in-order dual instruction pipeline configuration, and the non-superscalar Motorola 68040 (1990) and MIPS R4000 (1991).

The name "Pentium" is originally derived from the Greek word pente (πέντε), meaning "five", a reference to the prior numeric naming convention of Intel's 80x86 processors (8086–80486), with the Latin ending -ium since the processor would otherwise have been named 80586 using that convention.

The P5 microarchitecture was designed by the same Santa Clara team which designed the 386 and 486.{{cite book |page=1 |title=The Pentium Chronicles: The People, Passion, and Politics Behind Intel's Landmark Chips |first=Robert P. |last=Colwell |author-link=Bob Colwell |publisher=Wiley |date=2006 |isbn=978-0-471-73617-2}} Design work started in 1989;{{cite magazine |title=Inside Intel |magazine=Business Week |issue=3268 |date=June 1, 1992}}{{rp|page=88}} the team decided to use a superscalar RISC architecture which would be a convergence of RISC and CISC technology,House, Dave, "Putting the RISC vs. CISC Debate to Rest", Intel Corporation, Microcomputer Solutions, November/December 1991, page 18 with on-chip cache, floating-point, and branch prediction. The preliminary design was first successfully simulated in 1990, followed by the laying-out of the design. By this time, the team had several dozen engineers. It took some 100 million clock cycles of pre-silicon verification test which includes major operating systems and many application were booted and running. They had to use the Quickturn Systems Inc. software to run pre-silicon simulation program which was 30,000 times quicker than the previous technique method available.Chen, Allan, Editor; Hodson Gerri, Associate Edtior, "Intelperspectives: Intel's Newsletter for MIS Profesionals, Volume 2, Number 1", Intel Corporation, Microcomputer Solutions, January/February 1993. page 11 The design was taped out, or transferred to silicon, in April 1992, at which point beta-testing began.{{cite magazine |url=http://www.iptegrity.com/index.php?option=com_content&task=view&id=34&Itemid=42 |title=The hot new star of microchips |first=Monica |last=Horten |magazine=New Scientist |issue=1871 |pages=31 ff |date=May 1, 1993 |access-date=June 9, 2009 |archive-url=https://web.archive.org/web/20110727064516/http://www.iptegrity.com/index.php?option=com_content&task=view&id=34&Itemid=42 |archive-date=July 27, 2011 |url-status=dead}} By mid-1992, the P5 team had 200 engineers.{{rp|page=89}} Intel at first planned to demonstrate the P5 in June 1992 at the trade show PC Expo, and to formally announce the processor in September 1992,{{cite magazine | page = 8| title = Intel to offer a peek at its '586' chip| first = Tom | last = Quinlan| magazine = InfoWorld| date = 16 March 1992| url = {{ google books | id=3D0EAAAAMBAJ | page=8 |plain-url=true }}}} but design problems forced the demo to be cancelled, and the official introduction of the chip was delayed until the spring of 1993.{{cite magazine| page = 1| title = Design woes force Intel to cancel 586 chip demo| first1 = Tom| last1 = Quinlan| first2 = Cate | last2 = Corcoran| magazine = InfoWorld| volume = 14| issue = 24| date = 15 June 1992| url = {{ google books | id=aVEEAAAAMBAJ | page=1 |plain-url=true }}}}{{cite magazine | pages = 1, 103| title = P5 chip delay won't alter rivals' plans| first1 = Tom | last1 = Quinlan| first2 = Cate| last2 = Corcoran| magazine = InfoWorld| volume = 14| issue = 30| date = 27 July 1992| url = {{ google books | id=HVEEAAAAMBAJ | page=1 |plain-url=true }}}} The first computer systems featuring the Pentium appeared in the summer of 1993, the first being Advanced Logic Research and their Evolution V workstation, released in the first week of July 1993.{{cite journal | last=Rohrbough | first=Linda | date=July 8, 1993 | url=https://link.gale.com/apps/doc/A14084213/GPS?u=wikipedia&sid=bookmark-GPS&xid=977b9036 | title=ALR Shipping First Pentium PCs Starting Under $2,500 | work=Newsbytes | publisher=The Washington Post Company | page=NEW07080026 | via=Gale}}{{cite journal | last=Staff writer | date=October 19, 1993 | url=https://www.proquest.com/docview/1524591176/ | title=Pentium PCs to hit US stores | work=South China Morning Post | page=1 | via=ProQuest}}{{cite journal | last=Woolley | first=Scott | date=May 30, 1994 | url=https://www.proquest.com/docview/211139258/ | title=As Pentium edge wanes, ALR rolls out new products | work=Orange County Business Journal | publisher=American City Business Journals | volume=17 | issue=22 | page=1 | via=ProQuest}}

John H. Crawford, chief architect of the original 386, co-managed the design of the P5,{{cite magazine| url = {{ google books | id=ajkEAAAAMBAJ |page = 51 | plain-url=true }}| pages = 51–55| title = Intel Turns 35: Now What?| first = David L. | last = Margulius| magazine = InfoWorld| date = July 21, 2003| volume = 25| issue = 28| issn = 0199-6649}} along with Donald Alpert, who managed the architectural team. Dror Avnon managed the design of the FPU.{{cite magazine |page=21 |url=https://ieeexplore.ieee.org/document/216745 |title=Architecture of the Pentium microprocessor] |first1=D. |last1=Alpert |first2=D. |last2=Avnon |magazine=IEEE Micro |volume=13 |issue=3 |date=June 1993 |doi=10.1109/40.216745}} Vinod K. Dham was general manager of the P5 group.{{rp|page=90}}

Intel's Larrabee multicore architecture project uses a processor core derived from a P5 core (P54C), augmented by multithreading, 64-bit instructions, and a 16-byte wide vector processing unit.§3 of {{cite journal |first1=L. |last1=Seiler |first2=D. |last2=Cavin |first3=E. |last3=Espasa |first4=T. |last4=Grochowski |first5=M. |last5=Juan |first6=P. |last6=Hanrahan |first7=S. |last7=Carmean |first8=A. |last8=Sprangle |first9=J. |last9=Forsyth |first10=R. |last10=Abrash |first11=R. |last11=Dubey |first12=E. |last12=Junkins |first13=T. |last13=Lake |first14=P. |last14=Sugerman |date=August 2008 |title=Larrabee: A Many-Core x86 Architecture for Visual Computing |journal=ACM Transactions on Graphics |volume=27 |issue=3 |pages=18:11 |issn=0730-0301 |doi=10.1145/1360612.1360617 |url=https://pages.cs.wisc.edu/~markhill/restricted/siggraph08_larrabee.pdf |access-date=August 18, 2023 |series=Proceedings of ACM SIGGRAPH 2008 |s2cid=52799248 }} Intel's low-powered Bonnell microarchitecture employed in early Atom processor cores also uses an in-order dual pipeline similar to P5.{{Citation |title=Why Pine Trail Isn't Much Faster Than the First Atom |last=Shimpi |first=Anand Lal |date=January 27, 2010 |url=http://www.anandtech.com/show/2925 |access-date=August 4, 2010}}

Intel used the Pentium name instead of 586, because in 1991, it had lost a trademark dispute over the "386" trademark, when a judge ruled that the number was generic. The company hired Lexicon Branding to come up with a new, non-numeric name.{{cite news |last1=Smith |first1=Ernie |title=Why Intel Couldn't Trademark Numbers Anymore |url=https://www.vice.com/en/article/why-intel-couldnt-trademark-numbers-anymore/ |access-date=July 13, 2023 |work=Vice |date=June 14, 2017 |language=en}}

The P5 microarchitecture brings several important advances over the prior i486 architecture.

• Performance:
• Superscalar architecture – The Pentium has two datapaths (pipelines) that allow it to complete two instructions per clock cycle in many cases. The main pipe (U) can handle any instruction, while the other (V) can handle the most common simple instructions. Some{{who|date=July 2018}} reduced instruction set computer (RISC) proponents had argued that the "complicated" x86 instruction set would probably never be implemented by a tightly pipelined microarchitecture, much less by a dual-pipeline design. The 486 and the Pentium demonstrated that this was indeed possible and feasible.
• 64-bit burst-mode external databus doubles the amount of information possible to read or write on each memory access and therefore allows the Pentium to load its code cache faster than the 80486; it also allows faster access and storage of 64-bit and 80-bit x87 FPU data.
• Separation of code and data in both 8-Kbyte on-chip cachesRant, Jon, "Pentium Processor: Previewing Desktop Computing's Next Step", Intel Corporation, Microcomputer Solutions, March/April 1993, page 1 lessens the fetch and operand read/write conflicts compared to the 486. To reduce access time and implementation cost, both of them are 2-way associative, instead of the single 4-way cache of the 486. A related enhancement in the Pentium is the ability to read a contiguous block from the code cache even when it is split between two cache lines (at least 17 bytes in worst case).
• Much faster floating-point unit. Some instructions showed an enormous improvement, most notably FMUL, with up to 15 times higher throughput than in the 80486 FPU. The Pentium is also able to execute a FXCH ST(x) instruction in parallel with an ordinary (arithmetical or load/store) FPU instruction.
• Four-input address adders enables the Pentium to further reduce the address calculation latency compared to the 80486. The Pentium can calculate full addressing modes with segment-base + base-register + scaled register + immediate offset in a single cycle; the 486 has a three-input address adder only, and must therefore divide such calculations between two cycles.
• The microcode can employ both pipelines to enable auto-repeating instructions such as REP MOVSW perform one iteration every clock cycle, while the 80486 needed three clocks per iteration (and the earliest x86 chips significantly more than the 486). Also, optimization of the access to the first microcode words during the decode stages helps in making several frequent instructions execute significantly more quickly, especially in their most common forms and in typical cases. Some examples are (486→Pentium, in clock cycles): CALL (3→1), RET (5→2), shifts/rotates (2–3→1).
• A faster, fully hardware-based multiplier makes instructions such as MUL and IMUL several times faster (and more predictable) than in the 80486; the execution time is reduced from 13 to 42 clock cycles down to 10–11 for 32-bit operands.
• Virtualized interrupt to speed up virtual 8086 mode.
• Branch prediction
• Other features:
• Enhanced debug features with the introduction of the Processor-based debug port (see Pentium Processor Debugging in the Developers Manual, Vol 1).
• Enhanced self-test features like the L1 cache parity check (see Cache Structure in the Developers Manual, Vol 1).
• New instructions: CPUID, CMPXCHG8B, RDTSC, RDMSR, WRMSR, RSM.
• Test registers TR0–TR7 and MOV instructions for access to them were eliminated.
• The later Pentium MMX also added the MMX instruction set, a basic integer single instruction, multiple data (SIMD) instruction set extension marketed for use in multimedia applications. MMX could not be used simultaneously with the x87 FPU instructions because the registers were reused (to allow fast context switches). More important enhancements were the doubling of the instruction and data cache sizes and a few microarchitectural changes for better performance.

The Pentium was designed to execute over 100 million instructions per second (MIPS),{{cite web |url=http://dede.essortment.com/pcusersguides_rjje.htm |title=PC users guide: General Computer Information |access-date=September 14, 2007 |url-status=dead |archive-url=https://web.archive.org/web/20070728013256/http://dede.essortment.com/pcusersguides_rjje.htm |archive-date=July 28, 2007}} and the 75 MHz model was able to reach 126.5 MIPS in certain benchmarks.{{cite web|url=http://www.islandnet.com/~kpolsson/micropro/proc1994.htm |title=Chronology of Microprocessors |first=Ken |last=Polsson}} The Pentium architecture typically offered just under twice the performance of a 486 processor per clock cycle in common benchmarks. The fastest 80486 parts (with slightly improved microarchitecture and 100 MHz operation) were almost as powerful as the first-generation Pentiums, and the AMD Am5x86, which despite its name is actually a 486-class CPU, was roughly equal to the Pentium 75 regarding pure ALU performance.

The early versions of 60–66 MHz P5 Pentiums had a problem in the floating-point unit that resulted in incorrect (but predictable) results from some division operations. This flaw, discovered in 1994 by professor Thomas Nicely at Lynchburg College, Virginia, became widely known as the Pentium FDIV bug and caused embarrassment for Intel, which created an exchange program to replace the faulty processors.

In 1997, another erratum was discovered that could allow a malicious program to crash a system without any special privileges, the "F00F bug". All P5 series processors were affected and no fixed steppings were ever released, however contemporary operating systems were patched with workarounds to prevent crashes.

The Pentium was Intel's primary microprocessor for personal computers during the mid-1990s. The original design was reimplemented in newer processes and new features were added to maintain its competitiveness, and to address specific markets such as portable computers. As a result, there were several variants of the P5 microarchitecture.

File:Intel Pentium arch.svg

The first Pentium microprocessor core was code-named "P5". Its product code was 80501 (80500 for the earliest steppings Q0399). There were two versions, specified to operate at 60 MHz and 66 MHz respectively, using Socket 4. This first implementation of the Pentium was released using a 273-pin PGA form factor and ran on a 5v power supply. (descended from the usual transistor-transistor logic (TTL) compatibility requirements). It contained 3.1 million transistors and measured 16.7 mm by 17.6 mm for an area of 293.92 mm².{{cite magazine |last=Case |first=Brian |date=March 29, 1993 |title=Intel Reveals Pentium Implementation Details |magazine=Microprocessor Report}} It was fabricated in a 800 nm bipolar complementary metal–oxide–semiconductor (BiCMOS) process.{{cite web| url = http://datasheets.chipdb.org/Intel/x86/Pentium/24159502.pdf| title = Intel Pentium processor (510\60, 567\66). Nov 1994}} The 5-volt design resulted in relatively high energy consumption for its operating frequency when compared to the directly following models.

File:Intel Pentium P54C die.jpg

The P5 was followed by the P54C (80502) in 1994, with versions specified to operate at 75, 90, or 100 MHz using a 3.3 volt power supply. Marking the switch to Socket 5, this was the first Pentium processor to operate at 3.3 volts, reducing energy consumption, but necessitating voltage regulation on mainboards. As with higher-clocked 486 processors, an internal clock multiplier was employed from here on to let the internal circuitry work at a higher frequency than the external address and data buses, as it is more complicated and cumbersome to increase the external frequency, due to physical constraints. It also allowed two-way multiprocessing, and had an integrated local APIC and new power management features. It contained 3.3 million transistors and measured 163 mm². It was fabricated in a BiCMOS process which has been described as both 500 nm and 600 nm due to differing definitions.

The P54C was followed by the P54CQS in early 1995, which operated at 120 MHz. It was fabricated in a 350 nm BiCMOS process and was the first commercial microprocessor to be fabricated in a 350 nm process.{{cite magazine |last=Gwennap |first=Linley |date=March 27, 1995 |title=Pentium is First CPU to Reach 0.35 Micron |magazine=Microprocessor Report}} Its transistor count is identical to the P54C and, despite the newer process, it had an identical die area as well. The chip was connected to the package using wire bonding, which only allows connections along the edges of the chip. A smaller chip would have required a redesign of the package, as there is a limit on the length of the wires and the edges of the chip would be further away from the pads on the package. The solution was to keep the chip the same size, retain the existing pad-ring, and only reduce the size of the Pentium's logic circuitry to enable it to achieve higher clock frequencies.

The P54CQS was quickly followed by the P54CS, which operated at 133, 150, 166 and 200 MHz, and introduced Socket 7. It contained 3.3 million transistors, measured 90 mm² and was fabricated in a 350 nm BiCMOS process with four levels of interconnect.

{{Further|Pentium OverDrive}}

The P24T Pentium OverDrive for 486 systems were released in 1995, which were based on 3.3 V 600 nm versions using a 63 or 83 MHz clock. Since these used Socket 2/3, some modifications had to be made to compensate for the 32-bit data bus and slower on-board L2 cache of 486 motherboards. They were therefore equipped with a 32 KB L1 cache (double that of pre-P55C Pentium CPUs).

File:Intel Pentium MMX arch.svg

File:P-MMX.JPG

The P55C (or 80503) was developed by Intel's Research & Development Center in Haifa, Israel. It was sold as Pentium with MMX Technology (usually just called Pentium MMX); although it was based on the P5 core, it featured a new set of 57 "MMX" instructions intended to improve performance on multimedia tasks, such as encoding and decoding digital media data. The Pentium MMX line was introduced on October 22, 1996, and released in January 1997.{{Citation |title=New Chip Begs New Questions |publisher=CNet |url=http://news.cnet.com/New-chip-begs-new-questions/2100-1001_3-240247.html?tag=mncol |access-date=February 6, 2009}}

The new instructions worked on new data types: 64-bit packed vectors of either eight 8-bit integers, four 16-bit integers, two 32-bit integers, or one 64-bit integer. So, for example, the PADDUSB (Packed ADD Unsigned Saturated Byte) instruction adds two vectors, each containing eight 8-bit unsigned integers together, elementwise; each addition that would overflow saturates, yielding 255, the maximal unsigned value that can be represented in a byte. These rather specialized instructions generally require special coding by the programmer for them to be used.{{citation needed|date=March 2021}}

Other changes to the core include a 6-stage pipeline (vs. 5 on P5) with a return stack (first done on Cyrix 6x86) and better parallelism, an improved instruction decoder, 16KB L1 data cache + 16KB L1 instruction cache with Both 4-way associativity (vs. 8KB L1 Data/instruction with 2-way on P5), 4 write buffers that could now be used by either pipeline (vs. one corresponding to each pipeline on P5) and an improved branch predictor taken from the Pentium Pro,{{cite web |url=https://www.ece.cmu.edu/~ece548/localcpy/24281603.pdf |title=Intel Architecture Optimization Manual |year=1997 |access-date=September 1, 2017 |pages=2–16 |archive-date=July 5, 2017 |archive-url=https://web.archive.org/web/20170705101430/http://www.ece.cmu.edu/~ece548/localcpy/24281603.pdf |url-status=dead }}{{cite web |url=http://philipstorr.id.au/pcbook/book1/process.htm |access-date=September 1, 2017 |title=Phil Storrs PC Hardware book |archive-date=January 20, 2020 |archive-url=https://web.archive.org/web/20200120053206/http://philipstorr.id.au/pcbook/book1/process.htm |url-status=dead }} with a 512-entry buffer (vs. 256 on P5).{{cite web |url=http://download.intel.com/support/processors/pentiummmx/sb/24318504.pdf |title=Pentium Processor with MMX Technology |year=1997 |access-date=September 1, 2017 |archive-url=https://web.archive.org/web/20100705122448/http://download.intel.com/support/processors/pentiummmx/sb/24318504.pdf |archive-date=July 5, 2010 |url-status=dead}}

It contained 4.5 million transistors and had an area of 140 mm². It was fabricated in a 280 nm CMOS process with the same metal pitches as the previous 350 nm BiCMOS process, so Intel described it as "350 nm" because of its similar transistor density.{{cite magazine |last=Slater |first=Michael |date=March 5, 1996 |title=Intel's Long-Awaited P55C Disclosed |magazine=Microprocessor Report}} The process has four levels of interconnect.

While the P55C remained compatible with Socket 7, the voltage requirements for powering the chip differ from the standard Socket 7 specifications. Most motherboards manufactured for Socket 7 before the establishment of the P55C standard are not compliant with the dual voltage rail required for proper operation of this CPU (2.8 volt core voltage, 3.3 volt input/output (I/O) voltage). Intel addressed the issue with OverDrive upgrade kits that featured an interposer with its own voltage regulation.

Pentium MMX notebook CPUs used a mobile module that held the CPU. This module was a printed circuit board (PCB) with the CPU directly attached to it in a smaller form factor. The module snapped to the notebook motherboard, and typically a heat spreader was installed and made contact with the module. However, with the 250 nm Tillamook Mobile Pentium MMX (named after a city in Oregon), the module also held the 430TX chipset along with the system's 512 KB static random-access memory (SRAM) cache memory.

After the introduction of the Pentium, competitors such as NexGen,{{cite journal|title=NexGen to Beat Intel's Chip Prices|last1=Corcoran|first1=Cate|last2=Crothers|first2=Brooke|journal=InfoWorld|publisher=IDG|date=July 11, 1994|page=5|url=https://books.google.com/books?id=ljgEAAAAMBAJ&pg=PA5}} AMD, Cyrix, and Texas Instruments announced Pentium-compatible processors in 1994.{{cite journal|title=Pentium Killers|last=Barr|first=Christopher|journal=PC Magazine|publisher=Ziff Davis|date=January 11, 1994|volume=13|issue=1|page=29|url=https://books.google.com/books?id=E9TvMcu1mIwC&pg=PA29}} CIO magazine identified NexGen's Nx586 as the first Pentium-compatible CPU,{{cite journal|title=In the Chips|last=Edwards|first=John|journal=CIO magazine|publisher=IDG|date=June 15, 1995|volume=8|issue=17|pages=72–76|url=https://books.google.com/books?id=aAYAAAAAMBAJ&pg=PA72}} while PC Magazine described the Cyrix 6x86 as the first. These were followed by the AMD K5, which was delayed due to design difficulties. AMD later bought NexGen to help design the AMD K6, and Cyrix was bought by National Semiconductor.{{cite journal|title=The CPU for Your Next PC|last=Slater|first=Michael|journal=PC Magazine|date=September 23, 1997|pages=130–133|volume=16|issue=16|publisher=Ziff Davis|url=https://books.google.com/books?id=rm500_oURScC&pg=PA122}} Later processors from AMD and Intel retain compatibility with the original Pentium.

• AMD K5, AMD K6
• Cyrix 6x86
• WinChip C6
• NexGen Nx586
• Rise mP6

• List of Intel CPU microarchitectures
• List of Intel Pentium processors
• Cache on a stick (COASt), L2 cache modules for Pentium
• IA-32 instruction set architecture (ISA)
• Intel 82497 cache controller

{{Reflist}}

• [http://www.cpu-collection.de/?tn=0&l0=co&l1=Intel&l2=Pentium%20P54 CPU-Collection.de] - Intel Pentium images and descriptions
• [http://www.plasma-online.de/english/identify/picture/intel_cpu.html Plasma Online Intel CPU Identification]
• [http://www.chipdb.org/index.php?template=timeline The Pentium Timeline Project] {{Webarchive|url=https://web.archive.org/web/20211223151333/http://www.chipdb.org/index.php?template=timeline |date=December 23, 2021 }} The Pentium Timeline Project maps oldest and youngest chip known of every s-spec made. Data are shown in an interactive timeline.

• [http://datasheets.chipdb.org/Intel/x86/Pentium/24159502.pdf Pentium (P5)]
• [http://datasheets.chipdb.org/Intel/x86/Pentium/24199710.PDF Pentium (P54)]
• [http://datasheets.chipdb.org/Intel/x86/Pentium%20MMX/24318504.PDF Pentium MMX (P55C)]
• [http://datasheets.chipdb.org/Intel/x86/Pentium%20MMX/24329204.PDF Mobile Pentium MMX (P55C)]
• [http://datasheets.chipdb.org/Intel/x86/Pentium%20MMX/24346802.PDF Mobile Pentium MMX (Tillamook)]

These official manuals provide an overview of the Pentium processor and its features:

• Pentium Processor Family Developer's Manual [https://web.archive.org/web/20111014203214/http://download.intel.com/design/intarch/manuals/24142805.pdf Pentium Processor (Volume 1)] (Intel order number 241428)
• Pentium Processor Family Developer's Manual [https://web.archive.org/web/20120313153131/http://download.intel.com/design/pentium/MANUALS/24319101.PDF Volume 2: Instruction Set Reference] (Intel order number 243191)
• Pentium Processor Family Developer's Manual [ftp://download.intel.com/design/pentium/manuals/24143004.pdf Volume 3: Architecture and Programming Manual]{{dead link|date=May 2025|bot=medic}}{{cbignore|bot=medic}} (Intel order number 241430)

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{{Intel processors|P5}}

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Category:Computer-related introductions in 1993

Category:Intel x86 microprocessors

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