CPUID#EAX=0Dh: XSAVE features and state-components

! style="width: 75px" | 30

! style="width: 75px" | 29

! style="width: 75px" | 28

! style="width: 75px" | 27

! style="width: 75px" | 26

! style="width: 75px" | 25

! style="width: 75px" | 24

! style="width: 75px" | 23

! style="width: 75px" | 22

! style="width: 75px" | 21

! style="width: 75px" | 20

! style="width: 75px" | 19

! style="width: 75px" | 18

! style="width: 75px" | 17

! style="width: 75px" | 16

! style="width: 75px" | 15

! style="width: 75px" | 14

! style="width: 75px" | 13

! style="width: 75px" | 12

! style="width: 75px" | 11

! style="width: 75px" | 10

! style="width: 75px" | 9

! style="width: 75px" | 8

! style="width: 75px" | 7

! style="width: 75px" | 6

! style="width: 75px" | 5

! style="width: 75px" | 4

! style="width: 75px" | 3

! style="width: 75px" | 2

! style="width: 75px" | 1

! style="width: 75px" | 0

! Encoding in Binary

| {{n/a}} || {{n/a}} || {{n/a}}

| {{n/a}} || {{n/a}} || {{n/a}}

| {{n/a}} || {{n/a}} || {{n/a}}

| {{n/a|{{efn|The i386 processor does not support the CPUID instruction - it does however return Family ID 3h in the reset-value of EDX.}}}} || {{n/a}} || {{n/a}}

| 486

| 486,AMD, [https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/datasheets/20736.pdf Enhanced Am486DX Microprocessor Family], pub.no. 20736 rev B, March 1997, section 9.2.2, page 55. [https://web.archive.org/web/20231018093730/https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/datasheets/20736.pdf Archived] on 18 Oct 2023.
5x86,
Élan SC4xx/5xxAMD, [https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/user-guides/21030.pdf ÉlanSC400 and ÉlanSC410 Microcontrollers User's Manual], pub.no. 21030, 1997, section 3.6.2, page 73. [https://web.archive.org/web/20231018093705/https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/user-guides/21030.pdf Archived] on 18 Oct 2023.

| Cyrix 5x86,Cyrix, [http://www.bitsavers.org/components/cyrix/94246-00_5x86_CPU_BIOS_Writers_Guide_199510.pdf 5x86 BIOS Writers Guide], rev 1.12, order no. 92426-00, 1995, page 7
Cyrix MediaGX,Cyrix, [http://www.bitsavers.org/components/cyrix/appnotes/Cyrix_CPU_Detection_Guide_1997.pdf CPU Detection Guide], rev 1.01, 2 Oct 1997, page 6.
UMC Green CPU,Debbie Wiles, [https://web.archive.org/web/20040604002243/http://debs.future.easyspace.com/Programming/OS/cpuid.txt CPU Identification], archived on 2006-06-04
MCST Elbrus (most models),
MiSTer ao486MiSTer ao486 source code, [https://github.com/MiSTer-devel/ao486_MiSTer/blob/43a20047d5e2e99f1264dadbdab777733ccbb61a/rtl/ao486/defines.v rtl/ao486/defines.v], line 70. [https://web.archive.org/web/20231023193346/https://raw.githubusercontent.com/MiSTer-devel/ao486_MiSTer/43a20047d5e2e99f1264dadbdab777733ccbb61a/rtl/ao486/defines.v Archived] on 23 Oct 2023.

| Pentium,
Pentium MMX,
Quark X1000

| K5,
K6

| Cyrix 6x86,
Cyrix MediaGXm,
Geode (except NX),
NexGen Nx586,
IDT WinChip,
IDT WinChip 2,
IDT WinChip 3,
Transmeta Crusoe,
Rise mP6,
SiS 550,
DM&P Vortex86 (early),CPU-World, [https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=66102 CPUID for Vortex86DX2 933 MHz]. [https://archive.today/20231017222230/https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=66102 Archived] on 17 Oct 2023.
RDC IAD 100,
MCST Elbrus-8C2

| Pentium Pro,
Pentium II,
Pentium III,
Pentium M,
{{nowrap|Intel Core (all variants),}}
{{nowrap|Intel Atom (all variants),}}
Xeon (except NetBurst variants),
Xeon Phi (except KNC)

| K7: Athlon,
Athlon XP

| Cyrix 6x86MX/MII,
VIA C3,
VIA C7,
VIA Nano,
DM&P Vortex86 (DX3,EX2CPU-World, [https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=72324 CPUID for Vortex86EX2]. [https://archive.today/20231018100523/https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=72324 Archived] on 18 Oct 2023.),
Zhaoxin ZX-A/B/C/C+,
(Centaur CNSInstLatx64, [http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls0040672_CNS_04_CPUID.txt Centaur CNS CPUID dump]. [https://web.archive.org/web/20230530122012/http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls0040672_CNS_04_CPUID.txt Archived] on 30 May 2023.),
MCST Elbrus-12C/16C/2C3

| Itanium
(in IA-32 mode)

| {{n/a}}

| Zhaoxin KaiXian,
Zhaoxin KaisHeng

| {{n/a|{{efn|Family ID 8h has been reported to have been deliberately avoided for the Pentium 4 processor family due to incompatibility with Windows NT 4.0.Jeff Atwood, [https://blog.codinghorror.com/nasty-software-hacks-and-intels-cpuid/ Nasty Software Hacks and Intel's CPUID]. Coding Horror, 16 Aug 2005.}}}} || {{n/a}} || {{n/a}}

| {{n/a}} || {{n/a}} || {{n/a}}

| {{n/a}} || {{n/a}} || {{n/a}}

| Xeon Phi (Knights Corner)Intel, [https://www.intel.com/content/dam/develop/external/us/en/documents/327364001en.pdf Intel Xeon Phi Coprocessor Instruction Set Architecture Reference Manual], sep 2012, order no. 327364-001, appendix B.8, pages 673-674. [https://web.archive.org/web/20210804022347/https://software.intel.com/content/dam/develop/external/us/en/documents/327364001en.pdf Archived] on 4 Aug 2021. || {{n/a}} || {{n/a}}

| {{n/a}} || {{n/a}} || {{n/a}}

| {{n/a}} || {{n/a}} || {{n/a}}

| {{n/a}} || {{n/a}} || {{n/a}}

| NetBurst (Pentium 4)

| K8/Hammer
(Athlon 64)

| Transmeta Efficeon

| {{n/a}} || K10: Phenom || {{n/a}}

| Itanium 2CPU-World, [https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=40724 CPUID for Intel Itanium 2 1.50 GHz]. [https://archive.today/20231017221310/https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=40724 Archived] on 17 Oct 2023.
(in IA-32 mode) || Turion X2 || {{n/a}}

| {{n/a}} || Llano || {{n/a}}

| Intel Core (Panther Cove and up){{Cite web |title=[PATCH] x86/cpu: Add two Intel CPU model numbers - Tony Luck |url=https://lore.kernel.org/lkml/20240923173750.16874-1-tony.luck@intel.com/ |access-date=2024-09-24 |website=lore.kernel.org}} || {{n/a}} || {{n/a}}

| {{n/a}} || Bobcat || {{n/a}}

| {{n/a}} || Bulldozer,
Piledriver,
Steamroller,
Excavator || {{n/a}}

| {{n/a}} || Jaguar,
Puma || {{n/a}}

| {{n/a}} || Zen 1,
Zen 2 || {{n/a}}

| {{n/a}} || colspan=2 style="text-align:center" | Hygon Dhyana

| {{n/a}} || Zen 3,
Zen 4 || {{n/a}}

| {{n/a}} || Zen 5 || {{n/a}}

| Brand Index

|

| CLFLUSH line size (Value * 8 = cache line size in bytes)

| if CLFLUSH feature flag is set.

CPUID.01.EDX.CLFSH [bit 19]= 1

| Maximum number of addressable IDs for logical processors in this physical package;

The nearest power-of-2 integer that is not smaller than this value is the number of unique initial APIC IDs reserved for addressing different logical processors in a physical package.{{efn|On CPUs with more than 128 logical processors in a single package (e.g. Intel Xeon Phi 7290InstLatX64, [http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0050671_KnightsLanding_CPUID2.txt 72-Core Intel Xeon Phi 7290 CPUID dump] and AMD Threadripper Pro 7995WXInstLatx64, [http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0A10F81_K19_StormPeak_01_CPUID.txt 96-Core AMD Ryzen Threadripper Pro 7995WX CPUID dump]) the value in bit 23:16 is set to a non-power-of-2 value.}}

Former use: Number of logical processors per physical processor; two for the Pentium 4 processor with Hyper-Threading Technology.{{Citation |title=Intel Processor Identification and the CPUID Instruction |date=May 2002 |url=http://bochs.sourceforge.net/techspec/24161821.pdf |archive-url=https://web.archive.org/web/20210417041749/https://bochs.sourceforge.io/techspec/24161821.pdf |archive-date=2021-04-17 |publisher=Intel}}

| if Hyper-threading feature flag is set.

CPUID.01.EDX.HTT [bit 28]= 1

| Local APIC ID: The initial APIC-ID is used to identify the executing logical processor.{{efn|text=The Local APIC ID can also be identified via the cpuid 0Bh leaf ( CPUID.0Bh.EDX[x2APIC-ID] ). On CPUs with more than 256 logical processors in one package (e.g. Xeon Phi 7290), leaf 0Bh must be used because the APIC ID does not fit into 8 bits. }}

| Pentium 4 and subsequent processors.

| fpu || Onboard x87 FPU

| sse3|| SSE3 (Prescott New Instructions - PNI)

! 0

| vme || Virtual 8086 mode extensions (such as VIF, VIP, PVI)

| pclmulqdq || PCLMULQDQ (carry-less multiply) instruction

! 1

| de || Debugging extensions (CR4 bit 3)

| dtes64 || 64-bit debug store (edx bit 21)

! 2

| pse || Page Size Extension (4 MB pages)

| monitor || MONITOR and MWAIT instructions (PNI)

! 3

| tsc || Time Stamp Counter and RDTSC instruction

| ds-cpl || CPL qualified debug store

! 4

| msr || Model-specific registers and RDMSR/WRMSR instructions

| vmx || Virtual Machine eXtensions

! 5

| pae || Physical Address Extension

| smx || Safer Mode Extensions (LaGrande) (GETSEC instruction)

! 6

| mce || Machine Check Exception

| est || Enhanced SpeedStep

! 7

| cx8{{efn|text=On processors from IDT, Transmeta and Rise (vendor IDs CentaurHauls, GenuineTMx86 and RiseRiseRise), the CMPXCHG8B instruction is always supported, however the feature bit for the instruction might not be set. This is a workaround for a bug in Windows NT.Geoff Chappell, [https://www.geoffchappell.com/studies/windows/km/cpu/cx8.htm CMPXCHG8B Support in the 32-Bit Windows Kernel], Jan 23, 2008. [https://web.archive.org/web/20230130233150/https://www.geoffchappell.com/studies/windows/km/cpu/cx8.htm Archived] on Jan 30, 2023.}}|| CMPXCHG8B (compare-and-swap) instruction

| tm2 || Thermal Monitor 2

! 8

| apic{{efn|On early AMD K5 (AuthenticAMD Family 5 Model 0) processors only, EDX bit 9 used to indicate support for PGE instead. This was moved to bit 13 from K5 Model 1 onwards.AMD, [http://www.bitsavers.org/components/amd/x86/K86/20734D_AMD_Processor_Recognition_Application_Notes_Jan97.pdf AMD Processor Recognition Application Note], publication #20734, rev D, Jan 1997, page 13}} || Onboard Advanced Programmable Interrupt Controller

| ssse3 || Supplemental SSE3 instructions

! 9

| style="background:lightgrey;" | (mtrr){{efn|text=Intel AP-485, revisions 006Intel, [https://kib.kiev.ua/x86docs/Intel/AppNote485/241618-006.pdf AP-485 Application Note - Intel Processor Identification and the CPUID Instruction], order no. 241618-006, march 1997, table 5 on page 10, see bit 10. to 008, lists {{nowrap|1=CPUID.(EAX=1):EDX[bit 10]}} as having the name "MTRR" (albeit described as "Reserved"/"Do not count on their value") - this name was removed in later revisions of AP-485, and the bit has been listed as reserved with no name since then.}}

| style="text-align:center; background:lightgrey;" | (reserved)

| cnxt-id || L1 Context ID

! 10

| sep{{efn|On Pentium Pro (GenuineIntel Family 6 Model 1) processors only, EDX bit 11 is invalid - the bit is set, but the SYSENTER and SYSEXIT instructions are not supported on the Pentium Pro.Michal Necasek, [http://www.os2museum.com/wp/sysenter-where-are-you/ SYSENTER, Where Are You?], OS/2 Museum, July 20, 2017}} || SYSENTER and SYSEXIT fast system call instructions

| sdbg || Silicon Debug interface

! 11

| mtrr || Memory Type Range Registers{{efn|text=For the MTRRs, additional feature information is not available through CPUID, but instead through the read-only MTRRCAP MSR (MSR 0FEh). This MSR has the following layout: {{(!}} class="wikitable sortable"

! Bits

{{!}}-

{{!}} 7:0 {{

{{!}}-

{{!}} 8 {{

{{!}}-

{{!}} 9 {{

{{!}}-

{{!}} 10 {{

{{!}}-

{{!}} 11 {{

{{!}}-

{{!}} 12 {{

{{!}}-

{{!}} 13 {{

{{!}}-

{{!}} 14 {{

{{!}}-

{{!}} 15 {{

{{!}}-

{{!}} 63:16 {{

{{!)}}}}

| fma || Fused multiply-add (FMA3)

! 12

| pge || Page Global Enable bit in CR4

| cx16 || CMPXCHG16B instruction{{efn|1=Some very early Intel 64 processors have the CMPXCHG16B feature bit set even though they do not support the instruction - this applies to GenuineIntel Family 0Fh Model 3 Stepping 4 chips (90nm Pentium 4) only.Intel, [https://www.intel.com/Assets/PDF/specupdate/302352.pdf Pentium 4 Processor on 90 nm Process Specification Update], order no. 302352-031, sep 2006, see erratum R85 on page 59. [https://web.archive.org/web/20081231012952/https://www.intel.com/Assets/PDF/specupdate/302352.pdf Archived] on 31 Dec 2008.}}

! 13

| mca || Machine check architecture

| xtpr || Can disable sending task priority messages

! 14

| cmov || Conditional move: CMOV, FCMOV and FCOMI instructions{{efn|FCMOV and FCOMI instructions only available if onboard x87 FPU also present (indicated by EDX bit 0).}}

| pdcm || Perfmon & debug capability

! 15

| pat || Page Attribute Table

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved){{efn|ECX bit 16 is listed as "Reserved" in public Intel and AMD documentation and is not set in any known processor. However, some versions of the Windows Vista kernel are reported to be checking this bitGeoff Chappell, [https://www.geoffchappell.com/studies/windows/km/cpu/cpuid/00000001h/ecx.htm ECX From CPUID Leaf 1], Jan 26, 2020. [https://web.archive.org/web/20200509082346/https://www.geoffchappell.com/studies/windows/km/cpu/cpuid/00000001h/ecx.htm Archived] on May 9, 2020. - if it is set, Vista will recognize it as a "processor channels" feature.}}

! 16

| pse-36 || 36-bit page size extension

| pcid || Process context identifiers (CR4 bit 17)

! 17

| psn || Processor Serial Number supported and enabled{{efn|text=On Intel and Transmeta CPUs that support PSN (Processor Serial Number), the PSN can be disabled by setting bit 21 of MSR 119h (BBL_CR_CTL) to 1. Doing so will remove leaf 3 and cause {{nowrap|1=CPUID.(EAX=1):EDX[bit 18]}} to return 0.}}

| dca || Direct cache access for DMA writes{{Cite journal | last1 = Huggahalli | first1 = Ram| last2 = Iyer | first2 = Ravi| last3 = Tetrick | first3 = Scott| doi = 10.1145/1080695.1069976 | title = Direct Cache Access for High Bandwidth Network I/O | journal = ACM SIGARCH Computer Architecture News | volume = 33 | issue = 2 | pages = 50–59| year = 2005 | id = CiteSeerX:{{URL|1=citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.91.957|2=10.1.1.91.957}}| citeseerx = 10.1.1.85.3862 }}{{Citation |title=What Every Programmer Should Know About Memory |year=2007 |first=Ulrich |last=Drepper |id = CiteSeerX:{{URL|1=citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.91.957|2=10.1.1.91.957}} }}

! 18

| clfsh || CLFLUSH cache line flush instruction (SSE2)

| sse4.1 || SSE4.1 instructions

! 19

| style="background:lightgrey;" | (nx)

| style="background:lightgrey;" | No-execute (NX) bit (Itanium only, reserved on other CPUs)Intel, [https://www.intel.com/content/dam/www/public/us/en/documents/manuals/itanium-architecture-vol-4-manual.pdf Itanium Architecture Software Developer's Manual, rev 2.3, volume 4: IA-32 Instruction Set], may 2010, document number: 323208, table 2-5, page 4:81, see bits 20 and 30. [https://web.archive.org/web/20120215121932/https://www.intel.com/content/dam/www/public/us/en/documents/manuals/itanium-architecture-vol-4-manual.pdf Archived] on Feb 15, 2012.{{efn|On non-Itanium x86 processors, support for the No-execute bit is indicated in {{nowrap|1=CPUID.(EAX=8000_0001):EDX[bit 20]}} instead.}}

| sse4.2 || SSE4.2 instructions

! 20

| ds || Debug store: save trace of executed jumps

| x2apic || x2APIC (enhanced APIC)

! 21

| acpi || Onboard thermal control MSRs for ACPI

| movbe || MOVBE instruction (big-endian)

! 22

| mmx || MMX instructions (64-bit SIMD)

| popcnt || POPCNT instruction

! 23

| fxsr || FXSAVE, FXRSTOR instructions, CR4 bit 9

| tsc-deadline || APIC implements one-shot operation using a TSC deadline value

! 24

| sse || Streaming SIMD Extensions (SSE) instructions
(aka "Katmai New Instructions"; 128-bit SIMD)

| aes-ni || AES instruction set

! 25

| sse2 || SSE2 instructions

| xsave || Extensible processor state save/restore:
XSAVE, XRSTOR, XSETBV, XGETBV instructions

! 26

| ss || CPU cache implements self-snoop

| osxsave || XSAVE enabled by OS

! 27

| htt || Max APIC IDs reserved field is Valid{{efn|text=EDX bit 28, if set, indicates that bits 23:16 of CPUID.(EAX=1):EBX are valid. If this bit is not set, then the CPU package contains only 1 logical processor.

In older documentation, this bit is often listed as a "Hyper-threading technology"Intel, [https://kib.kiev.ua/x86docs/Intel/AppNote485/241618-030.pdf AP-485, Processor Identification and the CPUID Instruction flag], rev 30, jan 2006, page 26 flag - however, while this flag is a prerequisite for Hyper-Threading support, it does not by itself indicate support for Hyper-Threading and it has been set on many CPUs that do not feature any form of multi-threading technology.Michal Necasek, [http://www.os2museum.com/wp/htt-means-hyper-threading-right/ HTT Means Hyper-Threading, Right?], OS/2 Museum, dec 11, 2017

| avx || Advanced Vector Extensions (256-bit SIMD)

! 28

| tm || Thermal monitor automatically limits temperature

| f16c || Floating-point conversion instructions to/from FP16 format

! 29

| ia64 || IA64 processor emulating x86

| rdrnd || RDRAND (on-chip random number generator) feature

! 30

| pbe || Pending Break Enable (PBE# pin) wakeup capability

| hypervisor || Hypervisor present (always zero on physical CPUs){{cite web |url=https://kb.vmware.com/s/article/1009458 |title=Mechanisms to determine if software is running in a VMware virtual machine |work=VMware Knowledge Base |publisher=VMWare |date=2015-05-01 |quote=Intel and AMD CPUs have reserved bit 31 of ECX of CPUID leaf 0x1 as the hypervisor present bit. This bit allows hypervisors to indicate their presence to the guest operating system. Hypervisors set this bit and physical CPUs (all existing and future CPUs) set this bit to zero. Guest operating systems can test bit 31 to detect if they are running inside a virtual machine. }}{{cite web |url=https://lore.kernel.org/lkml/1222881242.9381.17.camel@alok-dev1/ |title=Hypervisor CPUID Interface Proposal |last1=Kataria |first1=Alok |last2=Hecht |first2=Dan |publisher=LKML Archive on lore.kernel.org |date=2008-10-01 |url-status=live |archive-url=https://web.archive.org/web/20190315105121/https://lore.kernel.org/lkml/1222881242.9381.17.camel@alok-dev1/ |archive-date=2019-03-15 |quote=Bit 31 of ECX of CPUID leaf 0x1. This bit has been reserved by Intel & AMD for use by hypervisors and indicates the presence of a hypervisor. Virtual CPU's (hypervisors) set this bit to 1 and physical CPU's (all existing and future CPU's) set this bit to zero. This bit can be probed by the guest software to detect whether they are running inside a virtual machine. }}{{cite web |title=AMD64 Technology AMD64 Architecture Programmer's Manual Volume 2: System Programming |url=https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf |publisher=Advanced Micro Devices, Inc. |access-date=9 September 2023 |page=498 |language=English |id=24593 |edition=3.41 |archive-url=https://web.archive.org/web/20230930084941/https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf |archive-date=30 Sep 2023 |quote=15.2.2 Guest Mode This new processor mode is entered through the VMRUN instruction. When in guest mode, the behavior of some x86 instructions changes to facilitate virtualization. The CPUID function numbers 4000_0000h-4000_00FFh have been reserved for software use. Hypervisors can use these function numbers to provide an interface to pass information from the hypervisor to the guest. This is similar to extracting information about a physical CPU by using CPUID. Hypervisors use the CPUID Fn 400000[FF:00] bit to denote a virtual platform. Feature bit CPUID Fn0000_0001_ECX[31] has been reserved for use by hypervisors to indicate the presence of a hypervisor. Hypervisors set this bit to 1 and physical CPU's set this bit to zero. This bit can be probed by the guest software to detect whether they are running inside a virtual machine. }}

! 31

| rowspan=5 | Cache Type:

• 0: (No more caches)
• 1: Data Cache
• 2: Instruction Cache
• 3: Unified Cache
• 4-31: (reserved)

| rowspan=10 | System coherency line size in bytes, {{nowrap|minus 1}}

| WBINVD cache invalidation execution scope.
A value of 0 indicates that the INVD/WBINVD instructions will invalidate all lower-levels caches of this cache, including caches that belong to sibling processors sharing this cache. A value of 1 indicates that lower-level caches of sibling processors that are sharing this cache are not guaranteed to be all cleared.

! 0

| Cache inclusiveness. If 1, then cache is inclusive of lower-level caches.

! 1

| {{maybe|Complex cache indexing. If 1, then cache uses a complex function for cache indexing, else the cache is direct-mapped. (#4)}}

! 2

| style="text-align:center; background:lightgrey;" | (reserved)

! 3

| style="text-align:center; background:lightgrey;" | (reserved)

! 4

| Cache Level (starting from 1)

| style="text-align:center; background:lightgrey;" | (reserved)

! 7:5

| Self initializing cache level (1=doesn't need software initialization after reset)

| style="text-align:center; background:lightgrey;" | (reserved)

! 8

| Fully Associative Cache

| style="text-align:center; background:lightgrey;" | (reserved)

! 9

| {{maybe|(WBINVD cache invalidation execution scope){{efn|name=leaf4_knc|For CPUID leaf 4, bits 11:10 of EAX are documented for the Xeon Phi "Knights Corner" (GenuineIntel Family 0Bh) processor only. For other processors, bits 1:0 of EDX should be used instead.}} (#4)}}

| style="text-align:center; background:lightgrey;" | (reserved)

! 10

| {{maybe|(Cache Inclusiveness){{efn|name=leaf4_knc}} (#4)}}

| style="text-align:center; background:lightgrey;" | (reserved)

! 11

| style="text-align:center; background:lightgrey;" | (reserved)

| rowspan=2 | Physical line partitions (number of cache lines that share a cache address tag), {{nowrap|minus 1}}

| style="text-align:center; background:lightgrey;" | (reserved)

! 13:12

| rowspan=2 | Maximum number of addressable IDs for logical processors sharing this cache, {{nowrap|minus 1}}

| style="text-align:center; background:lightgrey;" | (reserved)

! 21:14

| rowspan=2 | Ways of cache associativity, {{nowrap|minus 1}}

| style="text-align:center; background:lightgrey;" | (reserved)

! 25:22

| {{maybe|Maximum number of addressable IDs for processor cores in physical package, {{nowrap|minus 1}} (#4)}}

| style="text-align:center; background:lightgrey;" | (reserved)

! 31:26

| rowspan="4" | Smallest monitor-line size in bytes

| rowspan="4" | Largest monitor-line size in bytes

| Number of C0{{efn|1=The C0 to C7 states are processor-specific C-states, which do not necessarily correspond 1:1 to ACPI C-states.}} sub-states supported for MWAIT

! 3:0

| Number of C1 sub-states supported for MWAIT

! 7:4

| Number of C2 sub-states supported for MWAIT

! 11:8

| Number of C3 sub-states supported for MWAIT

! 15:12

| rowspan="4" style="text-align:center; background:lightgrey;" | (reserved)

| rowspan="4" style="text-align:center; background:lightgrey;" | (reserved)

| Number of C4 sub-states supported for MWAIT

! 19:16

| Number of C5 sub-states supported for MWAIT

! 23:20

| Number of C6 sub-states supported for MWAIT

! 27:24

| Number of C7 sub-states supported for MWAIT

! 31:28

! Feature

| EMX || Enumeration of MONITOR/MWAIT extensions in ECX and EDX supported

| IBE || Supports treating interrupts as break-events for MWAIT even when interrupts are disabled

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| Monitorless_­MWAIT || Allow MWAIT to be used for power management without setting up memory monitoring with MONITORIntel, [https://cdrdv2-public.intel.com/819680/architecture-instruction-set-extensions-programming-reference.pdf Architecture Instruction Set Extensions Programming Reference], order no. 319433-052, March 2024, chapter 17. [https://web.archive.org/web/20240407230452/https://cdrdv2-public.intel.com/819680/architecture-instruction-set-extensions-programming-reference.pdf Archived] on Apr 7, 2024.

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! Feature

| DTS || Digital Thermal Sensor capability

| || Intel Turbo Boost Technology capability

| ARAT{{efn|text=On Intel Pentium 4 family processors only, bit 2 of EAX is used to indicate OPP (Operating Point Protection)Intel, [https://kib.kiev.ua/x86docs/Intel/AppNote485/241618-030.pdf Intel Processor Identification and the CPUID Instruction (AP-485, rev 30)], order no. 241618-030, Jan 2006, page 19. instead of ARAT.}} || Always Running APIC Timer capability

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| PLN || Power Limit Notification capability

| ECMD || Extended Clock Modulation Duty capability

| PTM || Package Thermal Management capability

| HWP || Hardware-controlled Performance States. MSRs added:

• IA32_PM_ENABLE(770h)
• IA32_HWP_CAPABILITIES(771h)
• IA32_HWP_REQUEST(774h)
• IA32_HWP_STATUS(777h

| HWP_Notification || HWP notification of dynamic guaranteed performance change - IA32_HWP_INTERRUPT(773h) MSR

| HWP_Activity_­Window || HWP Activity Window control - bits 41:32 of IA32_HWP_REQUEST MSR

| HWP_Energy_­Performance_­Preference || HWP Energy/performance preference control - bits 31:24 of IA32_HWP_REQUEST MSR

| HWP_Package_­Level_Request || HWP Package-level control - IA32_HWP_REQUEST_PKG(772h) MSR

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| HDC || Hardware Duty Cycling supported. MSRs added:

• IA32_PKG_HDC_CTL (DB0h)
• IA32_PM_CTL1 (DB1h)
• IA32_THREAD_STALL (DB2h)

| || Intel Turbo Boost Max Technology 3.0 available

| || Interrupts upon changes to IA32_HWP_CAPABILITIES.Highest_Performance (bits 7:0) supported

| || HWP PECI override supported - bits 63:60 of IA32_HWP_PECI_REQUEST_INFO(775h) MSR

| || Flexible HWP - bits 63:59 of IA32_HWP_REQUEST MSR

| Fast Access Mode || Fast access mode for IA32_HWP_REQUEST MSR supported{{efn|To enable fast (non-serializing) access mode for the IA32_HWP_REQUEST MSR on CPUs that support it, it is necessary to set bit 0 of the FAST_UNCORE_MSRS_CTL(657h) MSR.}}

| HW_FEEDBACK || Hardware Feedback Interface. Added MSRs:

• IA32_HW_FEEDBACK_PTR(17D0h)
• IA32_HW_FEEDBACK_CONFIG(17D1h) (bit 0 enables HFI, bit 1 enables Intel Thread Director)

| || IA32_HWP_REQUEST of idle logical processor ignored when only one of two logical processors that share a physical processor is active.

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| HWP Control MSR || IA32_HWP_CTL(776h) MSR supportedIntel, [https://kib.kiev.ua/x86docs/Intel/SDMs/325462-079.pdf Intel 64 and IA-32 Architecture Software Developer's Manual], order no. 352462-079, volume 3B, section 15.4.4.4, page 3503

| || Intel Thread Director supported. Added MSRs:

• IA32_THREAD_FEEDBACK_CHAR(17D2h)
• IA32_HW_FEEDBACK_THREAD_CONFIG(17D4h)

| || IA32_THERM_INTERRUPT MSR bit 25 supported

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| rowspan="4" | Number of Interrupt Thresholds in Digital Thermal Sensor

| Effective frequency interface supported - IA32_MPERF(0E7h) and IA32_APERF(0E8h) MSRs

| Hardware Feedback reporting: Performance Capability Reporting supported

! 0

| (ACNT2 Capability){{efn|text=The "ACNT2 Capability" bit is listed in Intel AP-485 rev 038Intel, [https://kib.kiev.ua/x86docs/Intel/AppNote485/241618-038.pdf Processor Identification and the CPUID Instruction], order no. 241618-038, apr 2012, p.38 and 039, but not listed in any revision of the Intel SDM. The feature is known to exist in only a few Intel CPUs, e.g. Xeon "Harpertown" stepping E0.Intel, [https://web.archive.org/web/20230511191706/https://qdms.intel.com/dm/d.aspx/4E8B0DA3-C0C1-49FF-8592-F3C36E417233/PCN108701-00.pdf Product Change Notification 108701], 1 aug 2008. Archived on May 11, 2023}}

| Hardware Feedback reporting: Efficiency Capability Reporting supported

! 1

| style="text-align:center; background:lightgrey;" | (reserved)

| rowspan="3" style="text-align:center; background:lightgrey;" | (reserved)

! 2

| Performance-Energy Bias capability - IA32_ENERGY_PERF_BIAS(1B0h) MSR

! 3

| rowspan="4" style="text-align:center; background:lightgrey;" | (reserved)

| style="text-align:center; background:lightgrey;" | (reserved)

! 7:4

| rowspan="2" | Number of Intel Thread Director classes supported by hardware

| Size of Hardware Feedback interface structure (in units of 4 KB) minus 1

! 11:8

| style="text-align:center; background:lightgrey;" | (reserved)

! 15:12

| style="text-align:center; background:lightgrey;" | (reserved)

| Index of this logical processor's row in hardware feedback interface structure

!
31:16
 

! Feature

! Short

! Feature

! Short

! Feature

| fsgsbase || Access to base of %fs and %gs

| prefetchwt1 || PREFETCHWT1 instruction

| (sgx-tem){{efn|name=leaf7_0_tdx}} || ?

! 0

| || IA32_TSC_ADJUST MSR

| avx512-vbmi || AVX-512 Vector Bit Manipulation Instructions

| sgx-keys || Attestation Services for Intel SGX

! 1

| sgx || Software Guard Extensions

| umip || User-mode Instruction Prevention

| avx512-4vnniw || AVX-512 4-register Neural Network Instructions

! 2

| bmi1 || Bit Manipulation Instruction Set 1

| pku || Memory Protection Keys for User-mode pages

| avx512-4fmaps || AVX-512 4-register Multiply Accumulation Single precision

! 3

| hle || TSX Hardware Lock Elision

| ospke || PKU enabled by OS

| fsrm || Fast Short {{nowrap|REP MOVSB}}

! 4

| avx2 || Advanced Vector Extensions 2

| waitpkg || Timed pause and user-level monitor/wait instructions (TPAUSE, UMONITOR, UMWAIT)

| uintr || User Inter-processor Interrupts

! 5

| fdp-excptn-only || x87 FPU data pointer register updated on exceptions only

| avx512-vbmi2 || AVX-512 Vector Bit Manipulation Instructions 2

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 6

| smep || Supervisor Mode Execution Prevention

| cet_ss/shstk || Control flow enforcement (CET): shadow stack (SHSTK alternative name)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 7

| bmi2 || Bit Manipulation Instruction Set 2

| gfni || Galois Field instructions

| avx512-vp2intersect || AVX-512 vector intersection instructions on 32/64-bit integers

! 8

| erms || Enhanced {{nowrap|REP MOVSB/STOSB}}

| vaes || Vector AES instruction set (VEX-256/EVEX)

| srbds-ctrl || Special Register Buffer Data Sampling Mitigations

! 9

| invpcid || INVPCID instruction

| vpclmulqdq || CLMUL instruction set (VEX-256/EVEX)

| md-clear || VERW instruction clears CPU buffers

! 10

| rtm || TSX Restricted Transactional Memory

| avx512-vnni || AVX-512 Vector Neural Network Instructions

| rtm-always-abort{{Cite web |date=June 2023 |title=Performance Monitoring Impact of Intel Transactional Synchronization Extension Memory Ordering Issue |url=https://cdrdv2.intel.com/v1/dl/getContent/604224 |access-date=8 May 2024 |website=Intel |page=8 |format=PDF}} || All TSX transactions are aborted

! 11

| rdt-m/pqm || Intel Resource Director (RDT) Monitoring or AMD Platform QOS Monitoring

| avx512-bitalg || AVX-512 BITALG instructions

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 12

| || x87 FPU CS and DS deprecated

| tme_en || Total Memory Encryption MSRs available

| rtm-force-abort || TSX_FORCE_ABORT (MSR 0x10f) is available

! 13

| mpx || Intel MPX (Memory Protection Extensions)

| avx512-vpopcntdq || AVX-512 Vector Population Count Double and Quad-word

| serialize || SERIALIZE instruction

! 14

| rdt-a/pqe || Intel Resource Director (RDT) Allocation or AMD Platform QOS Enforcement

| (fzm){{efn|name=leaf7_0_tdx|text=As of April 2024, the FZM, MPRR and SGX_TEM bits are listed only in Intel TDX documentationIntel, [https://web.archive.org/web/20210729201408/https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-module-1eas.pdf Architecture Specification: Intel Trust Domain Extensions (Intel TDX) Module], order no. 344425-001, sep 2020, pages 120-122. Archived from the [https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-module-1eas.pdf original] on Jul 29, 2021. and are not set in any known processor.}} || ?

| hybrid || Mixture of CPU types in processor topology (e.g. Alder Lake)

! 15

| avx512-f || AVX-512 Foundation

| la57 || 5-level paging (57 address bits)

| tsxldtrk || TSX load address tracking suspend/resume instructions (TSUSLDTRK and TRESLDTRK)

! 16

| avx512-dq || AVX-512 Doubleword and Quadword Instructions

| rowspan="5" | mawau || rowspan="5" | The value of userspace MPX Address-Width Adjust used by the BNDLDX and BNDSTX Intel MPX instructions in 64-bit mode

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 17

| rdseed || RDSEED instruction

| pconfig || Platform configuration (Memory Encryption Technologies Instructions)

! 18

| adx || Intel ADX (Multi-Precision Add-Carry Instruction Extensions)

| lbr || Architectural Last Branch Records

! 19

| smap || Supervisor Mode Access Prevention

| cet-ibt || Control flow enforcement (CET): indirect branch tracking

! 20

| avx512-ifma || AVX-512 Integer Fused Multiply-Add Instructions

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 21

| (pcommit) || (PCOMMIT instruction, deprecated)Intel, [https://www.intel.com/content/www/us/en/developer/articles/technical/deprecate-pcommit-instruction.html Deprecating the PCOMMIT instruction], sep 12, 2016. [https://archive.today/20230423213953/https://www.intel.com/content/www/us/en/developer/articles/technical/deprecate-pcommit-instruction.html Archived] on Apr 23, 2023.

| rdpid || RDPID (Read Processor ID) instruction and IA32_TSC_AUX MSR

| amx-bf16 || AMX tile computation on bfloat16 numbers

! 22

| clflushopt || CLFLUSHOPT instruction

| kl || AES Key Locker

| avx512-fp16 || AVX-512 half-precision floating-point arithmetic instructionsIntel, [https://cdrdv2-public.intel.com/678970/intel-avx512-fp16.pdf AVX512-FP16 Architecture Specification] (PDF), document number 347407-001, June 2021. [https://web.archive.org/web/20221026062138/https://cdrdv2-public.intel.com/678970/intel-avx512-fp16.pdf Archived] on Oct 26, 2022

! 23

| clwb || CLWB (Cache line writeback) instruction

| bus-lock-detect || Bus lock debug exceptions

| amx-tile || AMX tile load/store instructions

! 24

| pt || Intel Processor Trace

| cldemote || CLDEMOTE (Cache line demote) instruction

| amx-int8 || AMX tile computation on 8-bit integers

! 25

| avx512-pf || AVX-512 Prefetch Instructions

| (mprr){{efn|name=leaf7_0_tdx}} || ?

| ibrs / spec_ctrl || Speculation Control, part of Indirect Branch Control (IBC):
Indirect Branch Restricted Speculation (IBRS) and
Indirect Branch Prediction Barrier (IBPB){{cite web |title=Speculative Execution Side Channel Mitigations |version=Revision 2.0 |date=May 2018 |orig-year=January 2018 |id=Document Number: 336996-002 |publisher=Intel |url=https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf |access-date=2018-05-26}}{{Cite web | url=https://lwn.net/Articles/743019/ | title=IBRS patch series [LWN.net]}}

! 26

| avx512-er || AVX-512 Exponential and Reciprocal Instructions

| movdiri || MOVDIRI instruction

| stibp || Single Thread Indirect Branch Predictor, part of IBC

! 27

| avx512-cd || AVX-512 Conflict Detection Instructions

| movdir64b || MOVDIR64B (64-byte direct store) instruction

| L1D_FLUSH || IA32_FLUSH_CMD MSR

! 28

| sha || SHA-1 and SHA-256 extensions

| enqcmd || Enqueue Stores and EMQCMD/EMQCMDS instructions

| || IA32_ARCH_CAPABILITIES MSR (lists speculative side channel mitigations)

! 29

| avx512-bw || AVX-512 Byte and Word Instructions

| sgx-lc || SGX Launch Configuration

| || IA32_CORE_CAPABILITIES MSR (lists model-specific core capabilities)

! 30

| avx512-vl || AVX-512 Vector Length Extensions

| pks || Protection keys for supervisor-mode pages

| ssbd || Speculative Store Bypass Disable, as mitigation for Speculative Store Bypass (IA32_SPEC_CTRL)

! 31

! Short || Feature

! Short || Feature

! Short || Feature

| sha512 || SHA-512 extensions

| || Intel PPIN (Protected Processor Inventory Number): IA32_PPIN_CTL (04Eh) and IA32_PPIN (04Fh) MSRs.

| || Asymmetric RDT Monitoring capability

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 0

| sm3 || SM3 hash extensions

| pbndkb || Total Storage Encryption: PBNDKB instruction and TSE_CAPABILITY (9F1h) MSR.

| || Asymmetric RDT Allocation capability

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 1

| sm4 || SM4 cipher extensions

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| (legacy_­reduced_­isa) || (X86S,Intel, [https://web.archive.org/web/20241002150150/https://cdrdv2-public.intel.com/776648/x86s-eas-external-1.2.pdf X86S External Architecture Specification] v1.2, June 2024, order no. 351407-002, section 3.5, page 13. Archived from the [https://cdrdv2-public.intel.com/776648/x86s-eas-external-1.2.pdf original] on 2 Oct 2024. cancelledIntel, [https://www.intel.com/content/www/us/en/developer/articles/technical/envisioning-future-simplified-architecture.html Envisioning a Simplified Intel Architecture] - as of 20 Dec 2024, contains a mention that Intel has chosen not to pursue X86S. [https://web.archive.org/web/20241220104422/https://www.intel.com/content/www/us/en/developer/articles/technical/envisioning-future-simplified-architecture.html Archived] on 20 Dec 2024.)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 2

| rao-int || Remote Atomic Operations on integers: AADD, AAND, AOR, AXOR instructions

| CPUID­MAXVAL_­LIM_RMV || If 1, then bit 22 of IA32_MISC_ENABLE cannot be set to 1 to limit the value returned by CPUID.(EAX=0):EAX[7:0].

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 3

| avx-vnni || AVX Vector Neural Network Instructions (VNNI) (VEX encoded)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| (sipi64) || 64-bit SIPI (Startup InterProcessor Interrupt) (part of cancelled X86S)

| avx-vnni-int8 || AVX VNNI INT8 instructions

! 4

| avx512-bf16 || AVX-512 instructions for bfloat16 numbers

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| MSR_IMM || Immediate forms of the RDMSR and WRMSRNS instructions

| avx-ne-convert || AVX no-exception FP conversion instructions (bfloat16↔FP32 and FP16→FP32)

! 5

| lass || Linear Address Space Separation (CR4 bit 27)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 6

| cmpccxadd || CMPccXADD instructions

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 7

| archperf­monext || Architectural Performance Monitoring Extended Leaf (EAX=23h)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| amx-complex || AMX support for "complex" tiles (TCMMIMFP16PS and TCMMRLFP16PS)

! 8

| (dedup){{efn|text=As of April 2024, the DEDUP bit is listed only in Intel TDX documentation and is not set in any known processor.}} || ?

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 9

| fzrm || Fast zero-length {{nowrap| REP MOVSB}}

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| avx-vnni-int16 || AVX VNNI INT16 instructions

! 10

| fsrs || Fast short {{nowrap|REP STOSB}}

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 11

| rsrcs || Fast short {{nowrap|REP CMPSB}} and {{nowrap|REP SCASB}}

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 12

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| utmr || User-timer events: IA32_UINTR_TIMER (1B00h) MSR

! 13

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| prefetchi || Instruction-cache prefetch instructions (PREFETCHIT0 and PREFETCHIT1)

! 14

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| user_msr || User-mode MSR access instructions (URDMSR and UWRMSR)

! 15

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 16

| fred || Flexible Return and Event DeliveryIntel, [https://cdrdv2-public.intel.com/795033/346446-flexible-return-and-event-delivery.pdf Flexible Return and Event Delivery (FRED) Specification], rev 6.1, December 2023, order no. 346446-007, page 14. [https://web.archive.org/web/20231222195250/https://cdrdv2-public.intel.com/795033/346446-flexible-return-and-event-delivery.pdf Archived] on Dec 22, 2023.

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| uiret-uif-from-rflags || If 1, the UIRET (User Interrupt Return) instruction will set UIF (User Interrupt Flag) to the value of bit 1 of the RFLAGS image popped off the stack.

! 17

| lkgs || LKGS Instruction

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| cet-sss || If 1, then Control-Flow Enforcement (CET) Supervisor Shadow Stacks (SSS) are guaranteed not to become prematurely busy as long as shadow stack switching does not cause page faults on the stack being switched to.Intel, [https://kib.kiev.ua/x86docs/Intel/SDMs/325462-080.pdf Software Developer's Manual], order no. 325462-080, June 2023 - information about prematurely busy shadow stacks provided in Volume 1, section 17.2.3 on page 410; Volume 2A, table 3.8 (CPUID EAX=7,ECX=2) on page 820; Volume 3C, table 25-14 on page 3958 and section 26.4.3 on page 3984.Intel, [https://cdrdv2-public.intel.com/785687/356628-complex-shadow-stack-updates-2.pdf Complex Shadow-Stack Updates (Intel Control-Flow Enforcement Technology)], order no. 356628-001, August 2023. [https://web.archive.org/web/20240402080946/https://cdrdv2-public.intel.com/785687/356628-complex-shadow-stack-updates-2.pdf Archived] on 2 Apr 2024.LKML, [https://lkml.org/lkml/2023/6/16/1194 Re: (PATCH v3 00/21) Enable CET Virtualization], Jun 16, 2023 - provides additional discussion of how the CET-SSS prematurely-busy stack issue interacts with virtualization. [https://web.archive.org/web/20230807130831/https://lkml.org/lkml/2023/6/16/1194 Archived] on 7 Aug 2023.

! 18

| wrmsrns || WRMSRNS instruction (non-serializing write to MSRs)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| avx10 || AVX10 Converged Vector ISA (see also leaf 24h)Intel, [https://cdrdv2-public.intel.com/784267/355989-intel-avx10-spec.pdf Advanced Vector Extensions 10], rev 1.0, July 2023, order no. 355989-001. [https://web.archive.org/web/20230724201235/https://cdrdv2-public.intel.com/784267/355989-intel-avx10-spec.pdf Archived] on Jul 24, 2023.

! 19

| nmi_src || NMI source reporting

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 20

| amx-fp16 || AMX instructions for FP16 numbers

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| APX_F || Advanced Performance Extensions, Foundation (adds REX2 and extended EVEX prefix encodings to support 32 GPRs, as well as some new instructions)Intel, [https://cdrdv2-public.intel.com/786223/355828-intel-apx-spec.pdf Advanced Performance Extensions - Architecture Specification], rev 2.0, Aug 2023, order no. 355828-002, page 37. [https://web.archive.org/web/20230910083914/https://cdrdv2-public.intel.com/786223/355828-intel-apx-spec.pdf Archived] on Sep 10, 2023.

! 21

| hreset || HRESET instruction, IA32_HRESET_ENABLE (17DAh) MSR, and Processor History Reset Leaf (EAX=20h)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 22

| avx-ifma || AVX IFMA instructions

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| mwait || MWAIT instruction{{efn|1=Support for the MWAIT instruction may be indicated by either {{nowrap|1=CPUID.(EAX=1).ECX[3]}} or {{nowrap|1=CPUID.(EAX=7,ECX=1).EDX[23].}} (One or both may be set.) The former indicates support for the MONITOR instruction as well, while the latter does not indicate one way or another whether the MONITOR instruction is present. MWAIT without MONITOR may be present in systems that support the "Monitorless MWAIT" feature (which is itself indicated by {{nowrap|1=CPUID.(EAX=5).ECX[3]}}.)}}

! 23

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 24

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 25

| lam || Linear Address Masking

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 26

| msrlist || RDMSRLIST and WRMSRLIST instructions, and the IA32_BARRIER (02Fh) MSR

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 27

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 28

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 29

| invd_­disable_­post_­bios_done || If 1, supports INVD instruction execution prevention after BIOS Done.

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 30

| MOVRS || MOVRS and PREFETCHRST2 instructions supported (memory read/prefetch with read-shared hint)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 31

| psfd || Fast Store Forwarding PredictorIntel, [https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/fast-store-forwarding-predictor.html Fast Store Forwarding Predictor], 8 Feb 2022. [https://web.archive.org/web/20240406120655/https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/fast-store-forwarding-predictor.html Archived] on 6 Apr 2024. disable supported. (SPEC_CTRL (MSR 48h) bit 7)

| ipred_ctrl || IPRED_DIS controls supported. (SPEC_CTRL bits 3 and 4)

IPRED_DIS prevents instructions at an indirect branch target from speculatively executing until the branch target address is resolved.

| rrsba_ctrl || RRSBA behaviorIntel, [https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/return-stack-buffer-underflow.html Return Stack Buffer Underflow / CVE-2022-29901, CVE-2022-28693 / INTEL-SA-00702], 12 Jul 2022. [https://archive.today/20220713102638/https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/return-stack-buffer-underflow.html Archived] on 13 Jul 2022. disable supported. (SPEC_CTRL bits 5 and 6)

| ddpd_u || Data Dependent PrefetcherIntel, [https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/data-dependent-prefetcher.html Data Dependent Prefetcher], 10 Nov 2022. [https://web.archive.org/web/20240804163643/https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/data-dependent-prefetcher.html Archived] on 4 Aug 2024. disable supported. (SPEC_CTRL bit 8)

| bhi_ctrl || BHI_DIS_S behaviorIntel, [https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/branch-history-injection.html Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598], 4 Aug 2022. [https://archive.today/20230505163802/https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/branch-history-injection.html Archived] on 5 May 2023. enable supported. (SPEC_CTRL bit 10)

BHI_DIS_S prevents predicted targets of indirect branches executed in ring0/1/2 from being selected based on branch history from branches executed in ring 3.

| mcdt_no || If set, the processor does not exhibit MXCSR configuration dependent timing.

| || UC-lock disable feature supported.

| monitor_mitg_no || If set, indicates that the MONITOR/UMONITOR instructions are not affected by performance/power issues caused by the instructions exceeding the capacity of an internal monitor tracking table.Intel, [https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/monitor-umonitor-performance-guidance.html MONITOR and UMONITOR Performance Guidance], 10 Jul 2024. [https://web.archive.org/web/20241127041155/https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/monitor-umonitor-performance-guidance.html Archived] on 27 Nov 2024.

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| rowspan="3" | Size in bytes of state-component

| rowspan="3" | Offset of state-component from the start of the XSAVE/XRSTOR save area

(This offset is 0 for supervisor state-components, since these can only be saved with the XSAVES/XRSTORS instruction, which use compacting.)

| User/supervisor state-component:

• 0=user-state (enabled through XCR0)
• 1=supervisor-state (enabled through IA32_XSS)

! 0

| 64-byte alignment enable when state save compaction is used.

If this bit is set for a state-component, then, when storing state with compaction, padding will be inserted between the preceding state-component and this state-component as needed to provide 64-byte alignment. If this bit is not set, the state-component will be stored directly after the preceding one.

! 1

| style="text-align:center; background:lightgrey;"| (reserved)

!
31:2

| xsaveopt || XSAVEOPT instruction: save state-components that have been modified since last XRSTOR

| xsavec || XSAVEC instruction: save/restore state with compaction

| xgetbv_ecx1 || XGETBV with ECX=1 support

| xss || XSAVES and XRSTORS instructions and IA32_XSS MSR: save/restore state with compaction, including supervisor state.

| xfd || XFD (Extended Feature Disable) supported

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| x87 state || {{yes|XCR0{{efn|Bit 0 of XCR0 is hardwired to 1, so that the XSAVE instructions will always support save/restore of x87 state.}}}}

| SSE state: XMM0-XMM15 and MXCSR || rowspan=7 {{yes|XCR0}}

| AVX state: top halves of YMM0 to YMM15

| MPX state: BND0-BND3 bounds registers

| MPX state: BNDCFGU and BNDSTATUS registers

| AVX-512 state: opmask registers k0-k7

| AVX-512 "ZMM_Hi256" state: top halves of ZMM0 to ZMM15

| AVX-512 "Hi16_ZMM" state: ZMM16-ZMM31

| Processor Trace state || {{no|IA32_XSS}}

| PKRU (User Protection Keys) register || {{yes|XCR0}}

| PASID (Process Address Space ID) state || rowspan="7" {{no|IA32_XSS}}

| CET_U state (Control-flow Enforcement Technology: user-mode functionality MSRs)

| CET_S state (CET: shadow stack pointers for rings 0,1,2)

| HDC (Hardware Duty Cycling) state

| UINTR (User-Mode Interrupts) state

| LBR (Last Branch Record) state

| HWP (Hardware P-state control) state

| AMX tile configuration state: TILECFG || rowspan="3" {{yes|XCR0}}

| AMX tile data registers: tmm0-tmm7

| APX extended general-purpose registers: r16-r31

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| Lightweight Profiling (LWP) (AMD only) || {{yes|XCR0}}

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved){{efn|For the XCR0 and IA32_XSS registers, bit 63 is reserved specifically for bit vector expansion - this precludes the existence of a state-component 63.}}

! Short || Feature

! Short || Feature

| sgx1 || SGX1 leaf functions

| EXINFO || MISCSELECT: report information about page fault and general protection exception that occurred inside enclave

| rowspan=8 | MaxEnclave­Size_Not64|| rowspan=8 | Log2 of maximum enclave size supported in non-64-bit mode

! 0

| sgx2 || SGX2 leaf functions

| CPINFO || MISCSELECT: report information about control protection exception that occurred inside enclave

! 1

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 2

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 3

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 4

| oss || ENCLV leaves: EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 5

| || ENCLS leaves: ETRACKC, ERDINFO, ELDBC, ELDUC

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 6

| || ENCLU leaf: EVERIFYREPORT2

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 7

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| rowspan=8 | MaxEnclave­Size_64 || rowspan=8 | Log2 of maximum enclave size supported in 64-bit mode

! 8

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 9

| || ENCLS leaf: EUPDATESVN

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 10

| || ENCLU leaf: EDECSSA

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 11

| 256BITSGX || ENCLU leaf functions EGETKEY256 and EREPORT2

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 12

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 13

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 14

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 15

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

!
31:16
 

! Short || Feature

| style="background:lightgrey" | (INIT) || style="text-align:center; background:lightgrey;" | (must be 0){{efn|text=For the copy of the SECS that exists inside an exclave, bit 0 (INIT) of SECS.ATTRIBUTES is used to indicate that the enclave has been initialized with ENCLS[EINIT]. This bit must be 0 in the SECS copy that is given as input to ENCLS[CREATE].}}

| rowspan=12 colspan=2 style="text-align:center; background:lightgrey;"| (reserved)

! 0

| DEBUG || Permit debugger to read and write enclave data using EDBGRD and EDBGWR

! 1

| MODE64BIT || 64-bit-mode enclave

! 2

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 3

| PROVISIONKEY || Provisioning key available from EGETKEY

! 4

| EINITTOKEN_KEY || EINIT token key available from EGETKEY

! 5

| CET || CET (Control-Flow Enforcement Technology) attributes enable

! 6

| KSS || Key Separation and Sharing

! 7

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 8

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 9

| AEXNOTIFY || Threads inside enclave may receive AEX notificationsIntel, [https://cdrdv2-public.intel.com/736463/aex-notify-white-paper-public.pdf Asynchronous Enclave Exit Notify and the EDECCSSA User Leaf Function], 30 Jun 2022. [https://web.archive.org/web/20221121073302/https://cdrdv2-public.intel.com/736463/aex-notify-white-paper-public.pdf Archived] on 21 Nov 2022.

! 10

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

!
31:11
 

! EAX

! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="5" |

! EBX

! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="5" |

! ECX

! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="5" |

! EDX

! Bits

| Sub-leaf type:

• 0000: Invalid
• 0001: EPC section
• other: reserved

| rowspan=3 | Bits 51:32 of physical base address of EPC section

| EPC Section properties:

• 0000: Invalid
• 0001: Has confidentiality, integrity, and replay protection
• 0010: Has confidentiality protection only
• 0011: Has confidentiality and integrity protection
• other: reserved

| rowspan=3 | Bits 51:32 of size of EPC section

! 3:0

| style="text-align:center; background:lightgrey;"| (reserved)

| style="text-align:center; background:lightgrey;"| (reserved)

!
11:4
 

| rowspan=2 | Bits 31:12 of physical base address of EPC section

| rowspan=2 | Bits 31:12 of size of EPC section

!
19:12
 

| style="text-align:center; background:lightgrey;"| (reserved)

| style="text-align:center; background:lightgrey;"| (reserved)

!
31:20
 

! Short || Feature

| || CR3 filtering supported

| topaout || ToPA (Table of Physical Addresses) output mechanism for trace packets supported

! 0

| || Configurable PSB (Packet Stream Boundary) packet rate and Cycle-Accurate Mode (CYC packets) supported

| mentry || ToPA tables can contain hold multiple output entries

! 1

| || IP filtering, TraceStop filtering and preservation of PT MSRs across warm reset supported

| snglrngout || Single-Range Output scheme supported

! 2

| || MTC (Mini Time Counter) timing packets supported, and suppression of COFI (Change of Flow Instructions) packets supported.

| || Output to Trace Transport subsystem supported

! 3

| ptwrite || PTWRITE instruction supported

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 4

| || Power Event Trace supported

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 5

| || Preservation of PSB and PMI (performance monitoring interrupt) supported

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 6

| || Event Trace packet generation supported

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 7

| || TNT (Branch Taken-Not-Taken) packet generation disable supported.

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 8

| || PTTT (Processor Trace Trigger Tracing) supported

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 9

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

!
30:10
 

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

|

| IP (Instruction Pointer) format for trace packets that contain IP payloads:

• 0=RIP (effective-address IP)
• 1=LIP (linear-address IP, with CS base address added)

! 31

| Processor Base Frequency (in MHz){{efn|name=unsupp_1516}}

| Processor Maximum Frequency (in MHz){{efn|name=unsupp_1516}}

| Bus/Reference frequency (in MHz){{efn|name=unsupp_1516}}

! 15:0

| style="text-align:center; background:lightgrey;" | (reserved)

| style="text-align:center; background:lightgrey;" | (reserved)

| style="text-align:center; background:lightgrey;" | (reserved)

! 31:16

| SoC Vendor ID

| rowspan=3 | SoC Project ID

| rowspan=3 | SoC Stepping ID within an SoC project

! 15:0

| SoC Vendor ID scheme

• 0 : Vendor IDs assigned by Intel{{efn|text=As of May 2024, the following Vendor IDs are known to have been assigned by Intel:

{{(!}} class="wikitable sortable"

! ID

{{!}}-

{{!}} 1 {{

{{!)}}}}

• 1 : Industry standard enumeration scheme{{efn|text=As of May 2024, Intel documentation does not specify which "Industry Standard" enumeration scheme to use for the Vendor ID in EBX[15:0] if EBX[16] is set.}}

! 16

| style="text-align:center; background:lightgrey;" | (reserved)

! 31:17

! Short || Feature

! Short || Feature

| || Key Locker restriction of CPL0-only supported

| aes_kle || AES "Key Locker" Instructions enabled

| || No-backup parameter to LOADIWKEY supported

! 0

| || Key Locker restriction of no-encrypt supported

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| || KeySource encoding of 1 (randomization of internal wrapping key) supported

! 1

| || Key Locker restriction of no-decrypt supported

| aes_wide_kl || AES "Wide Key Locker" Instructions

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 2

| || (Process Restriction){{efn|text=As of April 2024, the "Process Restriction" bit is listed only in Intel TDX documentation and is not set in any known processor.}}

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 3

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| kl_msrs || "Key Locker" MSRs

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 4

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

!
31:5
 

! Short

! Short

! Short

| total_tile_bytes || Size of all tile registers, in bytes (8192)

| bytes_per_row || (64)

| max_rows || (16)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 15:0

| bytes_per_tile || Size of one tile, in bytes (1024)

| max_names || Number of tile registers (8)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 31:16

! Short

! Short

! Short

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| tmul_maxk || Maximum number of rows or columns (16)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 7:0

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| tmul_maxn || Maximum number of bytes per column (64)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 15:8

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 23:16

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 31:24

! Short

! Short

! Short

| amx-int8 || 8-bit integer support

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 0

| amx-bf16 || bfloat16 support

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 1

| amx-complex || Complex number support

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 2

| amx-fp16 || float16 support

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 3

| amx-fp8 || float8 support

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 4

| amx-transpose || Transposition instruction support

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 5

| amx-tf32 || tf32/fp19 support

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 6

| amx-avx512 || AMX-AVX512 support

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 7

| amx-movrs || AMX-MOVRS support

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 8

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 31:9

! Feature

| || AVX10 Converged Vector ISA version (≥1)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved as 111b){{efn|These three bits were originally designed to indicate the "supported vector width", with bit 16 indicating 128-bit vector support, bit 17 for 256-bit, and bit 18 for 512-bit. Shortly after the announcement of AVX10.1, Intel dropped plans for 128-bit vector only support (AVX10/128),Intel, [https://cdrdv2-public.intel.com/828964/355989-intel-avx10.1-spec.pdf Intel Advanced Vector Extensions 10 Architecture Specification], order no. 355989-003US, July 2024, see revision history on page 13. [https://web.archive.org/web/20241008214903/https://cdrdv2-public.intel.com/828964/355989-intel-avx10.1-spec.pdf Archived] on 8 Oct 2024. leaving only 256-bit (AVX10/256) or 512-bit (AVX10/512) maximum vector widths as supported. With AVX10.2, Intel dropped the vector width distinction entirely, instead mandating 512-bit vector support. As the only shipping AVX10.1 CPUs were based on Granite Rapids, which was a P-core design (AVX10/512 supported), no CPUs with AVX10/256 were ever shipped.}}

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! Feature

| (VPMM) || (Vector-Extension Packed Matrix Multiplication)Intel, [https://cdrdv2-public.intel.com/853286/intel-tdx-module-base-spec-348549006.pdf Trust Domain Extensions (Intel TDX) Module Base Architecture Specification], order no. 348549-006US, April 2025. [https://web.archive.org/web/20250424190213/https://cdrdv2-public.intel.com/853286/intel-tdx-module-base-spec-348549006.pdf Archived] on 24 Apr 2025.

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! Feature

! Short

! Feature

! Short

! Feature

! Short

! Feature

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 3:0

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| k1om || K1OM

! 4

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 31:5

! Feature

! Short

! Feature

| fpu || {{some|align=left|Onboard x87 FPU}}

| lahf_lm || LAHF/SAHF in long mode

! 0

| vme || {{some|align=left|Virtual mode extensions (VIF)}}

| cmp_legacy || Hyperthreading not valid

! 1

| de || {{some|align=left|Debugging extensions (CR4 bit 3)}}

| svm || Secure Virtual Machine

! 2

| pse || {{some|align=left|Page Size Extension}}

| extapic || Extended APIC space

! 3

| tsc || {{some|align=left|Time Stamp Counter}}

| cr8_legacy || CR8 in 32-bit mode

! 4

| msr || {{some|align=left|Model-specific registers}}

| abm/lzcnt || Advanced bit manipulation (LZCNT and POPCNT)

! 5

| pae || {{some|align=left|Physical Address Extension}}

| sse4a || SSE4a

! 6

| mce || {{some|align=left|Machine Check Exception}}

| misalignsse || Misaligned SSE mode

! 7

| cx8 || {{some|align=left|CMPXCHG8B (compare-and-swap) instruction}}

| 3dnowprefetch || PREFETCH and PREFETCHW instructions

! 8

| apic || {{some|align=left|Onboard Advanced Programmable Interrupt Controller}}

| osvw || OS Visible Workaround

! 9

| (syscall){{efn|text=The use of EDX bit 10 to indicate support for SYSCALL/SYSRET is only valid on AuthenticAMD Family 5 Model 7 CPUs (AMD K6, 250nm "Little Foot") - for all other processors, EDX bit 11 should be used instead.

These instructions were first introduced on Model 7AMD, [https://www.ardent-tool.com/CPU/docs/AMD/K6/20695.pdf AMD-K6 Processor Data Sheet], order no. 20695H/0, march 1998, section 24.2, page 283 - the CPUID bit to indicate their support was movedAMD, [https://www.ardent-tool.com/CPU/docs/AMD/K6/revs/21846h.pdf AMD-K6 Processor Revision Guide], order no. 21846H/0, June 1999, section 3.2.1, page 17 to EDX bit 11 from Model 8 (AMD K6-2) onwards.

| (SYSCALL/SYSRET, K6 only)

| ibs || Instruction Based Sampling

! 10

| syscall{{efn|On Intel CPUs, the CPUID bit for SYSCALL/SYSRET is only set if the CPUID instruction is executed in 64-bit mode.Intel, [https://kib.kiev.ua/x86docs/Intel/SDMs/325462-079.pdf Intel 64 and IA-32 Architectures Software Developer's Manual], order no. 325462-079, march 2023, table 3-8 on page 3-238}} || SYSCALL and SYSRET instructions

| xop || XOP instruction set

! 11

| mtrr || {{some|align=left|Memory Type Range Registers}}

| skinit || SKINIT/STGI instructions

! 12

| pge || {{some|align=left|Page Global Enable bit in CR4}}

| wdt || Watchdog timer

! 13

| mca || {{some|align=left|Machine check architecture}}

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 14

| cmov || {{some|align=left|Conditional move and FCMOV instructions}}

| lwp || Light Weight Profiling{{Citation |url=http://support.amd.com/us/Processor_TechDocs/43724.pdf |title=Lightweight Profiling Specification |publisher=AMD |date=August 2010 |access-date=2013-04-03 |url-status=dead |archive-url=https://web.archive.org/web/20121127061327/http://support.amd.com/us/Processor_TechDocs/43724.pdf | archive-date=2012-11-27 }}

! 15

| pat{{efn|name=ext1_edx_16_24|text=On some processors - Cyrix MediaGXm,Cyrix, [http://datasheets.chipdb.org/Cyrix/detect.pdf Cyrix CPU Detection Guide], rev 1.01, oct 2, 1997, page 12 several Geodes (NatSemi Geode GXm, GXLV, GX1; AMD Geode GX1AMD, [https://www.amd.com/system/files/TechDocs/goede_gx1_databook-rev5.pdf Geode GX1 Processor Data Book], rev 5.0, december 2003, pages 202 and 226. [https://web.archive.org/web/20200420011559/https://www.amd.com/system/files/TechDocs/goede_gx1_databook-rev5.pdf Archived] on 20 Apr 2020.) and Transmeta CrusoeTransmeta, [http://datasheets.chipdb.org/Transmeta/Crusoe/Crusoe_CPUID_5-7-02.pdf Processor Recognition], 2002-05-07, page 5 - EDX bits 16 and 24 have a different meaning:

• Bit 16: Floating-point Conditional Move (FCMOV) supported
• Bit 24: 6x86MX Extended MMX instructions supported

}}

| {{some|align=left|Page Attribute Table}}

| fma4 || 4-operand fused multiply-add instructions

! 16

| pse36 || {{some|align=left|36-bit page size extension}}

| tce || Translation Cache Extension

! 17

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 18

| ecc || "Athlon MP" / "Sempron" CPU brand identification{{efn|text=EDX bit 19 is used for CPU brand identification on AuthenticAMD Family 6 processors only - the bit is, combined with processor signature and FSB speed, used to identify processors as either multiprocessor-capable or carrying the Sempron brand name.AMD, [https://web.archive.org/web/20060626212818/http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/20734.pdf Processor Recognition Application Note], pub.no. 20734, rev. 3.13, december 2005. Section 2.2.2 (p.20) and Section 3 (pages 33 to 40) provide details on how {{nowrap|1=CPUID.(EAX=8000_0001):EDX[bit 19]}} should be used to identify processors. Section 3 also provides information on AMD's brand name string MSRs. Archived from the [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/20734.pdf original] on Jun 26, 2006.}}

| nodeid_msr || NodeID MSR (C001_100C)AMD, [https://www.amd.com/system/files/TechDocs/31116.pdf Family 10h BKDG], document no. 31116, rev 3.62, jan 11, 2013, p. 388 - lists the NodeId bit. [https://web.archive.org/web/20190116230101/https://www.amd.com/system/files/TechDocs/31116.pdf Archived] on 16 Jan 2019.

! 19

| nx || NX bit

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 20

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| tbm || Trailing Bit Manipulation

! 21

| mmxext || Extended MMX

| topoext || Topology Extensions

! 22

| mmx || {{some|align=left|MMX instructions}}

| perfctr_core || Core performance counter extensions

! 23

| fxsr{{efn|name=ext1_edx_16_24}} || {{some|align=left|FXSAVE, FXRSTOR instructions, CR4 bit 9}}

| perfctr_nb || Northbridge performance counter extensions

! 24

| fxsr_opt || FXSAVE/FXRSTOR optimizations

| (StreamPerfMon) || (Streaming performance monitor architecture){{efn|text=ECX bit 25 is listed as StreamPerfMon in revision 3.20 of AMD APMAMD, [https://kib.kiev.ua/x86docs/AMD/AMD64/24594_APM_v3-r3.20.pdf AMD64 Architecture Programmer's Manual Volume 3], pub. no. 24594, rev 3.20, may 2013, page 579 - lists the StreamPerfMon bit only - it is listed as reserved in later revisions. The bit is set on Excavator and Steamroller CPUs only.}}

! 25

| pdpe1gb || Gigabyte pages

| dbx || Data breakpoint extensions

! 26

| rdtscp || RDTSCP instruction

| perftsc ||Performance timestamp counter (PTSC)

! 27

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| pcx_l2i || L2I perf counter extensions

! 28

| lm || Long mode

| monitorx || MONITORX and MWAITX instructions

! 29

| 3dnowext || Extended 3DNow!

| addr_mask_ext || Address mask extension to 32 bits for instruction breakpoints

! 30

| 3dnow || 3DNow!

| colspan="2" style="text-align:center; background:lightgrey;" | (reserved)

! 31

| colspan=2 | Number of instruction TLB entries{{efn|name=tmta_tlbsize|On Transmeta CPUs, the value FFh is used to indicate a 256-entry TLB.}}

| colspan=2 | Cache line size in bytes

! 7:0

| colspan=2 | instruction TLB associativity{{efn|name=ex2_assoc|text=For the associativity fields of leaf 80000005h, the following values are used:

{{(!}} class="wikitable sortable"

! Value

{{!}}-

{{!}} 0 {{

{{!}}-

{{!}} 1 {{

{{!}}-

{{!}} 2 to FEh {{

{{!}}-

{{!}} FFh {{

{{!)}}

}}

| colspan=2 | Number of cache lines per tag

! 15:8

| colspan=2 | Number of data TLB entries{{efn|name=tmta_tlbsize}}

| colspan=2 | Cache associativity{{efn|name=ex2_assoc}}

! 23:16

| colspan=2 | Data TLB associativity{{efn|name=ex2_assoc}}

| colspan=2 | Cache size in kilobytes

! 31:24

! Short || Feature

| MCAOverflowRecov || MCA (Machine Check Architecture) overflow recovery support

| TS || Temperature Sensor

! 0

| SUCCOR || Software uncorrectable error containment and recovery capability

| FID || Frequency ID Control

! 1

| HWA || Hardware assert support (MSRs C001_10C0 to C001_10DF

| VID || Voltage ID Control

! 2

| ScalableMca || Scalable MCA supported

| TTP || THERMTRIP

! 3

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| TM || Hardware thermal control (HTC) supported

! 4

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| STC || Software thermal control (STC) supportedAMD, [https://www.amd.com/system/files/TechDocs/31116.pdf BKDG for AMD Family 10h Processors], pub.no. 31116, rev 3.62, jan 11, 2013, page 392. [https://web.archive.org/web/20190116230101/https://www.amd.com/system/files/TechDocs/31116.pdf Archived] on 16 Jan 2019.

! 5

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| 100MHzSteps || 100 MHz multiplier control

! 6

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| HwPstate || Hardware P-state control (MSRs C001_0061 to C001_0063)

! 7

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| TscInvariant || Invariant TSC - TSC (Time Stamp Counter) rate is guaranteed to be invariant across all P-states, C-states and sop grant transitions.

! 8

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| CPB || Core Performance Boost

! 9

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| EffFreqRO || Read-only effective frequency interface (MSRs C000_00E7 and C000_00E8)

! 10

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| ProcFeedback­Interface || Processor Feedback Interface supported

! 11

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| ProcPower­Reporting || Processor power reporting interface supported

! 12

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| Connected­Standby || Connected StandbyAMD, [https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip PPR For AMD Family 19h Model 61h rev B1 procesors], pub.no. 56713, rev 3.05, Mar 8, 2023, pages 99-100. [https://web.archive.org/web/20230425231817/https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip Archived] on 25 Apr 2023.

! 13

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| RAPL || Running Average Power Limit

! 14

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| FastCPPC || Fast CPPC (Collaborative Processor Performance Control) supported

! 15

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

!
31:16
 

! Short || Feature

| NumberOfMonitors || Number of Processor Feedback MSR pairs available, starting from MSR C001_0080 onwardsAMD, [https://www.amd.com/system/files/TechDocs/48751_16h_bkdg.pdf BKDG for AMD Family 16h Models 00-0Fh processors], pub.no. 48571, rev 3.03, Feb 19, 2015, page 482. [https://web.archive.org/web/20190116230055/https://www.amd.com/system/files/TechDocs/48751_16h_bkdg.pdf Archived] on 16 Jan 2019.

| rowspan=3 | CpuPwrSample­TimeRatio

| rowspan=3 | Ratio of compute unit power accumulator sample period to TSC counter period.

! 7:0

| Version || Processor Feedback Capabilities version

! 15:8

| MaxWrapTime || Maximum time between reads (in milliseconds) that software should use to avoid two wraps.

! 31:16

| clzero || CLZERO instruction

| retired_instr || Retired instruction count MSR (C000_00E9h) supported

| xrstor_fp_err || XRSTOR restores FP errors

| invlpgb || INVLPGB and TLBSYNC instructions

| rdpru || RDPRU instruction

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| mbe || Memory Bandwidth Enforcement

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| mcommit || MCOMMIT instruction

| wbnoinvd || WBNOINVD instruction

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| IBPB || Indirect Branch Prediction Barrier (performed by writing 1 to bit 0 of PRED_CMD (MSR 049h))

| wbinvd_int || WBINVD and WBNOINVD are interruptible

| IBRS || Indirect Branch Restricted Speculation

| STIBP || Single Thread Indirect Branch Prediction mode

| IbrsAlwaysOn || IBRS mode has enhanced performance and should be left always on

| StibpAlwaysOn || STIBP mode has enhanced performance and should be left always on

| ibrs_preferred || IBRS preferred over software

| ibrs_same_mode_protection || IBRS provides Same Mode Protection

| no_efer_lmsle || EFER.LMSLE is unsupported{{efn|text=The LMSLE (Long Mode Segment Limit Enable) feature does not have its own CPUID flag and is detected by checking CPU family and model. It was introduced in AuthenticAMD Family 0Fh Model 14hAMD, [https://www.amd.com/system/files/TechDocs/26094.PDF BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD Opteron Processors], publication #26094, rev 3.30, feb 2006, pages 29-30 (lists Athlon 64 revision differences, including LMSLE) ([https://web.archive.org/web/20190116230059/https://www.amd.com/system/files/TechDocs/26094.PDF archived] on 16 Jan 2019), and [https://www.amd.com/system/files/TechDocs/25759.pdf Revision Guide for AMD Athlon 64 and AMD Opteron Processors], publication #25759, rev 3.79, july 2009, pages 7-8 (lists Athlon 64 revision IDs) ([https://web.archive.org/web/20190118074904/https://www.amd.com/system/files/TechDocs/25759.pdf archived] on 18 Jan 2019).

(90nm Athlon64/Opteron) CPUs and is present in all later AMD CPUs - except the ones with the 'no_efer_lmsle' flag set.}}

| invlpgb_nested || INVLPGB support for nested pages

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| ppin || Protected Processor Inventory Number -

PPIN_CTL (C001_02F0) and PPIN (C001_02F1) MSRs are present

| ssbd || Speculative Store Bypass Disable

| ssbd_legacy || Speculative Store Bypass Disable Legacy

| ssbd_no || Speculative Store Bypass Disable Not Required

| cppc || Collaborative Processor Performance Control

| psfd || Predictive Store Forward Disable

| btc_no || Branch Type Confusion: Processor not affected

| IBPB_RET || IBPB (see bit 12) also clears return address predictor

| branch_sampling || Branch Sampling SupportAMD, [https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip PPR for AMD Family 19h Model 01h, Revision B1 Processors, Volume 1 of 2], document no. 55898, rev 0.50, may 27, 2021, page 98 - lists branch-sampling bit. [https://web.archive.org/web/20220724144832/https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Archived] on Jul 24, 2022

! EAX

! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="7" |

! ECX

! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="7" |

! EDX

! Bits

| Number of Physical Address Bits

| Number of Physical Threads in processor (minus 1)

| rowspan="3" style="max-width:18em" | Maximum page count for INVLPGB instruction

! style="padding-top:1em; padding-bottom:1em" | 7:0

| rowspan="2" | Number of Linear Address Bits

| style="text-align:center; background:lightgrey;"| (reserved)

! 11:8

| APIC ID Size

! 15:12

| rowspan="2" | Guest Physical Address Size{{efn|text=A value of 0 indicates that the "Guest Physical Address Size" is the same as the "Number Of Physical Address Bits", specified in EAX[7:0].}}

| Performance Timestamp Counter size

| rowspan="3" style="max-width:18em" | Maximum ECX value recognized by RDPRU instruction

! 17:16

| rowspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! 23:18

| style="text-align:center; background:lightgrey;"| (reserved)

! style="padding-top:1em; padding-bottom:1em" | 31:24

! EAX

! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="4" |

! EBX

! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="4" |

! ECX

! Bits

| SVM Revision Number

| rowspan="3" | Number of available ASIDs
(address space identifiers)

| rowspan="3" style="text-align:center; background:lightgrey;" | (reserved)

! 7:0

| style="text-align:center; background:lightgrey;" | (hypervisor){{efn|text=Early revisions of AMD's "Pacifica" documentation listed EAX bit 8 as an always-zero bit reserved for hypervisor use.AMD, [https://web.archive.org/web/20110613111809/http://www.mimuw.edu.pl/~vincent/lecture6/sources/amd-pacifica-specification.pdf AMD64 Virtualization Codenamed "Pacifica" Technology], publication no. 33047, rev 3.01, May 2005, appendix B, page 81. Archived on Jun 13, 2011.

Later AMD documentation, such as #25481 "CPUID specification" rev 2.18AMD, [https://kib.kiev.ua/x86docs/AMD/AMD-CPUID-Spec/25481-r2.18.pdf CPUID specification], publication #25481, revision 2.18, jan 2006, page 18. and later, only lists the bit as reserved.

In rev 2.30AMD, [https://kib.kiev.ua/x86docs/AMD/AMD-CPUID-Spec/25481-r2.34.pdf CPUID specification], publication #25481, revision 2.34, sep 2010, pages 5 and 11. and later, a different bit is listed as reserved for hypervisor use: {{nowrap|1=CPUID.(EAX=1):ECX[bit 31].}}

! 8

| style="text-align:center; background:lightgrey;" | (reserved)

! 31:9

| NP || Rapid Virtualization Indexing (Nested Paging)

| LbrVirt || LBR (Last Branch Records) virtualization

| SVML || SVM-Lock

| NRIPS || nRIP (next sequential instruction pointer) save on #VMEXIT supported

| TscRateMsr || MSR-based TSC rate control (MSR C000_0104h)

| VmcbClean || VMCB (Virtual Machine Control Block) clean bits supported

| FlushByAsid || TLB flush events (e.g. CR3 writes, CR4.PGE toggles) only flush the TLB entries of the current ASID (address space ID)

| DecodeAssist || Decode assists supported

| PmcVirt || PMC (Performance Monitoring Counters) virtualization

| style="background:lightgrey;"| (SseIsa10Compat){{efn|text=EDX bit 9 is briefly listed in some older revisions of AMD's document #25481 "CPUID Specification", and is set only in some AMD Bobcat CPUs.Instlatx64, [http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0500F10_K14_Bobcat_CPUID.txt AMD E-350 CPUID dump] - has CPUID.(EAX=8000000A):EDX[9] set.

Rev 2.28 of #25481 lists the bit as "Ssse3Sse5Dis"AMD, [https://kib.kiev.ua/x86docs/AMD/AMD-CPUID-Spec/25481-r2.28.pdf CPUID specification], publication #25481, revision 2.28, apr 2008, page 21. - in rev 2.34, it is listed as having been removed from the spec at rev 2.32 under the name "SseIsa10Compat".AMD, [https://kib.kiev.ua/x86docs/AMD/AMD-CPUID-Spec/25481-r2.34.pdf CPUID specification], publication #25481, revision 2.34, sep 2010, page 5 - lists "SseIsa10Compat" as having been dropped in November 2009.

| style="text-align:center; background:lightgrey;"| (reserved)

| PauseFilter || PAUSE intercept filter supported

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| PauseFilter­Threshold || PAUSE filter cycle count threshold supported

| AVIC || AMD Advanced Virtualized Interrupt Controller supported

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| VMSAVEvirt || VMSAVE and VMLOAD virtualization

| VGIF || Global Interrupt Flag (GIF) virtualization

| GMET || Guest Mode Execution Trap

| x2AVIC || x2APIC mode supported for AVIC

| SSSCheck || SVM Supervisor shadow stack restrictions

| SpecCtrl || SPEC_CTRL (MSR 2E0h) virtualization

| ROGPT || Read-Only Guest Page Table supported

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| HOST_MCE_­OVERRIDE || Guest mode Machine-check exceptions when host CR4.MCE=1 and guest CR4.MCE=0 cause intercepts instead of shutdowns

| TlbiCtl || INVLPGB/TLBSYNC hypervisor enable in VMCB and TLBSYNC intercept support

| VNMI || NMI (Non-Maskable interrupt) virtualization

| IbsVirt || IBS (Instruction-Based Sampling) virtualization

| ExtLvtOffset­FaultChg || Read/Write fault behavior for extended LVT offsets (APIC addresses 0x500-0x530) changed to Read Allowed, Write #VMEXITAMD, [https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip PPR for AMD Family 19h Model 61h, Revision B1 processors], document no. 56713, rev 3.05, mar 8 2023, page 102. [https://web.archive.org/web/20230425231817/https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip Archived] on Apr 25, 2023.

| VmcbAddr­ChkChg || VMCB address check change

| BusLock­Threshold || Bus Lock Threshold

| IdleHlt­Intercept || Idle HLT (HLT instruction executed while no virtual interrupt is pending) intercept

| Enhanced­Shutdown­Intercept || Support for EXITINFO1 on shutdown intercept, and nested shutdown intercepts will result in a non-interceptible shutdown.

| SME || Secure Memory Encryption

| SEV || Secure Encrypted Virtualization

| PageFlushMSR || Page flush MSR (C001_011Eh) supported

| SEV-ES || SEV Encrypted State

| SEV-SNP || SEV Secure Nested Paging

| VMPL || VM Privilege Levels

| RMPQUERY || RMPQUERY instruction supported

| VmplSSS || VMPL Supervisor shadow stack supported

| SecureTSC || Secure TSC supported

| TscAux­Virtualization || Virtualization of TSC_AUX MSR (C000_0103) supported

| HwEnfCacheCoh || Hardware cache coherency across encryption domains enforced

| 64BitHost || SEV Guest execution only allowed from 64-bit host

| Restricted­Injection || SEV-ES guests can refuse all event-injections except #HV (Hypervisor Injection Exception)

| Alternate­Injection || SEV-ES guests can use an encrypted VMCB field for event-injection

| DebugVirt || Full debug state virtualization supported for SEV-ES and SEV-SNP guests

| PreventHostIBS || Prevent host IBS for a SEV-ES guest

| VTE || Virtual Transparent Encryption for SEV

| Vmgexit­Parameter || VMGEXIT parameter is supported (using the RAX register)

| VirtualTomMsr || Virtual TOM (top-of-memory) MSR (C001_0135) supported

| IbsVirtGuestCtl || IBS virtualization is supported for SEV-ES and SEV-SNP guests

| PmcVirtGuestCtl || PMC virtualization is supported for SEV-ES and SEV-SNP guests

| RMPREAD || RMPREAD instruction supported

| GuestIntercept­Control || Guest Intercept control supported for SEV-ES guests

| SegmentedRmp || Segmented RMP (Reverse-Map Table) supported

| VmsaRegProt || VMSA (VM Save Area) register protection supported

| SmtProtection || SMT Protection supported

| SecureAvic || Secure AVIC supported

| AllowedSEV­features || ALLOWED_SEV_FEATURES_MASK field in VMCB (offset 138h) supported

| SVSMComm­PageMSR || SVSM (Secure VM Service ModuleAMD, [https://www.amd.com/system/files/TechDocs/58019_1.00.pdf Secure VM Service Module for SEV-SNP Guests], pub.no #58019, rev 1.00, Jul 2023, page 13. [https://web.archive.org/web/20230805094438/https://www.amd.com/system/files/TechDocs/58019_1.00.pdf Archived] on 5 Aug 2023.) communication page MSR (C001_F000h) supported

| NestedVirt­SnpMsr || VIRT_RMPUPDATE (C001_F001h) and VIRT_PSMASH (C001_F002h) MSRs supported

| HvInUse­WrAllowed || Writes to Hypervisor-owned paged allowed when marked in-use

| IbpbOnEntry || IBPB on entry to virtual machine supported

| C-bit (encryption enable bit) location in page table entry

| rowspan="4" style="max-width:18em" | Maximum ASID value that can be used for a SEV-enabled guest (maximum number of encrypted guests that can be supported simultaneously)

| rowspan="4" style="max-width:18em" | Minimum ASID value for a guest that is SEV-enabled but not SEV-ES-enabled

! 5:0

| Physical address width reduction when memory encryption is enabled

! 11:6

| Number of VMPLs (VM Privilege Levels) supported

! 15:12

| style="text-align:center; background:lightgrey;"| (reserved)

! 31:16

! Feature

| NoNestedDataBp || Processor ignores nested data breakpoints

| FsGsKernelGsBase­NonSerializing || WRMSR to the FS_BASE, GS_BASE and KernelGSBase MSRs is non-serializingAMD, [https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip PPR for AMD Family 19h Model 61h, Revision B1 processors], document no. 56713, rev 3.05, mar 8 2023, page 116. [https://web.archive.org/web/20230425231817/https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip Archived] on Apr 25, 2023.

| LFenceAlways­Serializing || LFENCE is always dispatch serializing

| SmmPgCfgLock || SMM paging configuration lock supported

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| NullSelect­ClearsBase || Null segment selector loads also clear the destination segment register base and limit

| UpperAddress­Ignore || Upper Address Ignore is supported

| AutomaticIBRS || Automatic IBRS

| NoSmmCtlMSR || SMM_CTL MSR (C0010116h) is not supported

| FSRS || Fast short {{nowrap|REP STOSB}} supported

| FSRC || Fast short {{nowrap|REPE CMPSB}} supported

| PMC2Precise­Retire || PreciseRetire performance counter control bit (MSR C0010002h bit 43) supported

| PrefetchCtlMsr || PrefetchControl MSR (C0000108h) is supported

| L2TlbSIzeX32 || If set, L2 TLB sizes (leaf 80000006h) are encoded as multiples of 32

| AMD_ERMSB || Processor supports AMD implementation of Enhanced {{nowrap|REP MOVSB}} and {{nowrap|REP STOSB}}

| OPCODE_0F017_­RECLAIM || Reserves opcode 0F 01 /7 for AMD use, returning #UD.AMD, [https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/software-optimization-guides/57254-PUB_3.00.zip Processor Programming Reference (PPR) for AMD Family 1Ah Model 24h, Revision B0 Processors], order no. 57254, rev 3.00, Sep 26, 2024, pages 102, 118, 119 and 199.

| CpuidUserDis || CPUID disable for non-privileged software (#GP)

| EPSF || Enhanced Predictive Store Forwarding supported

| FAST_REP_SCASB || Fast Short REP SCASB supported

| PREFETCHI || Instruction Cache prefetch instructions supported

| FP512_­DOWNGRADE || Downgrade of 512-bit datapath to 256-bit supported.{{efn|text=If the downgrade from 512-bit to 256-bit datapath is enabled, then AVX-512 instructions that work on 512-bit data items will be split into two 256-bit parts that will be issued over two consecutive cycles. This datapath downgrade can help improve power efficiency for some workloads.AMD, [https://www.amd.com/content/dam/amd/en/documents/epyc-business-docs/white-papers/5th-gen-amd-epyc-processor-architecture-white-paper.pdf 5th Gen AMD EPYC Processor Architecture], First Edition, October 2024, page 9.}}

| WL_CLASS_­SUPPORT || Support for workload-based heuristic feedback to OS for scheduling decisions

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| ERAPS || Enhanced Return Address Predictor Security (see also EBX[23:16] "RapSize")

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| SBPB || Selective Branch Predictor Barrier supportedAMD, [https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf Technical Update Regarding Speculative Return Stack Overflow], rev 2.0, feb 2024. [https://web.archive.org/web/20240412225347/https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf Archived] on Apr 12, 2024.

| IBPB_BRTYPE || IBPB flushes all branch type predictions

| SRSO_NO || CPU is not subject to SRSO (Speculative Return Stack Overflow) vulnerability

| SRSO_USER_­KERNEL_NO || CPU is not subject to SRSO vulnerability across user/kernel boundary

| SRSO_MSR_FIX || SRSO can be mitigated by setting bit 4 of BP_CFG (MSR C001_102E)

| MicrocodePatchSize || The size of the Microcode patch in 16-byte multiples. If 0, the size of the patch is at most 5568 (15C0h) bytes

| RapSize || Return Address Predictor Size.
RapSize * 8 is the minimum number of CALL instructions without matching RET instructions that are needed to flush the Return Address Predictor.

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

! Feature

| sm2{{efn|name=nehemiah_special|text=On VIA Nehemiah and Antaur CPUs (CentaurHauls Family 6 Model 9 only),VIA, [http://datasheets.chipdb.org/VIA/Nehemiah/VIA%20C3%20Nehemiah%20Datasheet%20R113.pdf C3 Nehemiah Processor Datasheet], rev 1.13, Sep 29, 2004, page 21 bits 0,1,4,5 are used differently:

• Bit 0: Alternate Instruction Set (AIS) present
• Bit 1: AIS enabled
• Bit 4: LongHaul MSR (MSR 0x110A) present
• Bit 5: FEMMS instruction (opcode {{nowrap|0F 0E}}) present

}}

|| GMI SM2 instruction present

| sm2_en{{efn|name=nehemiah_special}} || SM2 enabled

| rng || PadLock RNG present: XSTORE and {{nowrap|REP XSTORE}} instructions

| rng_en || RNG enabled

| ccs{{efn|name=nehemiah_special}} || GMI SM3/SM4 instructions present: CCS_HASH and CCS_ENCRYPT

| ccs_en{{efn|name=nehemiah_special}} || SM3/SM4 instructions enabled

| xcrypt || PadLock Advanced Cryptographic Engine (ACE, using AES cipher) present: {{nowrap|REP XCRYPT(ECB,CBC,CFB,OFB)}} instructions

| xcrypt_en || ACE enabled

| ace2 || ACE v2 present: {{nowrap|REP XCRYPTCTR}} instruction, as well as support for digest mode and misaligned data for ACE's {{nowrap|REP XCRYPT*}} instructions.

| ace2_en || ACE v2 enabled

| phe || PadLock Hash Engine (PHE): {{nowrap|REP XSHA1}} and {{nowrap|REP XSHA256}} instructions

| phe_en || PHE enabled

| pmm || PadLock Montgomery Multiplier (PMM): {{nowrap|REP MONTMUL}} instruction

| pmm_en || PMM enabled

| colspan="2" style="text-align:center; background:lightgrey;"| (reserved)

| zx_fma || FMA supported

| parallax || Adaptive P-state control present

| parallax_en || Adaptive P-state control enabled

| overstress || Overstress feature for auto overclock present

| overstress_en || Overstress feature for auto overclock enabled

| tm3 || Thermal Monitor 3 present

| tm3_en || Thermal Monitor 3 enabled

| rng2 || RNG v2 - second generation RNG present: REP XRNG2 instruction

| rng2_en || RNG v2 enabled

| sem || SME feature present

| phe2 || PHE v2: SHA384 and SHA512 present

| phe2_en || PHE v2 enabled

| xmodx || RSA instructions present: XMODEXP and MONTMUL2 instructions

| xmodx_en || RSA instructions enabled

| vex || VEX instructions present

| vex_en || VEX instructions enabled

| stk || STK is present