Template:Processor technologies
{{Navbox
| name = Processor technologies
| title = Processor technologies
| listclass = hlist
| state = {{{state|autocollapse}}}
| group1 = Models
| list1 =
- Abstract machine
- Stored-program computer
- Finite-state machine
- with datapath
- Hierarchical
- Deterministic finite automaton
- Queue automaton
- Cellular automaton
- Quantum cellular automaton
- Turing machine
- Alternating Turing machine
- Universal
- Post–Turing
- Quantum
- Nondeterministic Turing machine
- Probabilistic Turing machine
- Hypercomputation
- Zeno machine
- Belt machine
- Stack machine
- Register machines
- Counter
- Pointer
- Random-access
- Random-access stored program
| group2 = Architecture
| list2 =
- Microarchitecture
- Von Neumann
- Harvard
- modified
- Dataflow
- Transport-triggered
- Cellular
- Endianness
- Memory access
- NUMA
- HUMA
- Load–store
- Register/memory
- Cache hierarchy
- Memory hierarchy
- Virtual memory
- Secondary storage
- Heterogeneous
- Fabric
- Multiprocessing
- Cognitive
- Neuromorphic
| group3 = Instruction set
architectures
| list3 =
{{Navbox|subgroup
| group1 = Types
| list1 =
- Orthogonal instruction set
- CISC
- RISC
- Application-specific
- EDGE
- TRIPS
- VLIW
- EPIC
- MISC
- OISC
- NISC
- ZISC
- VISC architecture
- Quantum computing
- Comparison
- Addressing modes
| group2 = Instruction
sets
| list2 =
- Motorola 68000 series
- VAX
- PDP-11
- x86
- ARM
- Stanford MIPS
- MIPS
- MIPS-X
- Power
- POWER
- PowerPC
- Power ISA
- Clipper architecture
- SPARC
- SuperH
- DEC Alpha
- ETRAX CRIS
- M32R
- Unicore
- Itanium
- OpenRISC
- RISC-V
- MicroBlaze
- LMC
- System/3x0
- S/360
- S/370
- S/390
- z/Architecture
- Tilera ISA
- VISC architecture
- Epiphany architecture
- Others
}}
| group4 = Execution
| list4 =
{{Navbox|subgroup
| group1 = Instruction pipelining
| list1 =
| group2 = Hazards
| list2 =
| group3 = Out-of-order
| list3 =
| group4 = Speculative
| list4 =
}}
| group5 = Parallelism
| list5 =
{{Navbox|subgroup
| group1 = Level
| list1 =
- Bit
- Bit-serial
- Word
- Instruction
- Pipelining
- Scalar
- Superscalar
- Task
- Thread
- Process
- Data
- Vector
- Memory
- Distributed
| group2 = Multithreading
| list2 =
- Temporal
- Simultaneous
- Hyperthreading
- Simultaneous and heterogenous
- Speculative
- Preemptive
- Cooperative
| group3 = Flynn's taxonomy
| list3 =
}}
| group6 = Processor
performance
| list6 =
- Transistor count
- Instructions per cycle (IPC)
- Cycles per instruction (CPI)
- Instructions per second (IPS)
- Floating-point operations per second (FLOPS)
- Transactions per second (TPS)
- Synaptic updates per second (SUPS)
- Performance per watt (PPW)
- Cache performance metrics
- Computer performance by orders of magnitude
| group7 = Types
| list7 =
- Central processing unit (CPU)
- Graphics processing unit (GPU)
- GPGPU
- Vector
- Barrel
- Stream
- Tile processor
- Coprocessor
- PAL
- ASIC
- FPGA
- FPOA
- CPLD
- Multi-chip module (MCM)
- System in a package (SiP)
- Package on a package (PoP)
{{Navbox|subgroup
| group1 = By application
| list1 =
| group2 = Systems
on chip
| list2 =
- System on a chip (SoC)
- Multiprocessor (MPSoC)
- Cypress PSoC
- Network on a chip (NoC)
| group3 = Hardware
accelerators
| list3 =
- Coprocessor
- AI accelerator
- Graphics processing unit (GPU)
- Image processor
- Vision processing unit (VPU)
- Physics processing unit (PPU)
- Digital signal processor (DSP)
- Tensor Processing Unit (TPU)
- Secure cryptoprocessor
- Network processor
- Baseband processor
}}
| group8 = Word size
| list8 =
- 1-bit
- 4-bit
- 8-bit
- 12-bit
- 15-bit
- 16-bit
- 24-bit
- 32-bit
- 48-bit
- 64-bit
- 128-bit
- 256-bit
- 512-bit
- bit slicing
- others
- variable
| group9 = Core count
| list9 =
| group10 = Components
| list10 =
- Core
- Cache
- CPU cache
- Scratchpad memory
- Data cache
- Instruction cache
- replacement policies
- coherence
- Bus
- Clock rate
- Clock signal
- FIFO
{{Navbox|subgroup
| group1 = Functional
units
| list1 =
- Arithmetic logic unit (ALU)
- Address generation unit (AGU)
- Floating-point unit (FPU)
- Memory management unit (MMU)
- Load–store unit
- Translation lookaside buffer (TLB)
- Branch predictor
- Branch target predictor
- Integrated memory controller (IMC)
- Memory management unit
- Instruction decoder
| group2 = Logic
| list2 =
| group3 = Registers
| list3 =
- Processor register
- Status register
- Stack register
- Register file
- Memory buffer
- Memory address register
- Program counter
| group4 = Control unit
| list4 =
| group5 = Datapath
| list5 =
- Multiplexer
- Demultiplexer
- Adder
- Multiplier
- CPU
- Binary decoder
- Address decoder
- Sum-addressed decoder
- Barrel shifter
| group6 = Circuitry
| list6=
}}
| group11 = Power
management
| list11 =
- PMU
- APM
- ACPI
- Dynamic frequency scaling
- Dynamic voltage scaling
- Clock gating
- Performance per watt (PPW)
| group12 = Related
| list12 =
- History of general-purpose CPUs
- Microprocessor chronology
- Processor design
- Digital electronics
- Hardware security module
- Semiconductor device fabrication
- Tick–tock model
- Pin grid array
- Chip carrier
}}